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Thu, 14 Aug 2025 05:58:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v3 03/85] linux-user/aarch64: Generate ESR signal records Date: Thu, 14 Aug 2025 22:56:30 +1000 Message-ID: <20250814125752.164107-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814125752.164107-1-richard.henderson@linaro.org> References: <20250814125752.164107-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1755176366014124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 3 +++ linux-user/aarch64/signal.c | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index deb45eaa73..da89dbb095 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -33,6 +33,9 @@ static void signal_for_exception(CPUARMState *env, vaddr = addr) uint32_t syn =3D env->exception.syndrome; int si_code, si_signo; =20 + /* Let signal delivery see that ESR is live. */ + env->cp15.esr_el[1] =3D syn; + switch (syn_get_ec(syn)) { case EC_DATAABORT: case EC_INSNABORT: diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 668353bbda..ef97be3ac7 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -65,6 +65,13 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; =20 +#define TARGET_ESR_MAGIC 0x45535201 + +struct target_esr_context { + struct target_aarch64_ctx head; + uint64_t esr; +}; + #define TARGET_EXTRA_MAGIC 0x45585401 =20 struct target_extra_context { @@ -201,6 +208,14 @@ static void target_setup_fpsimd_record(struct target_f= psimd_context *fpsimd, } } =20 +static void target_setup_esr_record(struct target_esr_context *ctx, + CPUARMState *env) +{ + __put_user(TARGET_ESR_MAGIC, &ctx->head.magic); + __put_user(sizeof(*ctx), &ctx->head.size); + __put_user(env->cp15.esr_el[1], &ctx->esr); +} + static void target_setup_extra_record(struct target_extra_context *extra, uint64_t datap, uint32_t extra_size) { @@ -531,6 +546,9 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd =3D (struct target_fpsimd_context *)ctx; break; =20 + case TARGET_ESR_MAGIC: + break; /* ignore */ + case TARGET_SVE_MAGIC: if (sve || size < sizeof(struct target_sve_context)) { goto err; @@ -683,7 +701,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, uc.tuc_mcontext.__reserved), }; int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; - int zt_ofs =3D 0; + int zt_ofs =3D 0, esr_ofs =3D 0; int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0, zt_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -693,6 +711,15 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, fpsimd_ofs =3D alloc_sigframe_space(sizeof(struct target_fpsimd_contex= t), &layout); =20 + /* + * In user mode, ESR_EL1 is only set by cpu_loop while queueing the + * signal, and it's only valid for the one sync insn. + */ + if (env->cp15.esr_el[1]) { + esr_ofs =3D alloc_sigframe_space(sizeof(struct target_esr_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -754,6 +781,11 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, =20 target_setup_general_frame(frame, env, set); target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); + if (esr_ofs) { + target_setup_esr_record((void *)frame + esr_ofs, env); + /* Leave ESR_EL1 clear while it's not relevant. */ + env->cp15.esr_el[1] =3D 0; + } target_setup_end_record((void *)frame + layout.std_end_ofs); if (layout.extra_ofs) { target_setup_extra_record((void *)frame + layout.extra_ofs, --=20 2.43.0