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Thu, 14 Aug 2025 05:59:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v3 36/85] target/arm: Convert regime_has_2_ranges from switch to table Date: Thu, 14 Aug 2025 22:57:03 +1000 Message-ID: <20250814125752.164107-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814125752.164107-1-richard.henderson@linaro.org> References: <20250814125752.164107-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1755177081995124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 28 ---------------------------- target/arm/mmuidx-internal.h | 17 +++++++++++++++++ target/arm/mmuidx.c | 19 ++++++++++--------- 3 files changed, 27 insertions(+), 37 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3b730a5d81..0322646753 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1029,34 +1029,6 @@ static inline void arm_call_el_change_hook(ARMCPU *c= pu) } } =20 -/* - * Return true if this address translation regime has two ranges. - * Note that this will not return the correct answer for AArch32 - * Secure PL1&0 (i.e. mmu indexes E3, E30_0, E30_3_PAN), but it is - * never called from a context where EL3 can be AArch32. (The - * correct return value for ARMMMUIdx_E3 would be different for - * that case, so we can't just make the function return the - * correct value anyway; we would need an extra "bool e3_is_aarch32" - * argument which all the current callsites would pass as 'false'.) - */ -static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - return true; - default: - return false; - } -} - static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index d8d64a14d6..f03a2ab94c 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -15,6 +15,7 @@ FIELD(MMUIDXINFO, EL, 0, 2) FIELD(MMUIDXINFO, ELVALID, 2, 1) FIELD(MMUIDXINFO, REL, 3, 2) FIELD(MMUIDXINFO, RELVALID, 5, 1) +FIELD(MMUIDXINFO, 2RANGES, 6, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -39,4 +40,20 @@ static inline uint32_t regime_el(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, REL); } =20 +/* + * Return true if this address translation regime has two ranges. + * Note that this will not return the correct answer for AArch32 + * Secure PL1&0 (i.e. mmu indexes E3, E30_0, E30_3_PAN), but it is + * never called from a context where EL3 can be AArch32. (The + * correct return value for ARMMMUIdx_E3 would be different for + * that case, so we can't just make the function return the + * correct value anyway; we would need an extra "bool e3_is_aarch32" + * argument which all the current callsites would pass as 'false'.) + */ +static inline bool regime_has_2_ranges(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, 2RANGES); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 6dfefa56c2..f880d21606 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -9,18 +9,19 @@ =20 #define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) #define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) +#define R2 R_MMUIDXINFO_2RANGES_MASK =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* * A-profile. */ - [ARMMMUIdx_E10_0] =3D EL(0) | REL(1), - [ARMMMUIdx_E10_1] =3D EL(1) | REL(1), - [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1), + [ARMMMUIdx_E10_0] =3D EL(0) | REL(1) | R2, + [ARMMMUIdx_E10_1] =3D EL(1) | REL(1) | R2, + [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1) | R2, =20 - [ARMMMUIdx_E20_0] =3D EL(0) | REL(2), - [ARMMMUIdx_E20_2] =3D EL(2) | REL(2), - [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2), + [ARMMMUIdx_E20_0] =3D EL(0) | REL(2) | R2, + [ARMMMUIdx_E20_2] =3D EL(2) | REL(2) | R2, + [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2) | R2, =20 [ARMMMUIdx_E2] =3D EL(2) | REL(2), =20 @@ -31,9 +32,9 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { [ARMMMUIdx_Stage2_S] =3D REL(2), [ARMMMUIdx_Stage2] =3D REL(2), =20 - [ARMMMUIdx_Stage1_E0] =3D REL(1), - [ARMMMUIdx_Stage1_E1] =3D REL(1), - [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1), + [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2, + [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2, + [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2, =20 /* * M-profile. --=20 2.43.0