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Thu, 14 Aug 2025 05:59:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v3 33/85] target/arm: Convert arm_mmu_idx_to_el from switch to table Date: Thu, 14 Aug 2025 22:57:00 +1000 Message-ID: <20250814125752.164107-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814125752.164107-1-richard.henderson@linaro.org> References: <20250814125752.164107-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1755176885936124100 In an effort to keep all ARMMMUIdx data in one place, begin construction of an info table describing all of the properties of the mmu_idx. Begin with the access EL. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 +-- target/arm/mmuidx-internal.h | 29 +++++++++++++++++++++++++ target/arm/helper.c | 27 ------------------------ target/arm/mmuidx.c | 41 ++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 7 +++++- 5 files changed, 77 insertions(+), 30 deletions(-) create mode 100644 target/arm/mmuidx-internal.h create mode 100644 target/arm/mmuidx.c diff --git a/target/arm/internals.h b/target/arm/internals.h index b6499683cc..2dc82330ec 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -34,6 +34,7 @@ #include "system/memory.h" #include "syndrome.h" #include "cpu-features.h" +#include "mmuidx-internal.h" =20 /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -986,8 +987,6 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_id= x) return mmu_idx | ARM_MMU_IDX_A; } =20 -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); - /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); =20 diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h new file mode 100644 index 0000000000..29bba4ecb5 --- /dev/null +++ b/target/arm/mmuidx-internal.h @@ -0,0 +1,29 @@ +/* + * QEMU Arm software mmu index internal definitions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_ARM_MMUIDX_INTERNAL_H +#define TARGET_ARM_MMUIDX_INTERNAL_H + +#include "mmuidx.h" +#include "tcg/debug-assert.h" +#include "hw/registerfields.h" + + +FIELD(MMUIDXINFO, EL, 0, 2) +FIELD(MMUIDXINFO, ELVALID, 2, 1) + +extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; + +#define arm_mmuidx_is_valid(x) ((unsigned)(x) < ARRAY_SIZE(arm_mmuidx_tab= le)) + +/* Return the exception level associated with this mmu index. */ +static inline int arm_mmu_idx_to_el(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + tcg_debug_assert(FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, ELVALID= )); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, EL); +} + +#endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 9447d7ba59..8985ad8c8a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9895,33 +9895,6 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 -/* Return the exception level we're running at if this is our mmu_idx */ -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) -{ - if (mmu_idx & ARM_MMU_IDX_M) { - return mmu_idx & ARM_MMU_IDX_M_PRIV; - } - - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E30_0: - return 0; - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - return 1; - case ARMMMUIdx_E2: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - return 2; - case ARMMMUIdx_E3: - case ARMMMUIdx_E30_3_PAN: - return 3; - default: - g_assert_not_reached(); - } -} - #ifndef CONFIG_TCG ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c new file mode 100644 index 0000000000..309b1d68df --- /dev/null +++ b/target/arm/mmuidx.c @@ -0,0 +1,41 @@ +/* + * QEMU Arm software mmu index definitions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "mmuidx-internal.h" + + +#define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) + +const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { + /* + * A-profile. + */ + [ARMMMUIdx_E10_0] =3D EL(0), + [ARMMMUIdx_E10_1] =3D EL(1), + [ARMMMUIdx_E10_1_PAN] =3D EL(1), + + [ARMMMUIdx_E20_0] =3D EL(0), + [ARMMMUIdx_E20_2] =3D EL(2), + [ARMMMUIdx_E20_2_PAN] =3D EL(2), + + [ARMMMUIdx_E2] =3D EL(2), + + [ARMMMUIdx_E3] =3D EL(3), + [ARMMMUIdx_E30_0] =3D EL(0), + [ARMMMUIdx_E30_3_PAN] =3D EL(3), + + /* + * M-profile. + */ + [ARMMMUIdx_MUser] =3D EL(0), + [ARMMMUIdx_MPriv] =3D EL(1), + [ARMMMUIdx_MUserNegPri] =3D EL(0), + [ARMMMUIdx_MPrivNegPri] =3D EL(1), + [ARMMMUIdx_MSUser] =3D EL(0), + [ARMMMUIdx_MSPriv] =3D EL(1), + [ARMMMUIdx_MSUserNegPri] =3D EL(0), + [ARMMMUIdx_MSPrivNegPri] =3D EL(1), +}; diff --git a/target/arm/meson.build b/target/arm/meson.build index 07d9271aa4..91630a1f72 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -6,7 +6,12 @@ arm_ss.add(files( =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', - 'gdbstub64.c')) + 'gdbstub64.c' +)) + +arm_common_ss.add(files( + 'mmuidx.c', +)) =20 arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() --=20 2.43.0