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Thu, 14 Aug 2025 05:58:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v3 15/85] target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers Date: Thu, 14 Aug 2025 22:56:42 +1000 Message-ID: <20250814125752.164107-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814125752.164107-1-richard.henderson@linaro.org> References: <20250814125752.164107-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1755176881695116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 2 ++ target/arm/cpu.h | 4 +++ target/arm/cpu.c | 4 +++ target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2a4826f5c4..9efe9238c1 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -776,6 +776,8 @@ typedef enum FGTBit { DO_BIT(HFGRTR, ERRIDR_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), + DO_REV_BIT(HFGRTR, NPIRE0_EL1), + DO_REV_BIT(HFGRTR, NPIR_EL1), =20 /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ DO_BIT(HDFGRTR, DBGBCRN_EL1), diff --git a/target/arm/cpu.h b/target/arm/cpu.h index defe2852f2..fb87fcc3e6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -369,6 +369,9 @@ typedef struct CPUArchState { uint64_t tcr2_el[3]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ + uint64_t pir_el[4]; /* PIRE0_EL1, PIR_EL1, PIR_EL2, PIR_EL3 */ + uint64_t pire0_el2; + uint64_t s2pir_el2; uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register @@ -1738,6 +1741,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_ENTP2 (1ULL << 41) #define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) +#define SCR_PIEN (1ULL << 45) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f0545a276e..b472992b4a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -650,6 +650,10 @@ void arm_emulate_firmware_reset(CPUState *cpustate, in= t target_el) if (cpu_isar_feature(aa64_sctlr2, cpu)) { env->cp15.scr_el3 |=3D SCR_SCTLR2EN; } + if (cpu_isar_feature(aa64_s1pie, cpu) || + cpu_isar_feature(aa64_s2pie, cpu)) { + env->cp15.scr_el3 |=3D SCR_PIEN; + } if (cpu_isar_feature(aa64_mec, cpu)) { env->cp15.scr_el3 |=3D SCR_MECEN; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 61ba9ba5b2..6353b2dea1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -747,6 +747,10 @@ static void scr_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D SCR_SCTLR2EN; } + if (cpu_isar_feature(aa64_s1pie, cpu) || + cpu_isar_feature(aa64_s2pie, cpu)) { + valid_mask |=3D SCR_PIEN; + } if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |=3D SCR_MECEN; } @@ -4578,6 +4582,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", isar_feature_aa64_scxtnum }, =20 + { K(3, 0, 10, 2, 3), K(3, 4, 10, 2, 3), K(3, 5, 10, 2, 3), + "PIR_EL1", "PIR_EL2", "PIR_EL12", isar_feature_aa64_s1pie }, + { K(3, 0, 10, 2, 2), K(3, 4, 10, 2, 2), K(3, 5, 10, 2, 2), + "PIRE0_EL1", "PIRE0_EL2", "PIRE0_EL12", isar_feature_aa64_s1pie = }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -6242,6 +6251,60 @@ static const ARMCPRegInfo tcr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[2]) }, }; =20 +static CPAccessResult pien_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_PIEN) + && arm_current_el(env) < 3) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult pien_el1_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret =3D=3D CP_ACCESS_OK) { + ret =3D pien_access(env, ri, isread); + } + return ret; +} + +static const ARMCPRegInfo s1pie_reginfo[] =3D { + { .name =3D "PIR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, + .access =3D PL1_RW, .accessfn =3D pien_el1_access, + .fgt =3D FGT_NPIR_EL1, .nv2_redirect_offset =3D 0x2a0 | NV2_REDIR_NV= 1, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[1]) }, + { .name =3D "PIR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D pien_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[2]) }, + { .name =3D "PIR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[3]) }, + { .name =3D "PIRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 10, .crm =3D 2, + .access =3D PL1_RW, .accessfn =3D pien_el1_access, + .fgt =3D FGT_NPIRE0_EL1, .nv2_redirect_offset =3D 0x290 | NV2_REDIR_= NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[0]) }, + { .name =3D "PIRE0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D pien_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.pire0_el2) }, +}; + +static const ARMCPRegInfo s2pie_reginfo[] =3D { + { .name =3D "S2PIR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 5, .crn =3D 10, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D pien_access, + .nv2_redirect_offset =3D 0x2b0, + .fieldoffset =3D offsetof(CPUARMState, cp15.s2pir_el2) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7479,6 +7542,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, tcr2_reginfo); } =20 + if (cpu_isar_feature(aa64_s1pie, cpu)) { + define_arm_cp_regs(cpu, s1pie_reginfo); + } + if (cpu_isar_feature(aa64_s2pie, cpu)) { + define_arm_cp_regs(cpu, s2pie_reginfo); + } + if (cpu_isar_feature(aa64_mec, cpu)) { define_arm_cp_regs(cpu, mec_reginfo); if (cpu_isar_feature(aa64_mte, cpu)) { --=20 2.43.0