From nobody Sat Nov 15 08:48:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157159797742.7562319907838; Thu, 14 Aug 2025 00:39:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSW4-0006x4-IS; Thu, 14 Aug 2025 03:36:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVx-0006vE-5K for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVt-0004Tp-8V for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:44 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axx2n7kZ1oEqs_AQ--.20858S3; Thu, 14 Aug 2025 15:36:27 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S10; Thu, 14 Aug 2025 15:36:26 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 8/9] target/loongarch: Update matched ptw bit A/D with PTW supported Date: Thu, 14 Aug 2025 15:36:23 +0800 Message-Id: <20250814073624.430928-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157161087116600 Content-Type: text/plain; charset="utf-8" With hardware PTE supported, bit A will be set if there is read access or instruction fetch, and bit D will be set with write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 26 ++++++++++++++++++++ target/loongarch/cpu_helper.c | 45 +++++++++++++++++++++++++++++++---- 2 files changed, 67 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 2e63324abe..cb596dd57a 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -61,6 +61,32 @@ static inline bool pte_write(CPULoongArchState *env, uin= t64_t entry) return !!writable; } =20 +/* + * The folloing functions should be called with PTW enable checked + * With hardware PTW enabled + * Bit D will be set by hardware with write access + * Bit A will be set by hardware with read/intruction fetch access + */ +static inline uint64_t pte_mkaccess(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, V, 1); +} + +static inline uint64_t pte_mkdirty(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, D, 1); +} + +static inline bool pte_access(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, V); +} + +static inline bool pte_dirty(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, D); +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 79c994255f..7b0bac3dc9 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -111,11 +111,12 @@ TLBRet loongarch_page_table_walker(CPULoongArchState = *env, int access_type, int mmu_idx) { CPUState *cs =3D env_cpu(env); - target_ulong index, phys; + target_ulong index, phys =3D 0; uint64_t dir_base, dir_width; - uint64_t base; + uint64_t base, pte; int level; vaddr address; + TLBRet ret; =20 address =3D context->addr; if ((address >> 63) & 0x1) { @@ -145,6 +146,7 @@ TLBRet loongarch_page_table_walker(CPULoongArchState *e= nv, /* pte */ if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* Huge Page. base is pte */ + pte =3D base; base =3D FIELD_DP64(base, TLBENTRY, LEVEL, 0); base =3D FIELD_DP64(base, TLBENTRY, HUGE, 0); if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) { @@ -156,12 +158,13 @@ TLBRet loongarch_page_table_walker(CPULoongArchState = *env, context->pte_buddy[0] =3D base; context->pte_buddy[1] =3D base + BIT_ULL(dir_base); base +=3D (BIT_ULL(dir_base) & address); + index =3D 0; } else { /* Normal Page. base points to pte */ get_dir_base_width(env, &dir_base, &dir_width, 0); index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; - base =3D ldq_phys(cs->as, phys); + base =3D pte =3D ldq_phys(cs->as, phys); if (cpu_has_ptw(env)) { index &=3D 1; context->pte_buddy[index] =3D base; @@ -172,7 +175,41 @@ TLBRet loongarch_page_table_walker(CPULoongArchState *= env, =20 context->ps =3D dir_base; context->pte =3D base; - return loongarch_check_pte(env, context, access_type, mmu_idx); + ret =3D loongarch_check_pte(env, context, access_type, mmu_idx); + + /* + * Update bit A/D with hardware PTW supported + * + * Fixme: need atomic compchxg operation with pte update, other vCPUs = may + * update pte at the same time. + */ + if (ret =3D=3D TLBRET_MATCH && cpu_has_ptw(env)) { + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(base)) { + return ret; + } + + if (access_type !=3D MMU_DATA_STORE && pte_access(base)) { + return ret; + } + + base =3D pte_mkaccess(pte); + context->pte_buddy[index] =3D pte_mkaccess(context->pte_buddy[inde= x]); + if (access_type =3D=3D MMU_DATA_STORE) { + base =3D pte_mkdirty(base); + context->pte_buddy[index] =3D pte_mkdirty(context->pte_buddy[i= ndex]); + } + stq_phys(cs->as, phys, base); + + /* Bit A/D need be updated with both Even/Odd page with huge pte */ + if (FIELD_EX64(base, TLBENTRY, HUGE)) { + context->pte_buddy[1] =3D pte_mkaccess(context->pte_buddy[1]); + if (access_type =3D=3D MMU_DATA_STORE) { + context->pte_buddy[1] =3D pte_mkdirty(context->pte_buddy[1= ]); + } + } + } + + return ret; } =20 static TLBRet loongarch_map_address(CPULoongArchState *env, --=20 2.39.3