From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157088832155.79054108815274; Thu, 14 Aug 2025 00:38:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVv-0006tt-1g; Thu, 14 Aug 2025 03:36:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVp-0006rx-TI for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:37 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVk-0004Pe-9S for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:36 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxSWr4kZ1o_Ko_AQ--.20323S3; Thu, 14 Aug 2025 15:36:24 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S3; Thu, 14 Aug 2025 15:36:24 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 1/9] target/loongarch: Use auto method with PTW feature Date: Thu, 14 Aug 2025 15:36:16 +0800 Message-Id: <20250814073624.430928-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157090315116601 Content-Type: text/plain; charset="utf-8" PTW is short for page table walker, it is hardware page table walker function. With PTW supported, hardware MMU will parse page table table and update TLB entries automatically. This patch adds type OnOffAuto for PTW feature setting. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 22 ++++++++++++++++++++++ target/loongarch/cpu.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 990985708e..92292e6009 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -495,12 +495,29 @@ static void loongarch_set_lasx(Object *obj, bool valu= e, Error **errp) cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); } =20 +static bool loongarch_get_ptw(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->ptw !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_ptw(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; + + cpu->ptw =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + + val =3D cpu->env.cpucfg[2]; + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, HPTW, value); +} + static void loongarch_cpu_post_init(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); =20 cpu->lbt =3D ON_OFF_AUTO_OFF; cpu->pmu =3D ON_OFF_AUTO_OFF; + cpu->ptw =3D ON_OFF_AUTO_OFF; cpu->lsx =3D ON_OFF_AUTO_AUTO; cpu->lasx =3D ON_OFF_AUTO_AUTO; object_property_add_bool(obj, "lsx", loongarch_get_lsx, @@ -508,6 +525,11 @@ static void loongarch_cpu_post_init(Object *obj) object_property_add_bool(obj, "lasx", loongarch_get_lasx, loongarch_set_lasx); /* lbt is enabled only in kvm mode, not supported in tcg mode */ + if (tcg_enabled()) { + object_property_add_bool(obj, "ptw", loongarch_get_ptw, + loongarch_set_ptw); + } + if (kvm_enabled()) { kvm_loongarch_cpu_post_init(cpu); } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 3c5fcaa154..76e42f6d4e 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -158,6 +158,7 @@ FIELD(CPUCFG2, LBT_MIPS, 20, 1) FIELD(CPUCFG2, LBT_ALL, 18, 3) FIELD(CPUCFG2, LSPW, 21, 1) FIELD(CPUCFG2, LAM, 22, 1) +FIELD(CPUCFG2, HPTW, 24, 1) =20 /* cpucfg[3] bits */ FIELD(CPUCFG3, CCDMA, 0, 1) @@ -429,6 +430,7 @@ struct ArchCPU { uint32_t phy_id; OnOffAuto lbt; OnOffAuto pmu; + OnOffAuto ptw; OnOffAuto lsx; OnOffAuto lasx; OnOffAuto kvm_pv_ipi; --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157086735925.593832291014; Thu, 14 Aug 2025 00:38:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVv-0006tX-1i; Thu, 14 Aug 2025 03:36:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVp-0006rw-S3 for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:37 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVk-0004QZ-9B for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:36 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxC3L5kZ1o_6o_AQ--.54872S3; Thu, 14 Aug 2025 15:36:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S4; Thu, 14 Aug 2025 15:36:24 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 2/9] target/loongarch: Add CSR_PWCH write helper function Date: Thu, 14 Aug 2025 15:36:17 +0800 Message-Id: <20250814073624.430928-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157089579124100 Content-Type: text/plain; charset="utf-8" Bit HPTW_EN in register CSR_PWCH controls enabling hardware page table walker feature when PTW feature is enabled. Otherwise it is reserved bit. Here add register CSR_PWCH write helper function. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 1 + target/loongarch/tcg/csr_helper.c | 14 ++++++++++++++ target/loongarch/tcg/helper.h | 1 + .../tcg/insn_trans/trans_privileged.c.inc | 1 + 4 files changed, 17 insertions(+) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 0834e91f30..8f3108eca1 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -103,6 +103,7 @@ FIELD(CSR_PWCH, DIR3_BASE, 0, 6) FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6) FIELD(CSR_PWCH, DIR4_BASE, 12, 6) FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6) +FIELD(CSR_PWCH, HPTW_EN, 24, 1) =20 #define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */ FIELD(CSR_STLBPS, PS, 0, 5) diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 4433167332..007aedabdb 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -141,3 +141,17 @@ target_ulong helper_csrwr_pwcl(CPULoongArchState *env,= target_ulong val) env->CSR_PWCL =3D val; return old_v; } + +target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val) +{ + uint8_t has_ptw; + int64_t old_v =3D env->CSR_PWCH; + + has_ptw =3D FIELD_EX32(env->cpucfg[2], CPUCFG2, HPTW); + if (!has_ptw) { + val =3D FIELD_DP64(val, CSR_PWCH, HPTW_EN, 0); + } + + env->CSR_PWCH =3D val; + return old_v; + } diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h index 1d5cb0198c..0f62119987 100644 --- a/target/loongarch/tcg/helper.h +++ b/target/loongarch/tcg/helper.h @@ -106,6 +106,7 @@ DEF_HELPER_2(csrwr_asid, i64, env, tl) DEF_HELPER_2(csrwr_tcfg, i64, env, tl) DEF_HELPER_2(csrwr_ticlr, i64, env, tl) DEF_HELPER_2(csrwr_pwcl, i64, env, tl) +DEF_HELPER_2(csrwr_pwch, i64, env, tl) DEF_HELPER_2(iocsrrd_b, i64, env, tl) DEF_HELPER_2(iocsrrd_h, i64, env, tl) DEF_HELPER_2(iocsrrd_w, i64, env, tl) diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index ecbfe23b63..224f98c5fb 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -79,6 +79,7 @@ void loongarch_csr_translate_init(void) SET_CSR_FUNC(ASID, NULL, gen_helper_csrwr_asid); SET_CSR_FUNC(PGD, gen_helper_csrrd_pgd, NULL); SET_CSR_FUNC(PWCL, NULL, gen_helper_csrwr_pwcl); + SET_CSR_FUNC(PWCH, NULL, gen_helper_csrwr_pwch); SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL); SET_CSR_FUNC(TCFG, NULL, gen_helper_csrwr_tcfg); SET_CSR_FUNC(TVAL, gen_helper_csrrd_tval, NULL); --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157065133919.1415768038266; Thu, 14 Aug 2025 00:37:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVz-0006vh-Pn; Thu, 14 Aug 2025 03:36:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVq-0006st-AR for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVk-0004Qm-BU for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:37 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxNHD5kZ1oAqs_AQ--.54826S3; Thu, 14 Aug 2025 15:36:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S5; Thu, 14 Aug 2025 15:36:25 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 3/9] target/loongarch: Add present and write bit with pte entry Date: Thu, 14 Aug 2025 15:36:18 +0800 Message-Id: <20250814073624.430928-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157069211124100 Content-Type: text/plain; charset="utf-8" With hardware PTW feature enabled, Present) bit and Write bit is checked by hardware, rather Valid bit and Dirty bit. Bit P means that the page is valid and present, and bit W means that the page is writable. The original V bit is treated as access bit, hardware sets this bit if there is read or write access. Bit D bit is updated by hardware if there is write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 2 ++ target/loongarch/cpu-mmu.h | 31 +++++++++++++++++++++++++++++++ target/loongarch/cpu_helper.c | 4 ++-- target/loongarch/tcg/tlb_helper.c | 14 +++++++------- 4 files changed, 42 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 8f3108eca1..82b30515b6 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -68,6 +68,8 @@ FIELD(TLBENTRY, PLV, 2, 2) FIELD(TLBENTRY, MAT, 4, 2) FIELD(TLBENTRY, G, 6, 1) FIELD(TLBENTRY, HUGE, 6, 1) +FIELD(TLBENTRY, P, 7, 1) +FIELD(TLBENTRY, W, 8, 1) FIELD(TLBENTRY, HGLOBAL, 12, 1) FIELD(TLBENTRY, LEVEL, 13, 2) FIELD(TLBENTRY_32, PPN, 8, 24) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 311bf7b2d7..e4f3199f44 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -29,6 +29,37 @@ typedef struct MMUContext { int mmu_index; } MMUContext; =20 +static inline bool cpu_has_ptw(CPULoongArchState *env) +{ + return !!FIELD_EX64(env->CSR_PWCH, CSR_PWCH, HPTW_EN); +} + +static inline bool pte_present(CPULoongArchState *env, uint64_t entry) +{ + uint8_t present; + + if (cpu_has_ptw(env)) { + present =3D FIELD_EX64(entry, TLBENTRY, P); + } else { + present =3D FIELD_EX64(entry, TLBENTRY, V); + } + + return !!present; +} + +static inline bool pte_write(CPULoongArchState *env, uint64_t entry) +{ + uint8_t writable; + + if (cpu_has_ptw(env)) { + writable =3D FIELD_EX64(entry, TLBENTRY, W); + } else { + writable =3D FIELD_EX64(entry, TLBENTRY, D); + } + + return !!writable; +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 6572d0a7cc..2e07049425 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -53,8 +53,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUCon= text *context, =20 tlb_entry =3D context->pte; tlb_ps =3D context->ps; - tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); - tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_v =3D pte_present(env, tlb_entry); + tlb_d =3D pte_write(env, tlb_entry); tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); if (is_la64(env)) { tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 7a4de7e566..10c01ead3f 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -119,11 +119,9 @@ static void raise_mmu_exception(CPULoongArchState *env= , vaddr address, static void invalidate_tlb_entry(CPULoongArchState *env, int index) { target_ulong addr, mask, pagesize; - uint8_t tlb_ps; + uint8_t tlb_ps, tlb_v; LoongArchTLB *tlb =3D &env->tlb[index]; int mmu_idx; - uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); - uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); uint8_t tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); =20 @@ -137,7 +135,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; addr =3D sextract64(addr, 0, TARGET_VIRT_ADDR_SPACE_BITS); =20 - if (tlb_v0) { + tlb_v =3D pte_present(env, tlb->tlb_entry0); + if (tlb_v) { mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry0, TLBENTRY, PLV)); /* Even page is accessed in kernel mode */ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW0) { @@ -147,7 +146,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) mmu_idx, TARGET_LONG_BITS); } =20 - if (tlb_v1) { + tlb_v =3D pte_present(env, tlb->tlb_entry1); + if (tlb_v) { mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry1, TLBENTRY, PLV)); /* Odd page is accessed in kernel mode */ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW1) { @@ -362,8 +362,8 @@ void helper_tlbwr(CPULoongArchState *env) /* Check whether ASID/VPPN is the same */ if (old->tlb_misc =3D=3D new.tlb_misc) { /* Check whether pte is the same or invalid */ - tlb_v0 =3D FIELD_EX64(old->tlb_entry0, TLBENTRY, V); - tlb_v1 =3D FIELD_EX64(old->tlb_entry1, TLBENTRY, V); + tlb_v0 =3D pte_present(env, old->tlb_entry0); + tlb_v1 =3D pte_present(env, old->tlb_entry1); if ((!tlb_v0 || new.tlb_entry0 =3D=3D old->tlb_entry0) && (!tlb_v1 || new.tlb_entry1 =3D=3D old->tlb_entry1)) { skip_inv =3D true; --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175515714200285.40109704930967; Thu, 14 Aug 2025 00:39:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSW2-0006we-Bq; Thu, 14 Aug 2025 03:36:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVt-0006uG-Fs for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:42 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVm-0004RE-B1 for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:39 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxaeH5kZ1oBas_AQ--.12282S3; Thu, 14 Aug 2025 15:36:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S6; Thu, 14 Aug 2025 15:36:25 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 4/9] target/loongarch: Add function sptw_prepare_tlb before adding tlb entry Date: Thu, 14 Aug 2025 15:36:19 +0800 Message-Id: <20250814073624.430928-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157143059116600 Content-Type: text/plain; charset="utf-8" With software page table walker, tlb entry comes from CSR registers. however with hardware page table walker, tlb entry comes from page table entry information directly, TLB CSR registers are not necessary. Here add function sptw_prepare_context(), get tlb entry information from TLB CSR registers. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 1 + target/loongarch/tcg/tlb_helper.c | 37 ++++++++++++++++++++----------- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index e4f3199f44..c3e869234a 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -27,6 +27,7 @@ typedef struct MMUContext { int prot; int tlb_index; int mmu_index; + uint64_t pte_buddy[2]; } MMUContext; =20 static inline bool cpu_has_ptw(CPULoongArchState *env) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 10c01ead3f..fa216b92fd 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -174,42 +174,53 @@ static void invalidate_tlb(CPULoongArchState *env, in= t index) tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0); } =20 -static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +/* Prepare tlb entry information in software PTW mode */ +static void sptw_prepare_context(CPULoongArchState *env, MMUContext *conte= xt) { - uint64_t lo0, lo1, csr_vppn; - uint16_t csr_asid; - uint8_t csr_ps; + uint64_t csr_vppn; =20 if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - csr_ps =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + context->ps =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); if (is_la64(env)) { csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN= ); } else { csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN= ); } - lo0 =3D env->CSR_TLBRELO0; - lo1 =3D env->CSR_TLBRELO1; + context->pte_buddy[0] =3D env->CSR_TLBRELO0; + context->pte_buddy[1] =3D env->CSR_TLBRELO1; } else { - csr_ps =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + context->ps =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); if (is_la64(env)) { csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN); } else { csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN); } - lo0 =3D env->CSR_TLBELO0; - lo1 =3D env->CSR_TLBELO1; + context->pte_buddy[0] =3D env->CSR_TLBELO0; + context->pte_buddy[1] =3D env->CSR_TLBELO1; } =20 + context->addr =3D csr_vppn << R_TLB_MISC_VPPN_SHIFT; +} + +static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +{ + uint64_t csr_vppn; + uint16_t csr_asid; + MMUContext context; + + sptw_prepare_context(env, &context); + csr_vppn =3D context.addr >> R_TLB_MISC_VPPN_SHIFT; + /* Store page size in field PS */ tlb->tlb_misc =3D 0; - tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); + tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, context.ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid); =20 - tlb->tlb_entry0 =3D lo0; - tlb->tlb_entry1 =3D lo1; + tlb->tlb_entry0 =3D context.pte_buddy[0]; + tlb->tlb_entry1 =3D context.pte_buddy[1]; } =20 /* Return an random value between low and high */ --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157064076103.49965003627426; Thu, 14 Aug 2025 00:37:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSW0-0006w7-OA; Thu, 14 Aug 2025 03:36:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVq-0006sr-92 for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVm-0004RH-B9 for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:37 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxQK_6kZ1oCKs_AQ--.20598S3; Thu, 14 Aug 2025 15:36:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S7; Thu, 14 Aug 2025 15:36:25 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 5/9] target/loongarch: Add common function get_tlb_random_index() Date: Thu, 14 Aug 2025 15:36:20 +0800 Message-Id: <20250814073624.430928-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157067779124100 Content-Type: text/plain; charset="utf-8" With software PTW system, tlb index is calculated randomly when new TLB entry is added. For hardware PTW, it is the same logic to add new TLB entry. Here common function get_tlb_random_index() is added to get random tlb index when adding new TLB entry. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 39 +++++++++++++++++++------------ 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index fa216b92fd..67b8f95849 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -390,31 +390,21 @@ void helper_tlbwr(CPULoongArchState *env) old->tlb_entry1 =3D new.tlb_entry1; } =20 -void helper_tlbfill(CPULoongArchState *env) +static int get_tlb_random_index(CPULoongArchState *env, vaddr addr, int ps) { - uint64_t address, entryhi; + vaddr address; int index, set, i, stlb_idx; - uint16_t pagesize, stlb_ps; + uint16_t stlb_ps; uint16_t asid, tlb_asid; LoongArchTLB *tlb; uint8_t tlb_e; =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - entryhi =3D env->CSR_TLBREHI; - /* Validity of pagesize is checked in helper_ldpte() */ - pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); - } else { - entryhi =3D env->CSR_TLBEHI; - /* Validity of pagesize is checked in helper_tlbrd() */ - pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); - } - /* Validity of stlb_ps is checked in helper_csrwr_stlbps() */ stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); - if (pagesize =3D=3D stlb_ps) { + if (ps =3D=3D stlb_ps) { /* Only write into STLB bits [47:13] */ - address =3D entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHI= FT); + address =3D addr & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT); set =3D -1; stlb_idx =3D (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */ for (i =3D 0; i < 8; ++i) { @@ -459,6 +449,25 @@ void helper_tlbfill(CPULoongArchState *env) } } =20 + return index; +} + +void helper_tlbfill(CPULoongArchState *env) +{ + uint64_t entryhi; + int index, pagesize; + + if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + entryhi =3D env->CSR_TLBREHI; + /* Validity of pagesize is checked in helper_ldpte() */ + pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + } else { + entryhi =3D env->CSR_TLBEHI; + /* Validity of pagesize is checked in helper_tlbrd() */ + pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + } + + index =3D get_tlb_random_index(env, entryhi, pagesize); invalidate_tlb(env, index); fill_tlb_entry(env, env->tlb + index); } --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157088676700.6788739008202; Thu, 14 Aug 2025 00:38:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSW2-0006wd-9o; Thu, 14 Aug 2025 03:36:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVt-0006uH-Fg for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:42 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVm-0004RL-OV for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:39 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxIK_6kZ1oC6s_AQ--.52613S3; Thu, 14 Aug 2025 15:36:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S8; Thu, 14 Aug 2025 15:36:26 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 6/9] target/loongarch: Add MMUContext parameter in fill_tlb_entry() Date: Thu, 14 Aug 2025 15:36:21 +0800 Message-Id: <20250814073624.430928-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157090330116600 Content-Type: text/plain; charset="utf-8" Function fill_tlb_entry() can be used with hardware PTW in future, here add input parameter MMUContext in fill_tlb_entry(). Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 67b8f95849..50c7583c6c 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -202,25 +202,24 @@ static void sptw_prepare_context(CPULoongArchState *e= nv, MMUContext *context) context->addr =3D csr_vppn << R_TLB_MISC_VPPN_SHIFT; } =20 -static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb, + MMUContext *context) { uint64_t csr_vppn; uint16_t csr_asid; - MMUContext context; =20 - sptw_prepare_context(env, &context); - csr_vppn =3D context.addr >> R_TLB_MISC_VPPN_SHIFT; + csr_vppn =3D context->addr >> R_TLB_MISC_VPPN_SHIFT; =20 /* Store page size in field PS */ tlb->tlb_misc =3D 0; - tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, context.ps); + tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, context->ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid); =20 - tlb->tlb_entry0 =3D context.pte_buddy[0]; - tlb->tlb_entry1 =3D context.pte_buddy[1]; + tlb->tlb_entry0 =3D context->pte_buddy[0]; + tlb->tlb_entry1 =3D context->pte_buddy[1]; } =20 /* Return an random value between low and high */ @@ -359,6 +358,7 @@ void helper_tlbwr(CPULoongArchState *env) LoongArchTLB *old, new; bool skip_inv =3D false; uint8_t tlb_v0, tlb_v1; + MMUContext context; =20 old =3D env->tlb + index; if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) { @@ -366,10 +366,11 @@ void helper_tlbwr(CPULoongArchState *env) return; } =20 + sptw_prepare_context(env, &context); new.tlb_misc =3D 0; new.tlb_entry0 =3D 0; new.tlb_entry1 =3D 0; - fill_tlb_entry(env, &new); + fill_tlb_entry(env, &new, &context); /* Check whether ASID/VPPN is the same */ if (old->tlb_misc =3D=3D new.tlb_misc) { /* Check whether pte is the same or invalid */ @@ -456,6 +457,7 @@ void helper_tlbfill(CPULoongArchState *env) { uint64_t entryhi; int index, pagesize; + MMUContext context; =20 if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { entryhi =3D env->CSR_TLBREHI; @@ -467,9 +469,10 @@ void helper_tlbfill(CPULoongArchState *env) pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); } =20 + sptw_prepare_context(env, &context); index =3D get_tlb_random_index(env, entryhi, pagesize); invalidate_tlb(env, index); - fill_tlb_entry(env, env->tlb + index); + fill_tlb_entry(env, env->tlb + index, &context); } =20 void helper_tlbclr(CPULoongArchState *env) --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157143566862.0652838126347; Thu, 14 Aug 2025 00:39:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSW2-0006wi-VH; Thu, 14 Aug 2025 03:36:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVt-0006uF-Fi for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:42 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVq-0004S1-0c for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:40 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxTOL6kZ1oDqs_AQ--.14533S3; Thu, 14 Aug 2025 15:36:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S9; Thu, 14 Aug 2025 15:36:26 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 7/9] target/loongarch: Add basic hardware PTW support Date: Thu, 14 Aug 2025 15:36:22 +0800 Message-Id: <20250814073624.430928-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157144953116600 Content-Type: text/plain; charset="utf-8" With software PTW, there is TLB refill exception if there is TLB miss. However with hardware PTW supported, hardware will search page table with TLB miss. Also if Present bit is not set, hardware PTW will take, it is used in odd/even TLB entry. For example in the first time odd TLB entry is valid and even TLB entry is 0. When software accesses with address from even page, there is no TLB miss only that TLB entry is 0. In this condition, hardwre PTW will take also. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 3 +++ target/loongarch/cpu_helper.c | 17 ++++++++++++++--- target/loongarch/tcg/tlb_helper.c | 26 ++++++++++++++++++++++++++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index c3e869234a..2e63324abe 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -67,6 +67,9 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUCon= text *context, TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx, int is_debug); +TLBRet loongarch_page_table_walker(CPULoongArchState *env, + MMUContext *context, + int access_type, int mmu_idx); void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, target_ulong level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 2e07049425..79c994255f 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -106,9 +106,9 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUC= ontext *context, return TLBRET_MATCH; } =20 -static TLBRet loongarch_page_table_walker(CPULoongArchState *env, - MMUContext *context, - int access_type, int mmu_idx) +TLBRet loongarch_page_table_walker(CPULoongArchState *env, + MMUContext *context, + int access_type, int mmu_idx) { CPUState *cs =3D env_cpu(env); target_ulong index, phys; @@ -151,12 +151,23 @@ static TLBRet loongarch_page_table_walker(CPULoongArc= hState *env, base =3D FIELD_DP64(base, TLBENTRY, HGLOBAL, 0); base =3D FIELD_DP64(base, TLBENTRY, G, 1); } + + dir_base -=3D 1; + context->pte_buddy[0] =3D base; + context->pte_buddy[1] =3D base + BIT_ULL(dir_base); + base +=3D (BIT_ULL(dir_base) & address); } else { /* Normal Page. base points to pte */ get_dir_base_width(env, &dir_base, &dir_width, 0); index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; base =3D ldq_phys(cs->as, phys); + if (cpu_has_ptw(env)) { + index &=3D 1; + context->pte_buddy[index] =3D base; + context->pte_buddy[1 - index] =3D ldq_phys(cs->as, + phys + 8 * (1 - 2 * index)); + } } =20 context->ps =3D dir_base; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 50c7583c6c..7fdac475b3 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -621,6 +621,20 @@ static inline void tlb_set_accessed(CPULoongArchState = *env, vaddr address, tlb->tlb_misc |=3D TLB_MISC_KM_PTE(n); } =20 +static void ptw_update_tlb(CPULoongArchState *env, MMUContext *context) +{ + int index; + bool match; + + match =3D loongarch_tlb_search(env, context->addr, &index); + if (!match) { + index =3D get_tlb_random_index(env, context->addr, context->ps); + } + + invalidate_tlb(env, index); + fill_tlb_entry(env, env->tlb + index, context); +} + bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -634,6 +648,18 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, /* Data access */ context.addr =3D address; ret =3D get_physical_address(env, &context, access_type, mmu_idx, 0); + if (ret !=3D TLBRET_MATCH && cpu_has_ptw(env)) { + /* Take HW PTW if TLB missed or bit P is zero */ + if (ret =3D=3D TLBRET_NOMATCH || ret =3D=3D TLBRET_INVALID) { + ret =3D loongarch_page_table_walker(env, &context, access_type= , mmu_idx); + if (ret =3D=3D TLBRET_MATCH) { + ptw_update_tlb(env, &context); + } + } else { + invalidate_tlb(env, context.tlb_index); + } + } + if (ret =3D=3D TLBRET_MATCH) { physical =3D context.physical; prot =3D context.prot; --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157159797742.7562319907838; Thu, 14 Aug 2025 00:39:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSW4-0006x4-IS; Thu, 14 Aug 2025 03:36:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVx-0006vE-5K for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVt-0004Tp-8V for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:44 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axx2n7kZ1oEqs_AQ--.20858S3; Thu, 14 Aug 2025 15:36:27 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S10; Thu, 14 Aug 2025 15:36:26 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 8/9] target/loongarch: Update matched ptw bit A/D with PTW supported Date: Thu, 14 Aug 2025 15:36:23 +0800 Message-Id: <20250814073624.430928-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157161087116600 Content-Type: text/plain; charset="utf-8" With hardware PTE supported, bit A will be set if there is read access or instruction fetch, and bit D will be set with write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 26 ++++++++++++++++++++ target/loongarch/cpu_helper.c | 45 +++++++++++++++++++++++++++++++---- 2 files changed, 67 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 2e63324abe..cb596dd57a 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -61,6 +61,32 @@ static inline bool pte_write(CPULoongArchState *env, uin= t64_t entry) return !!writable; } =20 +/* + * The folloing functions should be called with PTW enable checked + * With hardware PTW enabled + * Bit D will be set by hardware with write access + * Bit A will be set by hardware with read/intruction fetch access + */ +static inline uint64_t pte_mkaccess(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, V, 1); +} + +static inline uint64_t pte_mkdirty(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, D, 1); +} + +static inline bool pte_access(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, V); +} + +static inline bool pte_dirty(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, D); +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 79c994255f..7b0bac3dc9 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -111,11 +111,12 @@ TLBRet loongarch_page_table_walker(CPULoongArchState = *env, int access_type, int mmu_idx) { CPUState *cs =3D env_cpu(env); - target_ulong index, phys; + target_ulong index, phys =3D 0; uint64_t dir_base, dir_width; - uint64_t base; + uint64_t base, pte; int level; vaddr address; + TLBRet ret; =20 address =3D context->addr; if ((address >> 63) & 0x1) { @@ -145,6 +146,7 @@ TLBRet loongarch_page_table_walker(CPULoongArchState *e= nv, /* pte */ if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* Huge Page. base is pte */ + pte =3D base; base =3D FIELD_DP64(base, TLBENTRY, LEVEL, 0); base =3D FIELD_DP64(base, TLBENTRY, HUGE, 0); if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) { @@ -156,12 +158,13 @@ TLBRet loongarch_page_table_walker(CPULoongArchState = *env, context->pte_buddy[0] =3D base; context->pte_buddy[1] =3D base + BIT_ULL(dir_base); base +=3D (BIT_ULL(dir_base) & address); + index =3D 0; } else { /* Normal Page. base points to pte */ get_dir_base_width(env, &dir_base, &dir_width, 0); index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; - base =3D ldq_phys(cs->as, phys); + base =3D pte =3D ldq_phys(cs->as, phys); if (cpu_has_ptw(env)) { index &=3D 1; context->pte_buddy[index] =3D base; @@ -172,7 +175,41 @@ TLBRet loongarch_page_table_walker(CPULoongArchState *= env, =20 context->ps =3D dir_base; context->pte =3D base; - return loongarch_check_pte(env, context, access_type, mmu_idx); + ret =3D loongarch_check_pte(env, context, access_type, mmu_idx); + + /* + * Update bit A/D with hardware PTW supported + * + * Fixme: need atomic compchxg operation with pte update, other vCPUs = may + * update pte at the same time. + */ + if (ret =3D=3D TLBRET_MATCH && cpu_has_ptw(env)) { + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(base)) { + return ret; + } + + if (access_type !=3D MMU_DATA_STORE && pte_access(base)) { + return ret; + } + + base =3D pte_mkaccess(pte); + context->pte_buddy[index] =3D pte_mkaccess(context->pte_buddy[inde= x]); + if (access_type =3D=3D MMU_DATA_STORE) { + base =3D pte_mkdirty(base); + context->pte_buddy[index] =3D pte_mkdirty(context->pte_buddy[i= ndex]); + } + stq_phys(cs->as, phys, base); + + /* Bit A/D need be updated with both Even/Odd page with huge pte */ + if (FIELD_EX64(base, TLBENTRY, HUGE)) { + context->pte_buddy[1] =3D pte_mkaccess(context->pte_buddy[1]); + if (access_type =3D=3D MMU_DATA_STORE) { + context->pte_buddy[1] =3D pte_mkdirty(context->pte_buddy[1= ]); + } + } + } + + return ret; } =20 static TLBRet loongarch_map_address(CPULoongArchState *env, --=20 2.39.3 From nobody Sat Nov 15 05:35:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755157066931702.8747699679949; Thu, 14 Aug 2025 00:37:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSW5-0006xJ-3j; Thu, 14 Aug 2025 03:36:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1umSVy-0006vV-Cr for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:46 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1umSVv-0004UG-8j for qemu-devel@nongnu.org; Thu, 14 Aug 2025 03:36:46 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxfeH7kZ1oFas_AQ--.15276S3; Thu, 14 Aug 2025 15:36:27 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+T4kZ1oM9xKAA--.22944S11; Thu, 14 Aug 2025 15:36:27 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 9/9] target/loongarch: Add bit A/D checking in TLB entry with PTW supported Date: Thu, 14 Aug 2025 15:36:24 +0800 Message-Id: <20250814073624.430928-10-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250814073624.430928-1-maobibo@loongson.cn> References: <20250814073624.430928-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+T4kZ1oM9xKAA--.22944S11 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755157068225116600 Content-Type: text/plain; charset="utf-8" With read/write access, add bit A/D checking if hardware PTW is supported. If no matched, hardware page table walk is called. And then bit A/D is updated in PTE entry and TLB entry is updated also. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 7fdac475b3..8edd481a53 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -648,6 +648,21 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, /* Data access */ context.addr =3D address; ret =3D get_physical_address(env, &context, access_type, mmu_idx, 0); + if (ret =3D=3D TLBRET_MATCH && context.mmu_index !=3D MMU_DA_IDX + && cpu_has_ptw(env)) { + bool need_mark =3D true; + + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(context.pte)) { + need_mark =3D false; + } else if (access_type !=3D MMU_DATA_STORE && pte_access(context.p= te)) { + need_mark =3D false; + } + + if (need_mark) { + ret =3D TLBRET_NOMATCH; + } + } + if (ret !=3D TLBRET_MATCH && cpu_has_ptw(env)) { /* Take HW PTW if TLB missed or bit P is zero */ if (ret =3D=3D TLBRET_NOMATCH || ret =3D=3D TLBRET_INVALID) { --=20 2.39.3