From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1754991845; cv=none; d=zohomail.com; s=zohoarc; b=hM0v1YNBzZfSg4eYjeQlpOgpFaHcOb7vUxRcpIjjrRiEZaRuff7DIvcE8mUaF88iuSUg0xWR7ZChDNVZRJtsz5plAlzLxXTN1OGNZlqNmvtV8vjJlOvhHBsaX8MNaoHgtPgG4q7xfmeiPupqKdKHWhs6OmWkZvRhPFfAezcIneY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754991845; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=nxZvoyCGzGRwOfaCEKEC6Rtd40CTVoFOJ7SjUsHskXU=; b=Adhhm8w1m5LYhVRsa+KuALSxJ3gmsAygFC1A11Jhn5SjGtHDRMWimDbgvhnXX9UdVWu4HuAQxTTSNIvTYRt+0MlKB6ksiDyK25RaS0zg4ylSj59Bvosn8C70RjuRZCpsRz31vV/5B/1lMagRAeIVigG+ne9c2Qx1UjpsfMdcQLs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175499184561945.426007166117074; Tue, 12 Aug 2025 02:44:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ullUj-0007Pz-Ut; Tue, 12 Aug 2025 05:40:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullUf-0007On-JY; Tue, 12 Aug 2025 05:40:33 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullUc-0000Yh-Su; Tue, 12 Aug 2025 05:40:33 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 17:40:12 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:12 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 01/10] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model Date: Tue, 12 Aug 2025 17:39:58 +0800 Message-ID: <20250812094011.2617526-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991847203124100 From: Kane-Chen-AS Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage. The OTP memory can operate with an internal memory buffer. The OTP model provides a memory-like interface through a dedicated AddressSpace, allowing other device models (e.g., SBC) to issue transactions as if accessing a memory-mapped region. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- include/hw/nvram/aspeed_otp.h | 33 ++++++++++++ hw/nvram/aspeed_otp.c | 99 +++++++++++++++++++++++++++++++++++ hw/nvram/meson.build | 4 ++ 3 files changed, 136 insertions(+) create mode 100644 include/hw/nvram/aspeed_otp.h create mode 100644 hw/nvram/aspeed_otp.c diff --git a/include/hw/nvram/aspeed_otp.h b/include/hw/nvram/aspeed_otp.h new file mode 100644 index 0000000000..3752353860 --- /dev/null +++ b/include/hw/nvram/aspeed_otp.h @@ -0,0 +1,33 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_OTP_H +#define ASPEED_OTP_H + +#include "system/memory.h" +#include "hw/block/block.h" +#include "system/address-spaces.h" + +#define TYPE_ASPEED_OTP "aspeed-otp" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP) + +typedef struct AspeedOTPState { + DeviceState parent_obj; + + BlockBackend *blk; + + uint64_t size; + + AddressSpace as; + + MemoryRegion mmio; + + uint8_t *storage; +} AspeedOTPState; + +#endif /* ASPEED_OTP_H */ diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c new file mode 100644 index 0000000000..e5b7ca9676 --- /dev/null +++ b/hw/nvram/aspeed_otp.c @@ -0,0 +1,99 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "system/block-backend.h" +#include "hw/qdev-properties.h" +#include "hw/nvram/aspeed_otp.h" + +static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size) +{ + AspeedOTPState *s =3D opaque; + uint64_t val =3D 0; + + memcpy(&val, s->storage + offset, size); + + return val; +} + +static void aspeed_otp_write(void *opaque, hwaddr otp_addr, + uint64_t val, unsigned size) +{ + AspeedOTPState *s =3D opaque; + + memcpy(s->storage + otp_addr, &val, size); +} + +static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp) +{ + uint32_t *p; + int i, num; + + num =3D s->size / sizeof(uint32_t); + p =3D (uint32_t *)s->storage; + for (i =3D 0; i < num; i++) { + p[i] =3D (i % 2 =3D=3D 0) ? 0x00000000 : 0xFFFFFFFF; + } + + return true; +} + +static const MemoryRegionOps aspeed_otp_ops =3D { + .read =3D aspeed_otp_read, + .write =3D aspeed_otp_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static void aspeed_otp_realize(DeviceState *dev, Error **errp) +{ + AspeedOTPState *s =3D ASPEED_OTP(dev); + + if (s->size =3D=3D 0) { + error_setg(errp, "aspeed.otp: 'size' property must be set"); + return; + } + + s->storage =3D blk_blockalign(s->blk, s->size); + + if (!aspeed_otp_init_storage(s, errp)) { + return; + } + + memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops, + s, "aspeed.otp", s->size); + address_space_init(&s->as, &s->mmio, NULL); +} + +static const Property aspeed_otp_properties[] =3D { + DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0), +}; + +static void aspeed_otp_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D aspeed_otp_realize; + device_class_set_props(dc, aspeed_otp_properties); +} + +static const TypeInfo aspeed_otp_info =3D { + .name =3D TYPE_ASPEED_OTP, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(AspeedOTPState), + .class_init =3D aspeed_otp_class_init, +}; + +static void aspeed_otp_register_types(void) +{ + type_register_static(&aspeed_otp_info); +} + +type_init(aspeed_otp_register_types) diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index 10f3639db6..b66f23605b 100644 --- a/hw/nvram/meson.build +++ b/hw/nvram/meson.build @@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('= xlnx-bbram.c')) =20 specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c')) + +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( + 'aspeed_otp.c', + )) \ No newline at end of file --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1754991746; cv=none; d=zohomail.com; s=zohoarc; b=OYsDveGiBElrQtjg2YBwSqzNSH4cSFTIJjv1PLrpVnvxcZIVORmaJfiXQi/6sFkT8zjnC+Cytw5W7RgfdRHENPGxK4q3whgdt1+8cHZG5AHAPAZqqYfsnkZjLwPjhYFxbN6ZR5K7ShzTeTLbG9wYhgkpWkpOqjwBZMgFYQn84Ds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754991746; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=VHhK0WUKCxd5Nf2ABJrph+tnha3juZlZBMKD8cPQvP4=; b=CZNYyprLeOwKrioWUrpfaRkoy8Ku/tpiCJidAK8lSKooSPQDNmBhpzW8DKbi/izf4Lpis5lBB628uzClwhiuJZ8cfffKurmnuOOeq6Buww+c7dTI4/r3PzgY1QRlutoagu7fLDLee6yPti5k9Bjc8vGDpn7lpI1bt2OxHu/xprc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1754991746195382.9814545868626; Tue, 12 Aug 2025 02:42:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ullV3-0007T0-WB; Tue, 12 Aug 2025 05:40:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullUl-0007QW-M5; Tue, 12 Aug 2025 05:40:40 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullUh-0000Yh-Aa; Tue, 12 Aug 2025 05:40:39 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 17:40:13 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:13 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 02/10] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Date: Tue, 12 Aug 2025 17:39:59 +0800 Message-ID: <20250812094011.2617526-3-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991748744116600 From: Kane-Chen-AS This patch connects the aspeed.otp device to the ASPEED Secure Boot Controller (SBC) model. It implements OTP memory access via the SBC's command interface and enables emulation of secure fuse programming flows. The following OTP commands are supported: - READ: reads a 32-bit word from OTP memory into internal registers - PROG: programs a 32-bit word value to the specified OTP address Trace events are added to observe read/program operations and command handling flow. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_sbc.h | 5 ++ hw/misc/aspeed_sbc.c | 111 +++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 5 ++ 3 files changed, 121 insertions(+) diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h index 405e6782b9..0c2746d392 100644 --- a/include/hw/misc/aspeed_sbc.h +++ b/include/hw/misc/aspeed_sbc.h @@ -10,6 +10,7 @@ #define ASPEED_SBC_H =20 #include "hw/sysbus.h" +#include "hw/nvram/aspeed_otp.h" =20 #define TYPE_ASPEED_SBC "aspeed.sbc" #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600" @@ -36,10 +37,14 @@ struct AspeedSBCState { MemoryRegion iomem; =20 uint32_t regs[ASPEED_SBC_NR_REGS]; + + AspeedOTPState otp; }; =20 struct AspeedSBCClass { SysBusDeviceClass parent_class; + + bool has_otp; }; =20 #endif /* ASPEED_SBC_H */ diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index a7d101ba71..46a038337c 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -15,9 +15,13 @@ #include "hw/misc/aspeed_sbc.h" #include "qapi/error.h" #include "migration/vmstate.h" +#include "trace.h" =20 #define R_PROT (0x000 / 4) +#define R_CMD (0x004 / 4) +#define R_ADDR (0x010 / 4) #define R_STATUS (0x014 / 4) +#define R_CAMP1 (0x020 / 4) #define R_QSR (0x040 / 4) =20 /* R_STATUS */ @@ -41,6 +45,11 @@ #define QSR_RSA_MASK (0x3 << 12) #define QSR_HASH_MASK (0x3 << 10) =20 +#define OTP_MEMORY_SIZE 0x4000 +/* OTP command */ +#define SBC_OTP_CMD_READ 0x23b1e361 +#define SBC_OTP_CMD_PROG 0x23b1e364 + static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int si= ze) { AspeedSBCState *s =3D ASPEED_SBC(opaque); @@ -57,6 +66,84 @@ static uint64_t aspeed_sbc_read(void *opaque, hwaddr add= r, unsigned int size) return s->regs[addr]; } =20 +static bool aspeed_sbc_otp_read(AspeedSBCState *s, + uint32_t otp_addr) +{ + MemTxResult ret; + AspeedOTPState *otp =3D &s->otp; + uint32_t value, otp_offset; + + otp_offset =3D otp_addr << 2; + ret =3D address_space_read(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIE= D, + &value, sizeof(value)); + if (ret !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "Failed to read OTP memory, addr =3D %x\n", + otp_addr); + return false; + } + s->regs[R_CAMP1] =3D value; + trace_aspeed_sbc_otp_read(otp_addr, value); + + return true; +} + +static bool aspeed_sbc_otp_prog(AspeedSBCState *s, + uint32_t otp_addr) +{ + MemTxResult ret; + AspeedOTPState *otp =3D &s->otp; + uint32_t value =3D s->regs[R_CAMP1]; + + ret =3D address_space_write(&otp->as, otp_addr, MEMTXATTRS_UNSPECIFIED, + &value, sizeof(value)); + if (ret !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "Failed to write OTP memory, addr =3D %x\n", + otp_addr); + return false; + } + + trace_aspeed_sbc_otp_prog(otp_addr, value); + + return true; +} + +static void aspeed_sbc_handle_command(void *opaque, uint32_t cmd) +{ + AspeedSBCState *s =3D ASPEED_SBC(opaque); + AspeedSBCClass *sc =3D ASPEED_SBC_GET_CLASS(opaque); + bool ret =3D false; + uint32_t otp_addr; + + if (!sc->has_otp) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: OTP memory is not supported\n", + __func__); + return; + } + + s->regs[R_STATUS] &=3D ~(OTP_MEM_IDLE | OTP_IDLE); + otp_addr =3D s->regs[R_ADDR]; + + switch (cmd) { + case SBC_OTP_CMD_READ: + ret =3D aspeed_sbc_otp_read(s, otp_addr); + break; + case SBC_OTP_CMD_PROG: + ret =3D aspeed_sbc_otp_prog(s, otp_addr); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unknown command 0x%x\n", + __func__, cmd); + break; + } + + trace_aspeed_sbc_handle_cmd(cmd, otp_addr, ret); + s->regs[R_STATUS] |=3D (OTP_MEM_IDLE | OTP_IDLE); +} + static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -78,6 +165,9 @@ static void aspeed_sbc_write(void *opaque, hwaddr addr, = uint64_t data, "%s: write to read only register 0x%" HWADDR_PRIx "\= n", __func__, addr << 2); return; + case R_CMD: + aspeed_sbc_handle_command(opaque, data); + return; default: break; } @@ -115,10 +205,30 @@ static void aspeed_sbc_reset(DeviceState *dev) s->regs[R_QSR] =3D s->signing_settings; } =20 +static void aspeed_sbc_instance_init(Object *obj) +{ + AspeedSBCClass *sc =3D ASPEED_SBC_GET_CLASS(obj); + AspeedSBCState *s =3D ASPEED_SBC(obj); + + if (sc->has_otp) { + object_initialize_child(OBJECT(s), "otp", &s->otp, + TYPE_ASPEED_OTP); + } +} + static void aspeed_sbc_realize(DeviceState *dev, Error **errp) { AspeedSBCState *s =3D ASPEED_SBC(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedSBCClass *sc =3D ASPEED_SBC_GET_CLASS(dev); + + if (sc->has_otp) { + object_property_set_int(OBJECT(&s->otp), "size", + OTP_MEMORY_SIZE, &error_abort); + if (!qdev_realize(DEVICE(&s->otp), NULL, errp)) { + return; + } + } =20 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s, TYPE_ASPEED_SBC, 0x1000); @@ -155,6 +265,7 @@ static const TypeInfo aspeed_sbc_info =3D { .name =3D TYPE_ASPEED_SBC, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(AspeedSBCState), + .instance_init =3D aspeed_sbc_instance_init, .class_init =3D aspeed_sbc_class_init, .class_size =3D sizeof(AspeedSBCClass) }; diff --git a/hw/misc/trace-events b/hw/misc/trace-events index e3f64c0ff6..9e05b82f37 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -90,6 +90,11 @@ slavio_sysctrl_mem_readl(uint32_t ret) "Read system cont= rol 0x%08x" slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x" slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" =20 +# aspeed_sbc.c +aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling com= mand 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d" +aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr = 0x%" PRIx32 " value 0x%" PRIx32 +aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr= 0x%" PRIx32 " value 0x%" PRIx32 + # aspeed_scu.c aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" P= RIx64 " of size %u: 0x%" PRIx32 aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PR= Ix64 " of size %u: 0x%" PRIx32 --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1754991746; cv=none; d=zohomail.com; s=zohoarc; b=lhgz6muKHFIlrfhMCHegiLWYxq/vBhpjglOWTESdYPZnbpscs1+8g3w+UgeHwi03CbGYSAP/EnVwgDccI9t2EiBbqqLwjAqrJjYq0O7mx1YjAR5lmIXIWFz/souw5CsOpeW6y0EtdaxXDAAIq/sDutBExXLo50du9LP6AJeIhrQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754991746; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=F5NCIFqMQ2gso3EhrvSHOvRvWV3RU4d4q78SvSEhKt0=; b=dWFJVjvnPXUkZ26tEWc7K+mCuFUeBMlIHHJhkzCyDpXSN/UJiILV+lGBJNUum9yvOt+9ppMDoFAwrJTDqw+m7jtUAi4Rya795UzixA92r4ehUhEAGZlbLqVBlN+BlUAKaEVAaejvV0BMrJFk7bdAX0YmqAjg8b7fB8nCGJkuX+g= ARC-Authentication-Results: i=1; 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Tue, 12 Aug 2025 17:40:13 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:13 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 03/10] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Date: Tue, 12 Aug 2025 17:40:00 +0800 Message-ID: <20250812094011.2617526-4-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991748669116600 From: Kane-Chen-AS The has_otp attribute is enabled in the SBC subclasses for AST2600 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600.c | 2 +- hw/misc/aspeed_sbc.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index d12707f0ab..59ffd41a4a 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -261,7 +261,7 @@ static void aspeed_soc_ast2600_init(Object *obj) =20 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); =20 - object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); + object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC); =20 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DE= VICE); object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DE= VICE); diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index 46a038337c..b56a8b7678 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -273,8 +273,10 @@ static const TypeInfo aspeed_sbc_info =3D { static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, const void *= data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSBCClass *sc =3D ASPEED_SBC_CLASS(klass); =20 dc->desc =3D "AST2600 Secure Boot Controller"; + sc->has_otp =3D true; } =20 static const TypeInfo aspeed_ast2600_sbc_info =3D { --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1754991839; cv=none; d=zohomail.com; s=zohoarc; b=jHuNA9RVWumunqn1m3BIgES79nQRBozTogLFg1zafepjNfuHQG2Y5Ls/2NOGSpraI0lQQOx+V3BdGB29g0cd4LSICsugfXEbYPwFfZ+Q9zkagakUT6YMQoEmiyeI8X9MEn6WZol6Nyft1d6KJvs5KjJKqHc2Now0ZSy4o/benHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754991839; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 12 Aug 2025 05:40:50 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 17:40:13 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:13 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 04/10] hw/nvram/aspeed_otp: Add 'drive' property to support block backend Date: Tue, 12 Aug 2025 17:40:01 +0800 Message-ID: <20250812094011.2617526-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991840971124100 From: Kane-Chen-AS This patch introduces a 'drive' property to the Aspeed OTP device, allowing it to be backed by a block device. Users can now preload OTP data via QEMU CLI using a block backend. Example usage: ./qemu-system-arm \ -blockdev driver=3Dfile,filename=3Dotpmem.img,node-name=3Dotp \ -global aspeed-otp.drive=3Dotp \ ... If the drive is provided, its content will be loaded as the initial OTP state. Otherwise, an internal memory buffer will be used. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- hw/nvram/aspeed_otp.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c index e5b7ca9676..abb3731823 100644 --- a/hw/nvram/aspeed_otp.c +++ b/hw/nvram/aspeed_otp.c @@ -35,13 +35,25 @@ static bool aspeed_otp_init_storage(AspeedOTPState *s, = Error **errp) { uint32_t *p; int i, num; + uint64_t perm; =20 + if (s->blk) { + perm =3D BLK_PERM_CONSISTENT_READ | + (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); + if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) { + return false; + } + if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) { + error_setg(errp, "Failed to read the initial flash content"); + return false; + } + } else { num =3D s->size / sizeof(uint32_t); p =3D (uint32_t *)s->storage; for (i =3D 0; i < num; i++) { p[i] =3D (i % 2 =3D=3D 0) ? 0x00000000 : 0xFFFFFFFF; } - + } return true; } =20 @@ -75,6 +87,7 @@ static void aspeed_otp_realize(DeviceState *dev, Error **= errp) =20 static const Property aspeed_otp_properties[] =3D { DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0), + DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk), }; =20 static void aspeed_otp_class_init(ObjectClass *klass, const void *data) --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1754991841935617.7572861853159; Tue, 12 Aug 2025 02:44:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ullVW-0007r6-3r; Tue, 12 Aug 2025 05:41:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullV6-0007Um-Hb; Tue, 12 Aug 2025 05:41:06 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullUy-0000Yh-94; Tue, 12 Aug 2025 05:40:59 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 17:40:14 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:14 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Date: Tue, 12 Aug 2025 17:40:02 +0800 Message-ID: <20250812094011.2617526-6-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991842982124100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Implement correct OTP programming behavior for Aspeed OTP: - Support read-modify-write flow with one-way bit programming: * prog_bit uses 0s as the "to-be-programmed" mask. * Even-indexed words: 0->1, odd-indexed words: 1->0. * Reject non-programmable requests and log conflicts. - Enable unaligned accesses in MemoryRegionOps. Since each OTP address maps to a 1DW (4B) or 2DW (8B) block in the backing store, upper-layer accesses may be unaligned to block boundaries. This matches the irreversible, word-parity-dependent programming rules of Aspeed SoCs and exposes changes via QEMU trace events. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- hw/nvram/aspeed_otp.c | 80 ++++++++++++++++++++++++++++++++++++++++++- hw/nvram/trace-events | 5 +++ 2 files changed, 84 insertions(+), 1 deletion(-) diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c index abb3731823..66b2bfea28 100644 --- a/hw/nvram/aspeed_otp.c +++ b/hw/nvram/aspeed_otp.c @@ -12,6 +12,7 @@ #include "system/block-backend.h" #include "hw/qdev-properties.h" #include "hw/nvram/aspeed_otp.h" +#include "hw/nvram/trace.h" =20 static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size) { @@ -23,12 +24,87 @@ static uint64_t aspeed_otp_read(void *opaque, hwaddr of= fset, unsigned size) return val; } =20 +static bool valid_program_data(uint32_t otp_addr, + uint32_t value, uint32_t prog_bit) +{ + uint32_t programmed_bits, has_programmable_bits; + bool is_odd =3D otp_addr & 1; + + /* + * prog_bit uses 0s to indicate target bits to program: + * - if OTP word is even-indexed, programmed bits flip 0->1 + * - if odd, bits flip 1->0 + * Bit programming is one-way only and irreversible. + */ + if (is_odd) { + programmed_bits =3D ~value & prog_bit; + } else { + programmed_bits =3D value & (~prog_bit); + } + + /* If any bit can be programmed, accept the request */ + has_programmable_bits =3D value ^ (~prog_bit); + + if (programmed_bits) { + trace_aspeed_otp_prog_conflict(otp_addr, programmed_bits); + for (int i =3D 0; i < 32; ++i) { + if (programmed_bits & (1U << i)) { + trace_aspeed_otp_prog_bit(i); + } + } + } + + return has_programmable_bits !=3D 0; +} + +static bool program_otpmem_data(void *opaque, uint32_t otp_addr, + uint32_t prog_bit, uint32_t *value) +{ + AspeedOTPState *s =3D opaque; + bool is_odd =3D otp_addr & 1; + uint32_t otp_offset =3D otp_addr << 2; + + memcpy(value, s->storage + otp_offset, sizeof(uint32_t)); + + if (!valid_program_data(otp_addr, *value, prog_bit)) { + return false; + } + + if (is_odd) { + *value &=3D ~prog_bit; + } else { + *value |=3D ~prog_bit; + } + + return true; +} + static void aspeed_otp_write(void *opaque, hwaddr otp_addr, uint64_t val, unsigned size) { AspeedOTPState *s =3D opaque; + uint32_t otp_offset, value; =20 - memcpy(s->storage + otp_addr, &val, size); + if (!program_otpmem_data(s, otp_addr, val, &value)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Failed to program data, value =3D %x, bit =3D %= lx\n", + __func__, value, val); + return; + } + + otp_offset =3D otp_addr << 2; + memcpy(s->storage + otp_offset, &value, size); + + if (s->blk) { + if (blk_pwrite(s->blk, otp_offset, size, &value, 0) < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Failed to write %x to %x\n", + __func__, value, otp_offset); + + return; + } + } + trace_aspeed_otp_prog(otp_offset, val, value); } =20 static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp) @@ -63,6 +139,8 @@ static const MemoryRegionOps aspeed_otp_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, + .valid.unaligned =3D true, + .impl.unaligned =3D true }; =20 static void aspeed_otp_realize(DeviceState *dev, Error **errp) diff --git a/hw/nvram/trace-events b/hw/nvram/trace-events index 5e33b24d47..7084bf70d3 100644 --- a/hw/nvram/trace-events +++ b/hw/nvram/trace-events @@ -1,5 +1,10 @@ # See docs/devel/tracing.rst for syntax documentation. =20 +# aspeed_otp.c +aspeed_otp_prog(uint32_t addr, uint32_t prog_value, uint32_t value) "OTP M= emory program: addr 0x%" PRIx32 " prog_value 0x%" PRIx32 " value 0x%" PRIx32 +aspeed_otp_prog_conflict(uint32_t addr, uint32_t bits) "Conflict at addr= =3D0x%x, bits=3D0x%08x" +aspeed_otp_prog_bit(int bit) "Programmed bit %d" + # ds1225y.c nvram_read(uint32_t addr, uint32_t ret) "read addr %d: 0x%02x" nvram_write(uint32_t addr, uint32_t old, uint32_t val) "write addr %d: 0x%= 02x -> 0x%02x" --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1754991827; cv=none; d=zohomail.com; s=zohoarc; b=AIxag0nbr9YPTXyXkIuhm4cHxE8+34JvNVdiMSK7Z/rZ7S4gJBjh/M1Uwq6LUuhuksmKjgLZIvvcAp+iAQm7UMV7xP+fs/NrvjXELHmAkVnt/hgExwppk5Eqj19xMreKVIvTYM9XQ8QRqeh+kljfSZ8XoH6dyUDdpY4hx6ZXVz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754991827; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=b18vDFH2pPI2jmKv/dBz9269KF81bPZz+SdjEAHzk0M=; b=L7V2tShpx1QiAXXkc4yt1HB9k1ssfOxWr9AnyPfbVUk8KcsLZxmmwhMUGkMAaEUdndOsu33MIpd9STOUdKfqKVues1yZieroPlH7IbWfApY7H39EObrov4JsrgyapuAlEU1O/bPeTtYpt6atZdO+90ftPXE8Zx0rECQfIKkFWBk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1754991827650654.4041244527792; Tue, 12 Aug 2025 02:43:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ullVY-0007wc-NP; Tue, 12 Aug 2025 05:41:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullVF-0007WQ-Qa; Tue, 12 Aug 2025 05:41:12 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullVB-0000Yh-Eh; Tue, 12 Aug 2025 05:41:09 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 17:40:14 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:14 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Date: Tue, 12 Aug 2025 17:40:03 +0800 Message-ID: <20250812094011.2617526-7-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991828873124100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS The has_otp attribute is enabled in the SBC subclasses for AST1030 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_sbc.h | 1 + hw/arm/aspeed_ast10x0.c | 2 +- hw/misc/aspeed_sbc.c | 16 ++++++++++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h index 0c2746d392..7d640a022e 100644 --- a/include/hw/misc/aspeed_sbc.h +++ b/include/hw/misc/aspeed_sbc.h @@ -14,6 +14,7 @@ =20 #define TYPE_ASPEED_SBC "aspeed.sbc" #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600" +#define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10x0" OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC) =20 #define ASPEED_SBC_NR_REGS (0x93c >> 2) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index e6e1ee63c1..c446e70b24 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -154,7 +154,7 @@ static void aspeed_soc_ast1030_init(Object *obj) =20 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); =20 - object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); + object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC); =20 for (i =3D 0; i < sc->wdts_num; i++) { snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index b56a8b7678..052c70fd42 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -285,9 +285,25 @@ static const TypeInfo aspeed_ast2600_sbc_info =3D { .class_init =3D aspeed_ast2600_sbc_class_init, }; =20 +static void aspeed_ast10x0_sbc_class_init(ObjectClass *klass, const void *= data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSBCClass *sc =3D ASPEED_SBC_CLASS(klass); + + dc->desc =3D "AST10X0 Secure Boot Controller"; + sc->has_otp =3D true; +} + +static const TypeInfo aspeed_ast10x0_sbc_info =3D { + .name =3D TYPE_ASPEED_AST10X0_SBC, + .parent =3D TYPE_ASPEED_SBC, + .class_init =3D aspeed_ast10x0_sbc_class_init, +}; + static void aspeed_sbc_register_types(void) { type_register_static(&aspeed_ast2600_sbc_info); + type_register_static(&aspeed_ast10x0_sbc_info); type_register_static(&aspeed_sbc_info); } =20 --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1754991745; cv=none; d=zohomail.com; s=zohoarc; b=Khokap6UFR0xGGBQ0woRxBFPhwmQEFJakYWWrpulauff/tnPSl2PctKY29sIRy3yClsOfoXgtIsmCHiyY6u/mPnKoipSpXeaPwXCulKwWkh088rgGQU0CdJBstiBPn9g5dhS2KpgmkACeH2SCxlnCtxjbN3/6npoC53ENXiwkG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754991745; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=94tHXEVv4bgTlDuXoIajiy8JMOkYKBXBgcbxka4AQMI=; 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Tue, 12 Aug 2025 05:41:16 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 17:40:15 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:15 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Date: Tue, 12 Aug 2025 17:40:04 +0800 Message-ID: <20250812094011.2617526-8-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991772220124101 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS The OTP space contains three types of entries: data, conf, and strap. Data entries consist of two DWORDs, while the other types contain only one DWORD. This change adds the R_CAMP2 register (0x024 / 4) to store the second DWORD when reading from the OTP data region. With this enhancement, OTP reads now correctly return both DWORDs for data entries via the CAMP registers, along with improved address validation and error handling. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_sbc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index 052c70fd42..787e2d0489 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -22,6 +22,7 @@ #define R_ADDR (0x010 / 4) #define R_STATUS (0x014 / 4) #define R_CAMP1 (0x020 / 4) +#define R_CAMP2 (0x024 / 4) #define R_QSR (0x040 / 4) =20 /* R_STATUS */ @@ -50,6 +51,8 @@ #define SBC_OTP_CMD_READ 0x23b1e361 #define SBC_OTP_CMD_PROG 0x23b1e364 =20 +#define OTP_DATA_DWORD_COUNT (0x800) +#define OTP_TOTAL_DWORD_COUNT (0x1000) static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int si= ze) { AspeedSBCState *s =3D ASPEED_SBC(opaque); @@ -72,6 +75,16 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s, MemTxResult ret; AspeedOTPState *otp =3D &s->otp; uint32_t value, otp_offset; + bool is_data =3D false; + + if (otp_addr < OTP_DATA_DWORD_COUNT) { + is_data =3D true; + } else if (otp_addr >=3D OTP_TOTAL_DWORD_COUNT) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid OTP addr 0x%x\n", + otp_addr); + return false; + } =20 otp_offset =3D otp_addr << 2; ret =3D address_space_read(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIE= D, @@ -85,6 +98,20 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s, s->regs[R_CAMP1] =3D value; trace_aspeed_sbc_otp_read(otp_addr, value); =20 + if (is_data) { + ret =3D address_space_read(&otp->as, otp_offset + 4, + MEMTXATTRS_UNSPECIFIED, + &value, sizeof(value)); + if (ret !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "Failed to read OTP memory, addr =3D %x\n", + otp_addr); + return false; + } + s->regs[R_CAMP2] =3D value; + trace_aspeed_sbc_otp_read(otp_addr + 1, value); + } + return true; } =20 --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1754991839480213.8837162698312; Tue, 12 Aug 2025 02:43:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ullVY-0007wE-4h; Tue, 12 Aug 2025 05:41:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullVS-0007mC-7K; Tue, 12 Aug 2025 05:41:22 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ullVO-0000lv-6y; Tue, 12 Aug 2025 05:41:21 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 17:40:15 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:15 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Date: Tue, 12 Aug 2025 17:40:05 +0800 Message-ID: <20250812094011.2617526-9-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991841446116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Extend OTP command handling to recognize specific voltage mode register addresses and emulate the expected hardware behavior. Without this change, legitimate voltage mode change requests would be incorrectly reported as "Unknown command" and logged as an error. This implementation does not perform actual mode changes, but ensures that valid requests are accepted and ignored as per hardware behavior. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_sbc.c | 41 +++++++++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 1 + 2 files changed, 42 insertions(+) diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index 787e2d0489..2fc5db749d 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -49,10 +49,17 @@ #define OTP_MEMORY_SIZE 0x4000 /* OTP command */ #define SBC_OTP_CMD_READ 0x23b1e361 +#define SBC_OTP_CMD_WRITE 0x23b1e362 #define SBC_OTP_CMD_PROG 0x23b1e364 =20 #define OTP_DATA_DWORD_COUNT (0x800) #define OTP_TOTAL_DWORD_COUNT (0x1000) + +/* Voltage mode */ +#define MODE_REGISTER (0x1000) +#define MODE_REGISTER_A (0x3000) +#define MODE_REGISTER_B (0x5000) + static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int si= ze) { AspeedSBCState *s =3D ASPEED_SBC(opaque); @@ -115,6 +122,37 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s, return true; } =20 +static bool mode_handler(uint32_t otp_addr) +{ + switch (otp_addr) { + case MODE_REGISTER: + case MODE_REGISTER_A: + case MODE_REGISTER_B: + /* HW behavior, do nothing here */ + return true; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "Unsupported address 0x%x\n", + otp_addr); + return false; + } +} + +static bool aspeed_sbc_otp_write(AspeedSBCState *s, + uint32_t otp_addr) +{ + if (otp_addr =3D=3D 0) { + trace_aspeed_sbc_ignore_cmd(otp_addr); + return true; + } else { + if (mode_handler(otp_addr) =3D=3D false) { + return false; + } + } + + return true; +} + static bool aspeed_sbc_otp_prog(AspeedSBCState *s, uint32_t otp_addr) { @@ -157,6 +195,9 @@ static void aspeed_sbc_handle_command(void *opaque, uin= t32_t cmd) case SBC_OTP_CMD_READ: ret =3D aspeed_sbc_otp_read(s, otp_addr); break; + case SBC_OTP_CMD_WRITE: + ret =3D aspeed_sbc_otp_write(s, otp_addr); + break; case SBC_OTP_CMD_PROG: ret =3D aspeed_sbc_otp_prog(s, otp_addr); break; diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 9e05b82f37..eeb9243898 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -91,6 +91,7 @@ slavio_led_mem_writew(uint32_t val) "Write diagnostic LED= 0x%04x" slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" =20 # aspeed_sbc.c +aspeed_sbc_ignore_cmd(uint32_t cmd) "Ignoring command 0x%" PRIx32 aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling com= mand 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d" aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr = 0x%" PRIx32 " value 0x%" PRIx32 aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr= 0x%" PRIx32 " value 0x%" PRIx32 --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 12 Aug 2025 17:40:16 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:16 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test Date: Tue, 12 Aug 2025 17:40:06 +0800 Message-ID: <20250812094011.2617526-10-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991832285124100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS On boot, the SoC firmware reads data from the OTP region to obtain the chip ID and default settings. This change adds test cases to verify that the firmware can boot correctly with a pre-configured OTP image. Signed-off-by: Kane-Chen-AS --- tests/functional/meson.build | 2 + tests/functional/test_arm_aspeed_otp.py | 55 +++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 tests/functional/test_arm_aspeed_otp.py diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 311c6f1806..c731b779dd 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -34,6 +34,7 @@ test_timeouts =3D { 'arm_aspeed_bletchley' : 480, 'arm_aspeed_catalina' : 480, 'arm_aspeed_gb200nvl_bmc' : 480, + 'arm_aspeed_otp': 1200, 'arm_aspeed_rainier' : 480, 'arm_bpim2u' : 500, 'arm_collie' : 180, @@ -132,6 +133,7 @@ tests_arm_system_thorough =3D [ 'arm_aspeed_bletchley', 'arm_aspeed_catalina', 'arm_aspeed_gb200nvl_bmc', + 'arm_aspeed_otp', 'arm_aspeed_rainier', 'arm_bpim2u', 'arm_canona1100', diff --git a/tests/functional/test_arm_aspeed_otp.py b/tests/functional/tes= t_arm_aspeed_otp.py new file mode 100644 index 0000000000..48c7cad3f3 --- /dev/null +++ b/tests/functional/test_arm_aspeed_otp.py @@ -0,0 +1,55 @@ +import os +import time +import tempfile +import subprocess + +from qemu_test import LinuxKernelTest, Asset +from aspeed import AspeedTest +from qemu_test import exec_command_and_wait_for_pattern, skipIfMissingComm= ands + +class AspeedOtpMemoryTest(AspeedTest): + # AST2600 SDK image + ASSET_SDK_V907_AST2600 =3D Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.0= 7/ast2600-default-obmc.tar.gz', + 'cb6c08595bcbba1672ce716b068ba4e48eda1ed9abe78a07b30392ba2278feba') + + # AST1030 Zephyr image + ASSET_ZEPHYR_3_02 =3D Asset( + 'https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.03= .02/ast1030-evb-demo.zip', + '1ec83caab3ddd5d09481772801be7210e222cb015ce22ec6fffb8a76956dcd4f') + + def generate_otpmem_image(self): + path =3D self.scratch_file("otpmem.img") + pattern =3D b'\x00\x00\x00\x00\xff\xff\xff\xff' * (16 * 1024 // 8) + with open(path, "wb") as f: + f.write(pattern) + return path + + def test_ast2600_otp_blockdev_device(self): + image_path =3D self.archive_extract(self.ASSET_SDK_V907_AST2600) + otp_img =3D self.generate_otpmem_image() + self.vm.set_machine("ast2600-evb") + self.vm.set_console() + self.vm.add_args( + "-blockdev", f"driver=3Dfile,filename=3D{otp_img},node-name=3D= otp", + "-global", "aspeed-otp.drive=3Dotp", + ) + self.do_test_arm_aspeed_sdk_start(self.scratch_file("ast2600-defau= lt", "image-bmc")) + self.wait_for_console_pattern("ast2600-default login:") + + def test_ast1030_otp_blockdev_device(self): + kernel_name =3D "ast1030-evb-demo-3/zephyr.elf" + kernel_file =3D self.archive_extract(self.ASSET_ZEPHYR_3_02, membe= r=3Dkernel_name) + otp_img =3D self.generate_otpmem_image() + self.vm.set_machine("ast1030-evb") + self.vm.set_console() + self.vm.add_args( + "-kernel", kernel_file, + "-blockdev", f"driver=3Dfile,filename=3D{otp_img},node-name=3D= otp", + "-global", "aspeed-otp.drive=3Dotp", + ) + self.vm.launch() + self.wait_for_console_pattern("Booting Zephyr OS") + +if __name__ =3D=3D '__main__': + AspeedTest.main() --=20 2.43.0 From nobody Sat Nov 15 05:35:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 12 Aug 2025 17:40:16 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 17:40:16 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options Date: Tue, 12 Aug 2025 17:40:07 +0800 Message-ID: <20250812094011.2617526-11-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812094011.2617526-1-kane_chen@aspeedtech.com> References: <20250812094011.2617526-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754991769993124100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Add documentation for the OTP memory module used by AST2600 and AST1030 SoCs, and describe options for using a pre-generated image or an internal buffer. Include example commands for configuration and image generation. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index bf18c56347..6317c0e910 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -243,6 +243,37 @@ under Linux), use : =20 -M ast2500-evb,bmc-console=3Duart3 =20 +OTP Option +^^^^^^^^^^ + +Both the AST2600 and AST1030 chips use the same One Time Programmable +(OTP) memory module, which is utilized for configuration, key storage, +and storing user-programmable data. This OTP memory module is managed +by the Secure Boot Controller (SBC). The following options can be +specified or omitted based on your needs. + + * When the options are specified, the pre-generated configuration + file will be used as the OTP memory storage. + + * When the options are omitted, an internal memory buffer will be + used to store the OTP memory data. + +.. code-block:: bash + + -blockdev driver=3Dfile,filename=3Dotpmem.img,node-name=3Dotp \ + -global aspeed-otp.drive=3Dotp \ + +The following bash command can be used to generate a default +configuration file for OTP memory: + +.. code-block:: bash + + if [ ! -f otpmem.img ]; then + for i in $(seq 1 2048); do + printf '\x00\x00\x00\x00\xff\xff\xff\xff' + done > otpmem.img + fi + Aspeed 2700 family boards (``ast2700-evb``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 --=20 2.43.0