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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654548166116600 Add a XIVE2 controller to Power11 chip and machine. The controller has the same logic as Power10. Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 121 ++++++++++++++++++++++++++++++++++++++++++- include/hw/ppc/pnv.h | 18 +++++++ 2 files changed, 138 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b21c4aafaecb..eb89dd8b5a89 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -975,6 +975,7 @@ static void pnv_chip_power11_pic_print_info(PnvChip *ch= ip, GString *buf) { Pnv11Chip *chip11 =3D PNV11_CHIP(chip); =20 + pnv_xive2_pic_print_info(&chip11->xive, buf); pnv_psi_pic_print_info(&chip11->psi, buf); } =20 @@ -1485,6 +1486,50 @@ static void pnv_chip_power10_intc_print_info(PnvChip= *chip, PowerPCCPU *cpu, xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); } =20 +static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) +{ + Pnv11Chip *chip11 =3D PNV11_CHIP(chip); + Error *local_err =3D NULL; + Object *obj; + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + /* + * The core creates its interrupt presenter but the XIVE2 interrupt + * controller object is initialized afterwards. Hopefully, it's + * only used at runtime. + */ + obj =3D xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive), + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + pnv_cpu->intc =3D obj; +} + +static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu) +{ + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); +} + +static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) +{ + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); + pnv_cpu->intc =3D NULL; +} + +static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cp= u, + GString *buf) +{ + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -2347,6 +2392,10 @@ static void pnv_chip_power11_instance_init(Object *o= bj) object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE); object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER= ); + + object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2); + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive), + "xive-fabric"); object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, TYPE_PNV_N1_CHIPLET); =20 @@ -2414,7 +2463,26 @@ static void pnv_chip_power11_realize(DeviceState *de= v, Error **errp) return; } =20 - /* WIP: XIVE added in future patch */ + /* XIVE2 interrupt controller */ + object_property_set_int(OBJECT(&chip11->xive), "ic-bar", + PNV11_XIVE2_IC_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "esb-bar", + PNV11_XIVE2_ESB_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "end-bar", + PNV11_XIVE2_END_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar", + PNV11_XIVE2_NVPG_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "nvc-bar", + PNV11_XIVE2_NVC_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "tm-bar", + PNV11_XIVE2_TM_BASE(chip), &error_fatal); + object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE, + &chip11->xive.xscom_regs); =20 /* Processor Service Interface (PSI) Host Bridge */ object_property_set_int(OBJECT(&chip11->psi), "bar", @@ -2615,6 +2683,10 @@ static void pnv_chip_power11_class_init(ObjectClass = *klass, const void *data) k->chip_cfam_id =3D 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ k->cores_mask =3D POWER11_CORE_MASK; k->get_pir_tir =3D pnv_get_pir_tir_p10; + k->intc_create =3D pnv_chip_power11_intc_create; + k->intc_reset =3D pnv_chip_power11_intc_reset; + k->intc_destroy =3D pnv_chip_power11_intc_destroy; + k->intc_print_info =3D pnv_chip_power11_intc_print_info; k->isa_create =3D pnv_chip_power11_isa_create; k->dt_populate =3D pnv_chip_power11_dt_populate; k->pic_print_info =3D pnv_chip_power11_pic_print_info; @@ -2967,6 +3039,45 @@ static int pnv10_xive_broadcast(XiveFabric *xfb, return 0; } =20 +static bool pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t prio= rity, + uint32_t logic_serv, + XiveTCTXMatch *match) +{ + PnvMachineState *pnv =3D PNV_MACHINE(xfb); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv11Chip *chip11 =3D PNV11_CHIP(pnv->chips[i]); + XivePresenter *xptr =3D XIVE_PRESENTER(&chip11->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + + xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, + cam_ignore, priority, logic_serv, match); + } + + return !!match->count; +} + +static int pnv11_xive_broadcast(XiveFabric *xfb, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, + uint8_t priority) +{ + PnvMachineState *pnv =3D PNV_MACHINE(xfb); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv11Chip *chip11 =3D PNV11_CHIP(pnv->chips[i]); + XivePresenter *xptr =3D XIVE_PRESENTER(&chip11->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + + xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority= ); + } + return 0; +} + static bool pnv_machine_get_big_core(Object *obj, Error **errp) { PnvMachineState *pnv =3D PNV_MACHINE(obj); @@ -3145,6 +3256,7 @@ static void pnv_machine_power11_class_init(ObjectClas= s *oc, const void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); static const char compat[] =3D "qemu,powernv11\0ibm,powernv"; =20 pmc->compat =3D compat; @@ -3154,6 +3266,9 @@ static void pnv_machine_power11_class_init(ObjectClas= s *oc, const void *data) pmc->quirk_tb_big_core =3D true; pmc->dt_power_mgt =3D pnv_dt_power_mgt; =20 + xfc->match_nvt =3D pnv11_xive_match_nvt; + xfc->broadcast =3D pnv11_xive_broadcast; + mc->desc =3D "IBM PowerNV (Non-Virtualized) Power11"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power11_v2.0"); =20 @@ -3287,6 +3402,10 @@ static const TypeInfo types[] =3D { .name =3D MACHINE_TYPE_NAME("powernv11"), .parent =3D TYPE_PNV_MACHINE, .class_init =3D pnv_machine_power11_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XIVE_FABRIC }, + { }, + }, }, { .name =3D MACHINE_TYPE_NAME("powernv10-rainier"), diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f0002627bcab..cbdddfc73cd4 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE #define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip) =20 +#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE +#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip) + +#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE +#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip) + +#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE +#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip) + +#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE +#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip) + +#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE +#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip) + +#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE +#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip) + #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) =20 #endif /* PPC_PNV_H */ --=20 2.50.1