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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654437384124100 Implement Pnv11Chip, currently without chiptod, xive and phb. Chiptod, XIVE, PHB are implemented in later patches. Since Power11 core is same as Power10, the implementation of Pnv11Chip is a duplicate of corresponding Pnv10Chip. Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 317 +++++++++++++++++++++++++++++++++++++ hw/ppc/pnv_core.c | 17 ++ include/hw/ppc/pnv.h | 20 +++ include/hw/ppc/pnv_chip.h | 7 + include/hw/ppc/pnv_xscom.h | 49 ++++++ 5 files changed, 410 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d84c9067edb3..7422b9063358 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -490,6 +490,37 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip= , void *fdt) pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); } =20 +static void pnv_chip_power11_dt_populate(PnvChip *chip, void *fdt) +{ + static const char compat[] =3D "ibm,power11-xscom\0ibm,xscom"; + int i; + + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV11_XSCOM_BASE(chip)), + cpu_to_be64(PNV11_XSCOM_SIZE), + compat, sizeof(compat)); + + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D chip->cores[i]; + int offset; + + offset =3D pnv_dt_core(chip, pnv_core, fdt); + + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", + pa_features_31, sizeof(pa_features_31)))); + + if (pnv_core->big_core) { + i++; /* Big-core groups two QEMU cores */ + } + } + + if (chip->ram_size) { + pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); + } + + pnv_dt_lpc(chip, fdt, 0, PNV11_LPCM_BASE(chip), PNV11_LPCM_SIZE); +} + static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) { uint32_t io_base =3D d->ioport_id; @@ -822,6 +853,26 @@ static ISABus *pnv_chip_power10_isa_create(PnvChip *ch= ip, Error **errp) return pnv_lpc_isa_create(&chip10->lpc, false, errp); } =20 +static ISABus *pnv_chip_power11_isa_create(PnvChip *chip, Error **errp) +{ + Pnv11Chip *chip11 =3D PNV11_CHIP(chip); + qemu_irq irq; + + irq =3D qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPCHC); + qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "LPCHC", 0, irq); + + irq =3D qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ0); + qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 0, irq); + irq =3D qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ1); + qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 1, irq); + irq =3D qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ2); + qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 2, irq); + irq =3D qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ3); + qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 3, irq); + + return pnv_lpc_isa_create(&chip11->lpc, false, errp); +} + static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) { return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); @@ -885,6 +936,12 @@ static uint64_t pnv_chip_power10_xscom_core_base(PnvCh= ip *chip, return PNV10_XSCOM_EC_BASE(core_id); } =20 +static uint64_t pnv_chip_power11_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV11_XSCOM_EC_BASE(core_id); +} + static bool pnv_match_cpu(const char *default_type, const char *cpu_type) { PowerPCCPUClass *ppc_default =3D @@ -914,6 +971,13 @@ static void pnv_chip_power10_pic_print_info(PnvChip *c= hip, GString *buf) pnv_chip_power9_pic_print_info_child, buf); } =20 +static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf) +{ + Pnv11Chip *chip11 =3D PNV11_CHIP(chip); + + pnv_psi_pic_print_info(&chip11->psi, buf); +} + /* Always give the first 1GB to chip 0 else we won't boot */ static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) { @@ -1451,6 +1515,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip = *chip, PowerPCCPU *cpu, =20 #define POWER10_CORE_MASK (0xffffffffffffffull) =20 +#define POWER11_CORE_MASK (0xffffffffffffffull) + static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 =3D PNV8_CHIP(obj); @@ -2264,6 +2330,211 @@ static void pnv_chip_power10_realize(DeviceState *d= ev, Error **errp) } } =20 +static void pnv_chip_power11_instance_init(Object *obj) +{ + Pnv11Chip *chip11 =3D PNV11_CHIP(obj); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(obj); + int i; + + object_initialize_child(obj, "adu", &chip11->adu, TYPE_PNV_ADU); + + /* + * Use Power10 device models for PSI/LPC/OCC/SBE/HOMER as corresponding + * device models for Power11 are same + */ + object_initialize_child(obj, "psi", &chip11->psi, TYPE_PNV10_PSI); + object_initialize_child(obj, "lpc", &chip11->lpc, TYPE_PNV10_LPC); + object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC); + object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE); + object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER= ); + object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, + TYPE_PNV_N1_CHIPLET); + + for (i =3D 0; i < pcc->i2c_num_engines; i++) { + object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I= 2C); + } + + for (i =3D 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { + object_initialize_child(obj, "pib_spic[*]", &chip11->pib_spic[i], + TYPE_PNV_SPI); + } +} + +static void pnv_chip_power11_quad_realize(Pnv11Chip *chip11, Error **errp) +{ + PnvChip *chip =3D PNV_CHIP(chip11); + int i; + + chip11->nr_quads =3D DIV_ROUND_UP(chip->nr_cores, 4); + chip11->quads =3D g_new0(PnvQuad, chip11->nr_quads); + + for (i =3D 0; i < chip11->nr_quads; i++) { + PnvQuad *eq =3D &chip11->quads[i]; + + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], + PNV_QUAD_TYPE_NAME("power11")); + + pnv_xscom_add_subregion(chip, PNV11_XSCOM_EQ_BASE(eq->quad_id), + &eq->xscom_regs); + + pnv_xscom_add_subregion(chip, PNV11_XSCOM_QME_BASE(eq->quad_id), + &eq->xscom_qme_regs); + } +} + +static void pnv_chip_power11_realize(DeviceState *dev, Error **errp) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); + PnvChip *chip =3D PNV_CHIP(dev); + Pnv11Chip *chip11 =3D PNV11_CHIP(dev); + Error *local_err =3D NULL; + int i; + + /* XSCOM bridge is first */ + pnv_xscom_init(chip, PNV11_XSCOM_SIZE, PNV11_XSCOM_BASE(chip)); + + pcc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* ADU */ + object_property_set_link(OBJECT(&chip11->adu), "lpc", OBJECT(&chip11->= lpc), + &error_abort); + if (!qdev_realize(DEVICE(&chip11->adu), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_ADU_BASE, + &chip11->adu.xscom_regs); + + pnv_chip_power11_quad_realize(chip11, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* WIP: XIVE added in future patch */ + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_int(OBJECT(&chip11->psi), "bar", + PNV11_PSIHB_BASE(chip), &error_fatal); + /* PSI can be configured to use 64k ESB pages on Power11 */ + object_property_set_int(OBJECT(&chip11->psi), "shift", XIVE_ESB_64K, + &error_fatal); + if (!qdev_realize(DEVICE(&chip11->psi), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_PSIHB_BASE, + &PNV_PSI(&chip11->psi)->xscom_regs); + + /* LPC */ + if (!qdev_realize(DEVICE(&chip11->lpc), NULL, errp)) { + return; + } + memory_region_add_subregion(get_system_memory(), PNV11_LPCM_BASE(chip), + &chip11->lpc.xscom_regs); + + chip->fw_mr =3D &chip11->lpc.isa_fw; + chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", + (uint64_t) PNV11_LPCM_BASE(chi= p)); + + /* HOMER (must be created before OCC) */ + object_property_set_link(OBJECT(&chip11->homer), "chip", OBJECT(chip), + &error_abort); + if (!qdev_realize(DEVICE(&chip11->homer), NULL, errp)) { + return; + } + /* Homer Xscom region */ + pnv_xscom_add_subregion(chip, PNV11_XSCOM_PBA_BASE, + &chip11->homer.pba_regs); + /* Homer RAM region */ + memory_region_add_subregion(get_system_memory(), chip11->homer.base, + &chip11->homer.mem); + + /* Create the simplified OCC model */ + object_property_set_link(OBJECT(&chip11->occ), "homer", + OBJECT(&chip11->homer), &error_abort); + if (!qdev_realize(DEVICE(&chip11->occ), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_OCC_BASE, + &chip11->occ.xscom_regs); + qdev_connect_gpio_out(DEVICE(&chip11->occ), 0, qdev_get_gpio_in( + DEVICE(&chip11->psi), PSIHB9_IRQ_OCC)); + + /* OCC SRAM model */ + memory_region_add_subregion(get_system_memory(), + PNV11_OCC_SENSOR_BASE(chip), + &chip11->occ.sram_regs); + + /* SBE */ + if (!qdev_realize(DEVICE(&chip11->sbe), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_CTRL_BASE, + &chip11->sbe.xscom_ctrl_regs); + pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_MBOX_BASE, + &chip11->sbe.xscom_mbox_regs); + qdev_connect_gpio_out(DEVICE(&chip11->sbe), 0, qdev_get_gpio_in( + DEVICE(&chip11->psi), PSIHB9_IRQ_PSU)); + + /* N1 chiplet */ + if (!qdev_realize(DEVICE(&chip11->n1_chiplet), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, + &chip11->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); + + pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_EQ_BASE, + &chip11->n1_chiplet.xscom_pb_eq_mr); + + pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE, + &chip11->n1_chiplet.xscom_pb_es_mr); + + /* WIP: PHB added in future patch */ + + /* + * I2C + */ + for (i =3D 0; i < pcc->i2c_num_engines; i++) { + Object *obj =3D OBJECT(&chip11->i2c[i]); + + object_property_set_int(obj, "engine", i + 1, &error_fatal); + object_property_set_int(obj, "num-busses", + pcc->i2c_ports_per_engine[i], + &error_fatal); + object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); + if (!qdev_realize(DEVICE(obj), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_I2CM_BASE + + (chip11->i2c[i].engine - 1) * + PNV11_XSCOM_I2CM_SIZE, + &chip11->i2c[i].xscom_regs); + qdev_connect_gpio_out(DEVICE(&chip11->i2c[i]), 0, + qdev_get_gpio_in(DEVICE(&chip11->psi), + PSIHB9_IRQ_SBE_I2C)); + } + /* PIB SPI Controller */ + for (i =3D 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { + object_property_set_int(OBJECT(&chip11->pib_spic[i]), "spic_num", + i, &error_fatal); + /* pib_spic[2] connected to 25csm04 which implements 1 byte transf= er */ + object_property_set_int(OBJECT(&chip11->pib_spic[i]), "transfer_le= n", + (i =3D=3D 2) ? 1 : 4, &error_fatal); + object_property_set_int(OBJECT(&chip11->pib_spic[i]), "chip-id", + chip->chip_id, &error_fatal); + if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT + (&chip11->pib_spic[i])), errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_PIB_SPIC_BASE + + i * PNV11_XSCOM_PIB_SPIC_SIZE, + &chip11->pib_spic[i].xscom_spic_regs); + } +} + static void pnv_rainier_i2c_init(PnvMachineState *pnv) { int i; @@ -2329,6 +2600,34 @@ static void pnv_chip_power10_class_init(ObjectClass = *klass, const void *data) &k->parent_realize); } =20 +static uint32_t pnv_chip_power11_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &=3D (PNV11_XSCOM_SIZE - 1); + return addr >> 3; +} + +static void pnv_chip_power11_class_init(ObjectClass *klass, const void *da= ta) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvChipClass *k =3D PNV_CHIP_CLASS(klass); + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] =3D {14, 14,= 2, 16}; + + k->chip_cfam_id =3D 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ + k->cores_mask =3D POWER11_CORE_MASK; + k->get_pir_tir =3D pnv_get_pir_tir_p10; + k->isa_create =3D pnv_chip_power11_isa_create; + k->dt_populate =3D pnv_chip_power11_dt_populate; + k->pic_print_info =3D pnv_chip_power11_pic_print_info; + k->xscom_core_base =3D pnv_chip_power11_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power11_xscom_pcba; + dc->desc =3D "PowerNV Chip Power11"; + k->i2c_num_engines =3D PNV10_CHIP_MAX_I2C; + k->i2c_ports_per_engine =3D i2c_ports_per_engine; + + device_class_set_parent_realize(dc, pnv_chip_power11_realize, + &k->parent_realize); +} + static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, Error **errp) { @@ -2947,6 +3246,13 @@ static void pnv_machine_class_init(ObjectClass *oc, = const void *data) .parent =3D TYPE_PNV10_CHIP, \ } =20 +#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV11_CHIP, \ + } + static const TypeInfo types[] =3D { { .name =3D MACHINE_TYPE_NAME("powernv10-rainier"), @@ -3002,6 +3308,17 @@ static const TypeInfo types[] =3D { .abstract =3D true, }, =20 + /* + * P11 chip and variants + */ + { + .name =3D TYPE_PNV11_CHIP, + .parent =3D TYPE_PNV_CHIP, + .instance_init =3D pnv_chip_power11_instance_init, + .instance_size =3D sizeof(Pnv11Chip), + }, + DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_i= nit), + /* * P10 chip and variants */ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 08c20224b97d..fb2dfc7ba212 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -473,6 +473,11 @@ static void pnv_core_power10_class_init(ObjectClass *o= c, const void *data) pcc->xscom_size =3D PNV10_XSCOM_EC_SIZE; } =20 +static void pnv_core_power11_class_init(ObjectClass *oc, const void *data) +{ + pnv_core_power10_class_init(oc, data); +} + static void pnv_core_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -504,6 +509,7 @@ static const TypeInfo pnv_core_infos[] =3D { DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), + DEFINE_PNV_CORE_TYPE(power11, "power11_v2.0"), }; =20 DEFINE_TYPES(pnv_core_infos) @@ -725,6 +731,12 @@ static void pnv_quad_power10_class_init(ObjectClass *o= c, const void *data) pqc->xscom_qme_size =3D PNV10_XSCOM_QME_SIZE; } =20 +static void pnv_quad_power11_class_init(ObjectClass *oc, const void *data) +{ + /* Power11 quad is similar to Power10 quad */ + pnv_quad_power10_class_init(oc, data); +} + static void pnv_quad_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -752,6 +764,11 @@ static const TypeInfo pnv_quad_infos[] =3D { .name =3D PNV_QUAD_TYPE_NAME("power10"), .class_init =3D pnv_quad_power10_class_init, }, + { + .parent =3D TYPE_PNV_QUAD, + .name =3D PNV_QUAD_TYPE_NAME("power11"), + .class_init =3D pnv_quad_power11_class_init, + }, }; =20 DEFINE_TYPES(pnv_quad_infos); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index d8fca079f2fe..f0002627bcab 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -33,6 +33,7 @@ typedef struct PnvChip PnvChip; typedef struct Pnv8Chip Pnv8Chip; typedef struct Pnv9Chip Pnv9Chip; typedef struct Pnv10Chip Pnv10Chip; +typedef struct Pnv10Chip Pnv11Chip; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX @@ -57,6 +58,10 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, TYPE_PNV_CHIP_POWER10) =20 +#define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11_v2.0") +DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11, + TYPE_PNV_CHIP_POWER11) + PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id); PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); =20 @@ -252,4 +257,19 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV10_HOMER_BASE(chip) \ (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) =20 +/* Power11 */ +#define PNV11_XSCOM_SIZE PNV10_XSCOM_SIZE +#define PNV11_XSCOM_BASE(chip) PNV10_XSCOM_BASE(chip) + +#define PNV11_LPCM_SIZE PNV10_LPCM_SIZE +#define PNV11_LPCM_BASE(chip) PNV10_LPCM_BASE(chip) + +#define PNV11_PSIHB_ESB_SIZE PNV10_PSIHB_ESB_SIZE +#define PNV11_PSIHB_ESB_BASE(chip) PNV10_PSIHB_ESB_BASE(chip) + +#define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE +#define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip) + +#define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) + #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 24ce37a9c8e4..6bd930f8b439 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -141,6 +141,13 @@ struct Pnv10Chip { #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) #define PNV10_PIR2THREAD(pir) (((pir) & 0x7f)) =20 +#define TYPE_PNV11_CHIP "pnv11-chip" +DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP, + TYPE_PNV11_CHIP) + +/* Power11 core is same as Power10 */ +typedef struct Pnv10Chip Pnv11Chip; + struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index b14549db7033..610b075a27c3 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -207,6 +207,55 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_PIB_SPIC_BASE 0xc0000 #define PNV10_XSCOM_PIB_SPIC_SIZE 0x20 =20 +/* + * Power11 core is same as Power10 + */ +#define PNV11_XSCOM_EC_BASE(core) PNV10_XSCOM_EC_BASE(core) + +#define PNV11_XSCOM_ADU_BASE PNV10_XSCOM_ADU_BASE +#define PNV11_XSCOM_ADU_SIZE PNV10_XSCOM_ADU_SIZE + +#define PNV11_XSCOM_QME_BASE(core) PNV10_XSCOM_QME_BASE(core) + +#define PNV11_XSCOM_EQ_BASE(core) PNV10_XSCOM_EQ_BASE(core) + +#define PNV11_XSCOM_PSIHB_BASE PNV10_XSCOM_PSIHB_BASE +#define PNV11_XSCOM_PSIHB_SIZE PNV10_XSCOM_PSIHB_SIZE + +#define PNV11_XSCOM_I2CM_BASE PNV10_XSCOM_I2CM_BASE +#define PNV11_XSCOM_I2CM_SIZE PNV10_XSCOM_I2CM_SIZE + +#define PNV11_XSCOM_CHIPTOD_BASE PNV10_XSCOM_CHIPTOD_BASE +#define PNV11_XSCOM_CHIPTOD_SIZE PNV10_XSCOM_CHIPTOD_SIZE + +#define PNV11_XSCOM_OCC_BASE PNV10_XSCOM_OCC_BASE +#define PNV11_XSCOM_OCC_SIZE PNV10_XSCOM_OCC_SIZE + +#define PNV11_XSCOM_SBE_CTRL_BASE PNV10_XSCOM_SBE_CTRL_BASE +#define PNV11_XSCOM_SBE_CTRL_SIZE PNV10_XSCOM_SBE_CTRL_SIZE + +#define PNV11_XSCOM_SBE_MBOX_BASE PNV10_XSCOM_SBE_MBOX_BASE +#define PNV11_XSCOM_SBE_MBOX_SIZE PNV10_XSCOM_SBE_MBOX_SIZE + +#define PNV11_XSCOM_PBA_BASE PNV10_XSCOM_PBA_BASE +#define PNV11_XSCOM_PBA_SIZE PNV10_XSCOM_PBA_SIZE + +#define PNV11_XSCOM_XIVE2_BASE PNV10_XSCOM_XIVE2_BASE +#define PNV11_XSCOM_XIVE2_SIZE PNV10_XSCOM_XIVE2_SIZE + +#define PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE \ + PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE +#define PNV11_XSCOM_CHIPLET_CTRL_REGS_SIZE PNV10_XSCOM_CHIPLET_CTRL_REGS= _SIZE + +#define PNV11_XSCOM_N1_PB_SCOM_EQ_BASE PNV10_XSCOM_N1_PB_SCOM_EQ_BASE +#define PNV11_XSCOM_N1_PB_SCOM_EQ_SIZE PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE + +#define PNV11_XSCOM_N1_PB_SCOM_ES_BASE PNV10_XSCOM_N1_PB_SCOM_ES_BASE +#define PNV11_XSCOM_N1_PB_SCOM_ES_SIZE PNV10_XSCOM_N1_PB_SCOM_ES_SIZE + +#define PNV11_XSCOM_PIB_SPIC_BASE PNV10_XSCOM_PIB_SPIC_BASE +#define PNV11_XSCOM_PIB_SPIC_SIZE PNV10_XSCOM_PIB_SPIC_SIZE + void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654449451124100 The Powernv11 machine doesn't have XIVE & PHBs as of now XIVE2 interface and PHB5 added in later patches to Powernv11 machine Also add mention of Power11 to powernv documentation Note: A difference from P10's and P11's machine_class_init is, in P11 different number of PHBs cannot be used on the command line, ie. the following line does NOT exist in pnv_machine_power11_class_init, which existed in case of Power10: machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- docs/system/ppc/powernv.rst | 9 +++++---- hw/ppc/pnv.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst index f3ec2cc69c0d..5154794cc8cd 100644 --- a/docs/system/ppc/powernv.rst +++ b/docs/system/ppc/powernv.rst @@ -1,5 +1,5 @@ -PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powern= v11``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 PowerNV (as Non-Virtualized) is the "bare metal" platform using the OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can @@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today. Supported devices ----------------- =20 - * Multi processor support for POWER8, POWER8NVL and POWER9. + * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Powe= r11. * XSCOM, serial communication sideband bus to configure chiplets. * Simple LPC Controller. * Processor Service Interface (PSI) Controller. - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1= 0). + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1= 0 & + Power11). * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge. * Simple OCC is an on-chip micro-controller used for power management tas= ks. * iBT device to handle BMC communication, with the internal BMC simulator diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7422b9063358..b21c4aafaecb 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -3141,6 +3141,35 @@ static void pnv_machine_p10_rainier_class_init(Objec= tClass *oc, pmc->i2c_init =3D pnv_rainier_i2c_init; } =20 +static void pnv_machine_power11_class_init(ObjectClass *oc, const void *da= ta) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + static const char compat[] =3D "qemu,powernv11\0ibm,powernv"; + + pmc->compat =3D compat; + pmc->compat_size =3D sizeof(compat); + pmc->max_smt_threads =3D 4; + pmc->has_lpar_per_thread =3D true; + pmc->quirk_tb_big_core =3D true; + pmc->dt_power_mgt =3D pnv_dt_power_mgt; + + mc->desc =3D "IBM PowerNV (Non-Virtualized) Power11"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power11_v2.0"); + + object_class_property_add_bool(oc, "big-core", + pnv_machine_get_big_core, + pnv_machine_set_big_core); + object_class_property_set_description(oc, "big-core", + "Use big-core (aka fused-core) mode"); + + object_class_property_add_bool(oc, "lpar-per-core", + pnv_machine_get_lpar_per_core, + pnv_machine_set_lpar_per_core); + object_class_property_set_description(oc, "lpar-per-core", + "Use 1 LPAR per core mode"); +} + static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) { CPUPPCState *env =3D cpu_env(cs); @@ -3254,6 +3283,11 @@ static void pnv_machine_class_init(ObjectClass *oc, = const void *data) } =20 static const TypeInfo types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("powernv11"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv_machine_power11_class_init, + }, { .name =3D MACHINE_TYPE_NAME("powernv10-rainier"), .parent =3D MACHINE_TYPE_NAME("powernv10"), --=20 2.50.1 From nobody Sat Nov 15 05:23:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654548166116600 Add a XIVE2 controller to Power11 chip and machine. The controller has the same logic as Power10. Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 121 ++++++++++++++++++++++++++++++++++++++++++- include/hw/ppc/pnv.h | 18 +++++++ 2 files changed, 138 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b21c4aafaecb..eb89dd8b5a89 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -975,6 +975,7 @@ static void pnv_chip_power11_pic_print_info(PnvChip *ch= ip, GString *buf) { Pnv11Chip *chip11 =3D PNV11_CHIP(chip); =20 + pnv_xive2_pic_print_info(&chip11->xive, buf); pnv_psi_pic_print_info(&chip11->psi, buf); } =20 @@ -1485,6 +1486,50 @@ static void pnv_chip_power10_intc_print_info(PnvChip= *chip, PowerPCCPU *cpu, xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); } =20 +static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) +{ + Pnv11Chip *chip11 =3D PNV11_CHIP(chip); + Error *local_err =3D NULL; + Object *obj; + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + /* + * The core creates its interrupt presenter but the XIVE2 interrupt + * controller object is initialized afterwards. Hopefully, it's + * only used at runtime. + */ + obj =3D xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive), + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + pnv_cpu->intc =3D obj; +} + +static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu) +{ + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); +} + +static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) +{ + PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + + xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); + pnv_cpu->intc =3D NULL; +} + +static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cp= u, + GString *buf) +{ + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -2347,6 +2392,10 @@ static void pnv_chip_power11_instance_init(Object *o= bj) object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE); object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER= ); + + object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2); + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive), + "xive-fabric"); object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, TYPE_PNV_N1_CHIPLET); =20 @@ -2414,7 +2463,26 @@ static void pnv_chip_power11_realize(DeviceState *de= v, Error **errp) return; } =20 - /* WIP: XIVE added in future patch */ + /* XIVE2 interrupt controller */ + object_property_set_int(OBJECT(&chip11->xive), "ic-bar", + PNV11_XIVE2_IC_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "esb-bar", + PNV11_XIVE2_ESB_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "end-bar", + PNV11_XIVE2_END_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar", + PNV11_XIVE2_NVPG_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "nvc-bar", + PNV11_XIVE2_NVC_BASE(chip), &error_fatal); + object_property_set_int(OBJECT(&chip11->xive), "tm-bar", + PNV11_XIVE2_TM_BASE(chip), &error_fatal); + object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE, + &chip11->xive.xscom_regs); =20 /* Processor Service Interface (PSI) Host Bridge */ object_property_set_int(OBJECT(&chip11->psi), "bar", @@ -2615,6 +2683,10 @@ static void pnv_chip_power11_class_init(ObjectClass = *klass, const void *data) k->chip_cfam_id =3D 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ k->cores_mask =3D POWER11_CORE_MASK; k->get_pir_tir =3D pnv_get_pir_tir_p10; + k->intc_create =3D pnv_chip_power11_intc_create; + k->intc_reset =3D pnv_chip_power11_intc_reset; + k->intc_destroy =3D pnv_chip_power11_intc_destroy; + k->intc_print_info =3D pnv_chip_power11_intc_print_info; k->isa_create =3D pnv_chip_power11_isa_create; k->dt_populate =3D pnv_chip_power11_dt_populate; k->pic_print_info =3D pnv_chip_power11_pic_print_info; @@ -2967,6 +3039,45 @@ static int pnv10_xive_broadcast(XiveFabric *xfb, return 0; } =20 +static bool pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t prio= rity, + uint32_t logic_serv, + XiveTCTXMatch *match) +{ + PnvMachineState *pnv =3D PNV_MACHINE(xfb); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv11Chip *chip11 =3D PNV11_CHIP(pnv->chips[i]); + XivePresenter *xptr =3D XIVE_PRESENTER(&chip11->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + + xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, + cam_ignore, priority, logic_serv, match); + } + + return !!match->count; +} + +static int pnv11_xive_broadcast(XiveFabric *xfb, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, + uint8_t priority) +{ + PnvMachineState *pnv =3D PNV_MACHINE(xfb); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv11Chip *chip11 =3D PNV11_CHIP(pnv->chips[i]); + XivePresenter *xptr =3D XIVE_PRESENTER(&chip11->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + + xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority= ); + } + return 0; +} + static bool pnv_machine_get_big_core(Object *obj, Error **errp) { PnvMachineState *pnv =3D PNV_MACHINE(obj); @@ -3145,6 +3256,7 @@ static void pnv_machine_power11_class_init(ObjectClas= s *oc, const void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); static const char compat[] =3D "qemu,powernv11\0ibm,powernv"; =20 pmc->compat =3D compat; @@ -3154,6 +3266,9 @@ static void pnv_machine_power11_class_init(ObjectClas= s *oc, const void *data) pmc->quirk_tb_big_core =3D true; pmc->dt_power_mgt =3D pnv_dt_power_mgt; =20 + xfc->match_nvt =3D pnv11_xive_match_nvt; + xfc->broadcast =3D pnv11_xive_broadcast; + mc->desc =3D "IBM PowerNV (Non-Virtualized) Power11"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power11_v2.0"); =20 @@ -3287,6 +3402,10 @@ static const TypeInfo types[] =3D { .name =3D MACHINE_TYPE_NAME("powernv11"), .parent =3D TYPE_PNV_MACHINE, .class_init =3D pnv_machine_power11_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XIVE_FABRIC }, + { }, + }, }, { .name =3D MACHINE_TYPE_NAME("powernv10-rainier"), diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f0002627bcab..cbdddfc73cd4 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE #define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip) =20 +#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE +#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip) + +#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE +#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip) + +#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE +#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip) + +#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE +#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip) + +#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE +#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip) + +#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE +#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip) + #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) =20 #endif /* PPC_PNV_H */ --=20 2.50.1 From nobody Sat Nov 15 05:23:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654944716116600 Power11 also uses PHB5, same as Power10. Add Power11 PHBs with similar code as the corresponding Power10 implementat= ion. Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index eb89dd8b5a89..5392b1b417b6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -977,6 +977,8 @@ static void pnv_chip_power11_pic_print_info(PnvChip *ch= ip, GString *buf) =20 pnv_xive2_pic_print_info(&chip11->xive, buf); pnv_psi_pic_print_info(&chip11->psi, buf); + object_child_foreach_recursive(OBJECT(chip), + pnv_chip_power9_pic_print_info_child, buf); } =20 /* Always give the first 1GB to chip 0 else we won't boot */ @@ -2377,6 +2379,7 @@ static void pnv_chip_power10_realize(DeviceState *dev= , Error **errp) =20 static void pnv_chip_power11_instance_init(Object *obj) { + PnvChip *chip =3D PNV_CHIP(obj); Pnv11Chip *chip11 =3D PNV11_CHIP(obj); PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(obj); int i; @@ -2399,6 +2402,13 @@ static void pnv_chip_power11_instance_init(Object *o= bj) object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, TYPE_PNV_N1_CHIPLET); =20 + chip->num_pecs =3D pcc->num_pecs; + + for (i =3D 0; i < chip->num_pecs; i++) { + object_initialize_child(obj, "pec[*]", &chip11->pecs[i], + TYPE_PNV_PHB5_PEC); + } + for (i =3D 0; i < pcc->i2c_num_engines; i++) { object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I= 2C); } @@ -2431,6 +2441,38 @@ static void pnv_chip_power11_quad_realize(Pnv11Chip = *chip11, Error **errp) } } =20 +static void pnv_chip_power11_phb_realize(PnvChip *chip, Error **errp) +{ + Pnv11Chip *chip11 =3D PNV11_CHIP(chip); + int i; + + for (i =3D 0; i < chip->num_pecs; i++) { + PnvPhb4PecState *pec =3D &chip11->pecs[i]; + PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); + uint32_t pec_cplt_base; + uint32_t pec_nest_base; + uint32_t pec_pci_base; + + object_property_set_int(OBJECT(pec), "index", i, &error_fatal); + object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, + &error_fatal); + object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), + &error_fatal); + if (!qdev_realize(DEVICE(pec), NULL, errp)) { + return; + } + + pec_cplt_base =3D pecc->xscom_cplt_base(pec); + pec_nest_base =3D pecc->xscom_nest_base(pec); + pec_pci_base =3D pecc->xscom_pci_base(pec); + + pnv_xscom_add_subregion(chip, pec_cplt_base, + &pec->nest_pervasive.xscom_ctrl_regs_mr); + pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); + pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); + } +} + static void pnv_chip_power11_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); @@ -2560,7 +2602,12 @@ static void pnv_chip_power11_realize(DeviceState *de= v, Error **errp) pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE, &chip11->n1_chiplet.xscom_pb_es_mr); =20 - /* WIP: PHB added in future patch */ + /* PHBs */ + pnv_chip_power11_phb_realize(chip, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } =20 /* * I2C @@ -2693,6 +2740,7 @@ static void pnv_chip_power11_class_init(ObjectClass *= klass, const void *data) k->xscom_core_base =3D pnv_chip_power11_xscom_core_base; k->xscom_pcba =3D pnv_chip_power11_xscom_pcba; dc->desc =3D "PowerNV Chip Power11"; + k->num_pecs =3D PNV10_CHIP_MAX_PEC; k->i2c_num_engines =3D PNV10_CHIP_MAX_I2C; k->i2c_ports_per_engine =3D i2c_ports_per_engine; =20 @@ -3259,6 +3307,13 @@ static void pnv_machine_power11_class_init(ObjectCla= ss *oc, const void *data) XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); static const char compat[] =3D "qemu,powernv11\0ibm,powernv"; =20 + static GlobalProperty phb_compat[] =3D { + { TYPE_PNV_PHB, "version", "5" }, + { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, + }; + + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat= )); + pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); pmc->max_smt_threads =3D 4; --=20 2.50.1 From nobody Sat Nov 15 05:23:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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b=FkK6JTt9VyYliPJp7w+pAT SwZFVkXSiWKKI0Z0eY/szOezHlMbZtP2wWNqJevyN90UF30mSoGKa+LibNWvl/Na ykNvOulgbNU3GF/b4PQnMJEb2YXH5BuY6uiXJSOVOPel17lC13oT2X+sJPC2Mkb9 Jydm3Y1OSePhNu/hvxZ4v+v0ROWsEcfKaq9DKNOwNEOLIzeYWBC7bTO9yT4xYFq2 PHxgKw4VFansjjqvd2i6dksWP8XBE/gKDg2Jol0bNcxPaqMk1vGBAVaM3jsCIg02 0HSrk1uZowzxSV4p+a7ItByOA/6R1f5U3BC66VyoS+d/Avmva6c5TXayD6FlpPPg == From: Aditya Gupta To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , Harsh Prateek Bora Cc: Mahesh J Salgaonkar , Madhavan Srinivasan , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH v9 5/7] ppc/pnv: Add ChipTOD model for Power11 Date: Fri, 8 Aug 2025 17:29:27 +0530 Message-ID: <20250808115929.1073910-6-adityag@linux.ibm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250808115929.1073910-1-adityag@linux.ibm.com> References: <20250808115929.1073910-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Ho4cx93SpwUFZgb4NoCAeVFmNpMeHAnv X-Proofpoint-ORIG-GUID: KwBd-a0ZXbKi3wZ4FjGU2dRa0dMFdnmF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA4MDA5NiBTYWx0ZWRfXwEu0RfK1YZIT rRgXd/KoTB5ioI1y1BS7FVALyFnGB1wKkfWnCRLq6Li6JHlSNqVjiB6XzKV2rd8vYYI0n0HVdGm ObzvQyXWWlbCx8wnXsg4eBqpeBbfH2yVgCYLj/9DxZvdu99l915POzwmcRS+/6VD6x4H2KHEQuF vovhhTnk5aea0Jd7PKweu3dpLsXj5m6alNsCL0Ol1yawxmul2bHVWtZDbiI0LFH9FxBMdJfA6uQ FOvhHeNgQG9fCLLz4+XWn7mjSnQN8j119FV/+OjBkEoOttJwCRKUCK7QEFnXxW0SmY2KtOK/42B 2i6p4pcwQrx7jPZau222o5jkMdKTgwQa+8DegGY8nZb8PLB/VSvokU1rCTuzoHdCkrqIJ3cGVmb nvHRn/G6zEk73PSMlsPuFGSGhXCGs4p8C4q7AqZrG+ddbz4s7GuJqwAYblibnPUKpoJxUqdY X-Authority-Analysis: v=2.4 cv=TayWtQQh c=1 sm=1 tr=0 ts=6895e6c3 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=aow-egSQAAAA:8 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=20KFwNOVAAAA:8 a=b9eXF7Pav5jxbbk2SQIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=gFNbaldVC-z-bsjSTzMo:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_03,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508080096 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654535114124100 Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod code as the Power11 core is same as Power10 core. Cc: C=C3=A9dric Le Goater Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 15 +++++++++ hw/ppc/pnv_chiptod.c | 59 ++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_chiptod.h | 2 ++ 3 files changed, 76 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5392b1b417b6..673bb54c6789 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2399,6 +2399,8 @@ static void pnv_chip_power11_instance_init(Object *ob= j) object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2); object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive), "xive-fabric"); + object_initialize_child(obj, "chiptod", &chip11->chiptod, + TYPE_PNV11_CHIPTOD); object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, TYPE_PNV_N1_CHIPLET); =20 @@ -2549,6 +2551,19 @@ static void pnv_chip_power11_realize(DeviceState *de= v, Error **errp) chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", (uint64_t) PNV11_LPCM_BASE(chi= p)); =20 + /* ChipTOD */ + object_property_set_bool(OBJECT(&chip11->chiptod), "primary", + chip->chip_id =3D=3D 0, &error_abort); + object_property_set_bool(OBJECT(&chip11->chiptod), "secondary", + chip->chip_id =3D=3D 1, &error_abort); + object_property_set_link(OBJECT(&chip11->chiptod), "chip", OBJECT(chip= ), + &error_abort); + if (!qdev_realize(DEVICE(&chip11->chiptod), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV11_XSCOM_CHIPTOD_BASE, + &chip11->chiptod.xscom_regs); + /* HOMER (must be created before OCC) */ object_property_set_link(OBJECT(&chip11->homer), "chip", OBJECT(chip), &error_abort); diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c index b9e9c7ba3dbb..f887a18cde8d 100644 --- a/hw/ppc/pnv_chiptod.c +++ b/hw/ppc/pnv_chiptod.c @@ -210,6 +210,22 @@ static void chiptod_power10_broadcast_ttype(PnvChipTOD= *sender, } } =20 +static void chiptod_power11_broadcast_ttype(PnvChipTOD *sender, + uint32_t trigger) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv11Chip *chip11 =3D PNV11_CHIP(pnv->chips[i]); + PnvChipTOD *chiptod =3D &chip11->chiptod; + + if (chiptod !=3D sender) { + chiptod_receive_ttype(chiptod, trigger); + } + } +} + static PnvCore *pnv_chip_get_core_by_xscom_base(PnvChip *chip, uint32_t xscom_base) { @@ -283,6 +299,12 @@ static PnvCore *chiptod_power10_tx_ttype_target(PnvChi= pTOD *chiptod, } } =20 +static PnvCore *chiptod_power11_tx_ttype_target(PnvChipTOD *chiptod, + uint64_t val) +{ + return chiptod_power10_tx_ttype_target(chiptod, val); +} + static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { @@ -520,6 +542,42 @@ static const TypeInfo pnv_chiptod_power10_type_info = =3D { } }; =20 +static int pnv_chiptod_power11_dt_xscom(PnvXScomInterface *dev, void *fdt, + int xscom_offset) +{ + const char compat[] =3D "ibm,power-chiptod\0ibm,power11-chiptod"; + + return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(com= pat)); +} + +static void pnv_chiptod_power11_class_init(ObjectClass *klass, const void = *data) +{ + PnvChipTODClass *pctc =3D PNV_CHIPTOD_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); + + dc->desc =3D "PowerNV ChipTOD Controller (Power11)"; + device_class_set_props(dc, pnv_chiptod_properties); + + xdc->dt_xscom =3D pnv_chiptod_power11_dt_xscom; + + pctc->broadcast_ttype =3D chiptod_power11_broadcast_ttype; + pctc->tx_ttype_target =3D chiptod_power11_tx_ttype_target; + + pctc->xscom_size =3D PNV_XSCOM_CHIPTOD_SIZE; +} + +static const TypeInfo pnv_chiptod_power11_type_info =3D { + .name =3D TYPE_PNV11_CHIPTOD, + .parent =3D TYPE_PNV_CHIPTOD, + .instance_size =3D sizeof(PnvChipTOD), + .class_init =3D pnv_chiptod_power11_class_init, + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + static void pnv_chiptod_reset(void *dev) { PnvChipTOD *chiptod =3D PNV_CHIPTOD(dev); @@ -579,6 +637,7 @@ static void pnv_chiptod_register_types(void) type_register_static(&pnv_chiptod_type_info); type_register_static(&pnv_chiptod_power9_type_info); type_register_static(&pnv_chiptod_power10_type_info); + type_register_static(&pnv_chiptod_power11_type_info); } =20 type_init(pnv_chiptod_register_types); diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h index fde569bcbfa9..466b06560a28 100644 --- a/include/hw/ppc/pnv_chiptod.h +++ b/include/hw/ppc/pnv_chiptod.h @@ -17,6 +17,8 @@ OBJECT_DECLARE_TYPE(PnvChipTOD, PnvChipTODClass, PNV_CHIP= TOD) DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV9_CHIPTOD, TYPE_PNV9_CHIPTOD) #define TYPE_PNV10_CHIPTOD TYPE_PNV_CHIPTOD "-POWER10" DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV10_CHIPTOD, TYPE_PNV10_CHIPTOD) +#define TYPE_PNV11_CHIPTOD TYPE_PNV_CHIPTOD "-POWER11" +DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV11_CHIPTOD, TYPE_PNV11_CHIPTOD) =20 enum tod_state { tod_error =3D 0, --=20 2.50.1 From nobody Sat Nov 15 05:23:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654471753124100 As op-build images haven't been updated from long time (and may not get updated in future), use buildroot images provided by cedric [1]. Use existing nvme device being used in the test to mount the initrd. Also replace the check for "zImage loaded message" to skiboot's message when it starts the kernel: "Starting kernel at", since we are no longer using zImage from op-build This is required for newer processor tests such as Power11, as the op-build kernel image is old and doesn't support Power11. Power11 test has been added in a later patch. [1]: https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc= 64le_powernv8-2025.02 Cc: C=C3=A9dric Le Goater Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Suggested-by: C=C3=A9dric Le Goater Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- tests/functional/test_ppc64_powernv.py | 30 ++++++++++++++------------ 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/tests/functional/test_ppc64_powernv.py b/tests/functional/test= _ppc64_powernv.py index 685e2178ed78..2b4db1cf99b4 100755 --- a/tests/functional/test_ppc64_powernv.py +++ b/tests/functional/test_ppc64_powernv.py @@ -18,9 +18,14 @@ class powernvMachine(LinuxKernelTest): good_message =3D 'VFS: Cannot open root device' =20 ASSET_KERNEL =3D Asset( - ('https://archives.fedoraproject.org/pub/archive/fedora-secondary/' - 'releases/29/Everything/ppc64le/os/ppc/ppc64/vmlinuz'), - '383c2f5c23bc0d9d32680c3924d3fd7ee25cc5ef97091ac1aa5e1d853422fc5f') + ('https://github.com/legoater/qemu-ppc-boot/raw/refs/heads/main/' + 'buildroot/qemu_ppc64le_powernv8-2025.02/vmlinux'), + '6fd29aff9ad4362511ea5d0acbb510667c7031928e97d64ec15bbc5daf4b8151') + + ASSET_INITRD =3D Asset( + ('https://github.com/legoater/qemu-ppc-boot/raw/refs/heads/main/' + 'buildroot/qemu_ppc64le_powernv8-2025.02/rootfs.ext2'), + 'aee2192b692077c4bde31cb56ce474424b358f17cec323d5c94af3970c9aada2') =20 def do_test_linux_boot(self, command_line =3D KERNEL_COMMON_COMMAND_LI= NE): self.require_accelerator("tcg") @@ -78,27 +83,24 @@ def test_linux_big_boot(self): wait_for_console_pattern(self, console_pattern, self.panic_message) wait_for_console_pattern(self, self.good_message, self.panic_messa= ge) =20 - - ASSET_EPAPR_KERNEL =3D Asset( - ('https://github.com/open-power/op-build/releases/download/v2.7/' - 'zImage.epapr'), - '0ab237df661727e5392cee97460e8674057a883c5f74381a128fa772588d45cd') - def do_test_ppc64_powernv(self, proc): self.require_accelerator("tcg") - kernel_path =3D self.ASSET_EPAPR_KERNEL.fetch() + kernel_path =3D self.ASSET_KERNEL.fetch() + initrd_path =3D self.ASSET_INITRD.fetch() self.vm.set_console() self.vm.add_args('-kernel', kernel_path, - '-append', 'console=3Dtty0 console=3Dhvc0', + '-drive', + f'file=3D{initrd_path},format=3Draw,if=3Dnone,id= =3Ddrive0,readonly=3Don', + '-append', 'root=3D/dev/nvme0n1 console=3Dtty0 co= nsole=3Dhvc0', '-device', 'pcie-pci-bridge,id=3Dbridge1,bus=3Dpc= ie.1,addr=3D0x0', - '-device', 'nvme,bus=3Dpcie.2,addr=3D0x0,serial= =3D1234', + '-device', 'nvme,drive=3Ddrive0,bus=3Dpcie.2,addr= =3D0x0,serial=3D1234', '-device', 'e1000e,bus=3Dbridge1,addr=3D0x3', '-device', 'nec-usb-xhci,bus=3Dbridge1,addr=3D0x2= ') self.vm.launch() =20 self.wait_for_console_pattern("CPU: " + proc + " generation proces= sor") - self.wait_for_console_pattern("zImage starting: loaded") - self.wait_for_console_pattern("Run /init as init process") + self.wait_for_console_pattern("INIT: Starting kernel at ") + self.wait_for_console_pattern("Run /sbin/init as init process") # Device detection output driven by udev probing is sometimes cut = off # from console output, suspect S14silence-console init script. =20 --=20 2.50.1 From nobody Sat Nov 15 05:23:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1754654533928116600 With all Power11 support in place, add Power11 PowerNV test. Cc: C=C3=A9dric Le Goater Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Aditya Gupta --- tests/functional/test_ppc64_powernv.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/functional/test_ppc64_powernv.py b/tests/functional/test= _ppc64_powernv.py index 2b4db1cf99b4..9ada832b7816 100755 --- a/tests/functional/test_ppc64_powernv.py +++ b/tests/functional/test_ppc64_powernv.py @@ -116,5 +116,9 @@ def test_powernv10(self): self.set_machine('powernv10') self.do_test_ppc64_powernv('P10') =20 + def test_powernv11(self): + self.set_machine('powernv11') + self.do_test_ppc64_powernv('Power11') + if __name__ =3D=3D '__main__': LinuxKernelTest.main() --=20 2.50.1