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([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bd78875cesm9940171b3a.15.2025.08.04.11.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Aug 2025 11:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1754332803; x=1754937603; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c+UBZqDttGYfj8iBFfEmX5S23CgoyF14FdfzJLxCYYE=; b=NZ5E+KjF7uCcMifWTrG1se1FYXpOS/apP7A4CGddapbLVmQcEEKnriktiq3pN7uqIP QlXTAuqzPcHITYUiCm+6WTplKxbsBF7h7L3qFU0ZMU/cRMrlrs7LLaRlP/m3aB0laXYc Op8/Yve7L8iHwQ1V+TmnMexK4mfJYTpPZWtc6AeWMmTHacge/abKodbEx5fImsvI4QBQ jTf7KhBQamYbaeVyPS1UZP+wOqtRenCMGLUyrkyNUAy2V18gT4KGBfD39F2DkDAHDE+/ g2fd3xcI01/ONBj2Necc0MTTVYpRulPXCbdqcHUGrwzJxuqNdVprTns8BVbvDbqbibqb b/Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754332803; x=1754937603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c+UBZqDttGYfj8iBFfEmX5S23CgoyF14FdfzJLxCYYE=; b=gJkc6U3muonyY803jra1P3gvYWyIb35EWwMqaTLeb0wYEx+kOcJ4kz9uKdKp4EdQDK UcuJo3fFRbMSz9OlRz/cGCt+P7489UpDq+vIsC/PnNaXzvhOrNutc577SlKEBJ6DwkZ0 1Y/YNEqzpR5zfW/VNfON6iIDtZZ7TE4CDy2GhDhv4tT8PKmnDoXYBzZdJJ5Am4OOINZz AqccFdhS1L17zij8gYByvqdgwCQjv5n3+u+DLI21DGb8mapSGucC9fMI4KT/P9WmYDEO ihFWvfCNyRECd5oNAY8fUkzxOkYJF6Rp1L9iWPBCHPu1/zxRnNzNbJudJlBinRfCRQBi FeBQ== X-Gm-Message-State: AOJu0YxyZYGzt3xK5dpL8jE4+loKVqy44UOMH6j+5eu1CIZnTAw5zNH/ gqmUItQsHp5tVkLRAMLDtsUee433x3Y1rL1yLeBZLLTaGrKR4tIHRzhQC5P0vPIO68bF6womk9g 0qiiu X-Gm-Gg: ASbGncu6yBDHGmmij9C385uPGotndkrD/7l/WjMDFDOGZDOBvTanFEhThnXXeAkydYi Lkm6gPi3JGBUwxZAe3ZPSfzEi9oY7tkfci8bEJC06jE5pMeZ/lOpedhRdD1zkTh/CRkGeUfGflp gyLFxUxW3XJ+GoqkQTRY7EgxUD2UyLIsZpxN41FPef6nKH7+OX9vmzodOGp0ogcKDjoylDmTe83 xeqgA7+a9LQN6UlWI06zORedXWGSUtIy2Bmt9iiyOaxMLR5Q+ZuloSqZboWTgpZW467GM2KHGN9 U1MvzPCAquAa9sVc6GqY0isWyHBNJRLh+s+LoghuG2IqG3V0mlGwYLwtuZOP0A3xloT7Ghys8+e Elv11aYhMRCClgiN38XgFIvw0XD6OFt4/ X-Google-Smtp-Source: AGHT+IHN31UnwxogKhOBjyr/yOzuKJQLWZsxa9xqp1VJ8C/E2SwAK0SWIuVQjl+MkwdnD/swD0JSEA== X-Received: by 2002:a05:6a00:1254:b0:76b:e109:a1f4 with SMTP id d2e1a72fcca58-76bec4812c8mr13953681b3a.12.1754332803385; Mon, 04 Aug 2025 11:40:03 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, Weiwei Li , Palmer Dabbelt , richard.henderson@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Liu Zhiwei , qemu-arm@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Pierrick Bouvier Subject: [PATCH v3 07/12] include/semihosting/common-semi: extract common_semi API Date: Mon, 4 Aug 2025 11:39:45 -0700 Message-ID: <20250804183950.3147154-8-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250804183950.3147154-1-pierrick.bouvier@linaro.org> References: <20250804183950.3147154-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754336075772124100 Content-Type: text/plain; charset="utf-8" We transform target/{arm,riscv}/common-semi-target.h headers to proper compilation units, and use them in arm-compat-semi.c. This way, we can include only the declaration header (which is target agnostic), and selectively link the appropriate implementation based on current target. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- include/semihosting/common-semi.h | 6 ++++++ semihosting/arm-compat-semi.c | 3 +-- ...mon-semi-target.h =3D> common-semi-target.c} | 20 +++++++++---------- ...mon-semi-target.h =3D> common-semi-target.c} | 19 +++++++++--------- target/arm/meson.build | 4 ++++ target/riscv/meson.build | 4 ++++ 6 files changed, 33 insertions(+), 23 deletions(-) rename target/arm/{common-semi-target.h =3D> common-semi-target.c} (64%) rename target/riscv/{common-semi-target.h =3D> common-semi-target.c} (59%) diff --git a/include/semihosting/common-semi.h b/include/semihosting/common= -semi.h index 0a91db7c414..aa511a46f42 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -35,5 +35,11 @@ #define COMMON_SEMI_H =20 void do_common_semihosting(CPUState *cs); +uint64_t common_semi_arg(CPUState *cs, int argno); +void common_semi_set_ret(CPUState *cs, uint64_t ret); +bool is_64bit_semihosting(CPUArchState *env); +bool common_semi_sys_exit_is_extended(CPUState *cs); +uint64_t common_semi_stack_bottom(CPUState *cs); +bool common_semi_has_synccache(CPUArchState *env); =20 #endif /* COMMON_SEMI_H */ diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 1c593d5e0dc..5877214c47d 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -174,8 +174,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) =20 #endif =20 -#include "cpu.h" -#include "common-semi-target.h" +#include "semihosting/common-semi.h" =20 /* * Read the input value from the argument block; fail the semihosting diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-targe= t.c similarity index 64% rename from target/arm/common-semi-target.h rename to target/arm/common-semi-target.c index 6775a270aaa..2b77ce9c17b 100644 --- a/target/arm/common-semi-target.h +++ b/target/arm/common-semi-target.c @@ -7,12 +7,12 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H -#define TARGET_ARM_COMMON_SEMI_TARGET_H - +#include "qemu/osdep.h" +#include "cpu.h" +#include "semihosting/common-semi.h" #include "target/arm/cpu-qom.h" =20 -static inline uint64_t common_semi_arg(CPUState *cs, int argno) +uint64_t common_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -23,7 +23,7 @@ static inline uint64_t common_semi_arg(CPUState *cs, int = argno) } } =20 -static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +void common_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -34,27 +34,25 @@ static inline void common_semi_set_ret(CPUState *cs, ui= nt64_t ret) } } =20 -static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +bool common_semi_sys_exit_is_extended(CPUState *cs) { return is_a64(cpu_env(cs)); } =20 -static inline bool is_64bit_semihosting(CPUArchState *env) +bool is_64bit_semihosting(CPUArchState *env) { return is_a64(env); } =20 -static inline uint64_t common_semi_stack_bottom(CPUState *cs) +uint64_t common_semi_stack_bottom(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; return is_a64(env) ? env->xregs[31] : env->regs[13]; } =20 -static inline bool common_semi_has_synccache(CPUArchState *env) +bool common_semi_has_synccache(CPUArchState *env) { /* Ok for A64, invalid for A32/T32 */ return is_a64(env); } - -#endif diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-t= arget.c similarity index 59% rename from target/riscv/common-semi-target.h rename to target/riscv/common-semi-target.c index 663dedfdad2..aeaeb88d536 100644 --- a/target/riscv/common-semi-target.h +++ b/target/riscv/common-semi-target.c @@ -8,43 +8,42 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H -#define TARGET_RISCV_COMMON_SEMI_TARGET_H +#include "qemu/osdep.h" +#include "cpu.h" +#include "semihosting/common-semi.h" =20 -static inline uint64_t common_semi_arg(CPUState *cs, int argno) +uint64_t common_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xA0 + argno]; } =20 -static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +void common_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; env->gpr[xA0] =3D ret; } =20 -static inline bool is_64bit_semihosting(CPUArchState *env) +bool is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) !=3D MXL_RV32; } =20 -static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +bool common_semi_sys_exit_is_extended(CPUState *cs) { return is_64bit_semihosting(cpu_env(cs)); } =20 -static inline uint64_t common_semi_stack_bottom(CPUState *cs) +uint64_t common_semi_stack_bottom(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xSP]; } =20 -static inline bool common_semi_has_synccache(CPUArchState *env) +bool common_semi_has_synccache(CPUArchState *env) { return true; } - -#endif diff --git a/target/arm/meson.build b/target/arm/meson.build index 07d9271aa4d..688b50a2e26 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,12 +27,16 @@ arm_user_ss.add(files( 'helper.c', 'vfp_fpscr.c', )) +arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) =20 arm_common_system_ss.add(files('cpu.c')) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) +arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a4bd61e52a9..fdefe88ccdd 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -8,6 +8,10 @@ gen =3D [ =20 riscv_ss =3D ss.source_set() riscv_ss.add(gen) + +riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) + riscv_ss.add(files( 'cpu.c', 'cpu_helper.c', --=20 2.47.2