From nobody Sat Nov 15 07:40:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1754333128; cv=none; d=zohomail.com; s=zohoarc; b=XY02brRnij6UGzow0u6bO+5h9f1pWb9ICaIQUyaLkgeNNuzCQVGoAN4oRDZj3vLcwhtXH9t6SmcJu2dnXO0/UheoGa94uCgEHEngsrMW9ISJYe+TFkszf32kquWf+S1uwat9H+fq9EbHxPYAQBQpYgItg+4Z5Yf2agfafVqBPKg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754333128; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/WTB6euokv3iGCGL6+4F9EN2uhoa05QW/Xcitn/foyU=; b=X0lF5PLQu4ASNdqBXraZIyPpYN3CPVhrlAeSsHJqhTKhW7zecNdLIPqrzWSH1mnagIl7mNQgxblKdddz+wpmCaHuqrmiCg9Rbwp1rfq+As7TxyMzO1H7NkUxJrUr6VjedZGc/jEqHVCptr26d0W8ga0vuj9ijKo8I5TQkG6nSVU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175433312874310.24006824411481; Mon, 4 Aug 2025 11:45:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uj0Ag-0007lD-NB; Mon, 04 Aug 2025 14:44:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uiykD-0006Dt-Sh; Mon, 04 Aug 2025 13:13:07 -0400 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uiykB-0001Zi-Pm; Mon, 04 Aug 2025 13:13:05 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 77A3FA55683; Mon, 4 Aug 2025 17:12:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E12DC4CEF6; Mon, 4 Aug 2025 17:12:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754327573; bh=0S+5l/xpbav3rDV03iq76XUJ/B/q49QMOV/U/YVnmfU=; h=From:To:Cc:Subject:Date:From; b=SdSF2ClM+lkgXaoTwcmrBv1fx2wq9KO8kzadObd5sd5VPqDCth3XBEx4BMDLGv6te 4PlLFwsVsvm+plE8YbvjlszIxLu842IJTvgzwmu+09g5b8VTdzKsT//aqckTuG9SX5 zsY4mafXuypzuMMkFf7FgJA5ciMPUHipshLGoqrUntS0WuXrvFhja1ftwSysCodo3e 6aka5D3vh6JZIITVlHHbSy747YG8W0e08VctMePzKrs5+2BAJf1bFIq7lR+kThCg0s cQK7Vp/rtUyA71pGFxCwdSojUukEq/vLhbGo4yx+Re2IEyzfiusQ0Qpx6U8qj4zLbL 5mdSrlQ5/sGIA== From: guoren@kernel.org To: zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com, alistair.francis@wdc.com, seb@rivosinc.com, tjeznach@rivosinc.com Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, "Guo Ren (Alibaba DAMO Academy)" , qemu-stable@nongnu.org Subject: [PATCH V2] hw/riscv/riscv-iommu: Fixup PDT Nested Walk Date: Mon, 4 Aug 2025 13:12:38 -0400 Message-Id: <20250804171238.354493-1-guoren@kernel.org> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=147.75.193.91; envelope-from=guoren@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1754333130876124100 Content-Type: text/plain; charset="utf-8" From: "Guo Ren (Alibaba DAMO Academy)" Current implementation is wrong when iohgatp !=3D bare. The RISC-V IOMMU specification has defined that the PDT is based on GPA, not SPA. So this patch fixes the problem, making PDT walk correctly when the G-stage table walk is enabled. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Cc: qemu-stable@nongnu.org Cc: Sebastien Boeuf Cc: Tomasz Jeznach Signed-off-by: Guo Ren (Alibaba DAMO Academy) Reviewed-by: Nutty Liu Reviewed-by: Weiwei Li --- Changes in V2: - Remove nested param to make patch clearer. hw/riscv/riscv-iommu.c | 141 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 139 insertions(+), 2 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 96a7fbdefcf3..ded3f7b2fdce 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -866,6 +866,143 @@ static bool riscv_iommu_validate_process_ctx(RISCVIOM= MUState *s, return true; } =20 +/** + * pdt_memory_read: PDT wrapper of dma_memory_read. + * + * @s: IOMMU Device State + * @ctx: Device Translation Context with devid and pasid set + * @addr: address within that address space + * @buf: buffer with the data transferred + * @len: length of the data transferred + * @attrs: memory transaction attributes + */ +static MemTxResult pdt_memory_read(RISCVIOMMUState *s, + RISCVIOMMUContext *ctx, + dma_addr_t addr, + void *buf, dma_addr_t len, + MemTxAttrs attrs) +{ + uint64_t gatp_mode, pte; + struct { + unsigned char step; + unsigned char levels; + unsigned char ptidxbits; + unsigned char ptesize; + } sc; + MemTxResult ret; + dma_addr_t base =3D addr; + + /* G stages translation mode */ + gatp_mode =3D get_field(ctx->gatp, RISCV_IOMMU_ATP_MODE_FIELD); + if (gatp_mode =3D=3D RISCV_IOMMU_DC_IOHGATP_MODE_BARE) + goto out; + + /* G stages translation tables root pointer */ + base =3D PPN_PHYS(get_field(ctx->gatp, RISCV_IOMMU_ATP_PPN_FIELD)); + + /* Start at step 0 */ + sc.step =3D 0; + + if (s->fctl & RISCV_IOMMU_FCTL_GXL) { + /* 32bit mode for GXL =3D=3D 1 */ + switch (gatp_mode) { + case RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4: + if (!(s->cap & RISCV_IOMMU_CAP_SV32X4)) { + return MEMTX_ACCESS_ERROR; + } + sc.levels =3D 2; + sc.ptidxbits =3D 10; + sc.ptesize =3D 4; + break; + default: + return MEMTX_ACCESS_ERROR; + } + } else { + /* 64bit mode for GXL =3D=3D 0 */ + switch (gatp_mode) { + case RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: + if (!(s->cap & RISCV_IOMMU_CAP_SV39X4)) { + return MEMTX_ACCESS_ERROR; + } + sc.levels =3D 3; + sc.ptidxbits =3D 9; + sc.ptesize =3D 8; + break; + case RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: + if (!(s->cap & RISCV_IOMMU_CAP_SV48X4)) { + return MEMTX_ACCESS_ERROR; + } + sc.levels =3D 4; + sc.ptidxbits =3D 9; + sc.ptesize =3D 8; + break; + case RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: + if (!(s->cap & RISCV_IOMMU_CAP_SV57X4)) { + return MEMTX_ACCESS_ERROR; + } + sc.levels =3D 5; + sc.ptidxbits =3D 9; + sc.ptesize =3D 8; + break; + default: + return MEMTX_ACCESS_ERROR; + } + } + + do { + const unsigned va_bits =3D (sc.step ? 0 : 2) + sc.ptidxbits; + const unsigned va_skip =3D TARGET_PAGE_BITS + sc.ptidxbits * + (sc.levels - 1 - sc.step); + const unsigned idx =3D (addr >> va_skip) & ((1 << va_bits) - 1); + const dma_addr_t pte_addr =3D base + idx * sc.ptesize; + + /* Address range check before first level lookup */ + if (!sc.step) { + const uint64_t va_mask =3D (1ULL << (va_skip + va_bits)) - 1; + if ((addr & va_mask) !=3D addr) { + return MEMTX_ACCESS_ERROR; + } + } + + /* Read page table entry */ + if (sc.ptesize =3D=3D 4) { + uint32_t pte32 =3D 0; + ret =3D ldl_le_dma(s->target_as, pte_addr, &pte32, attrs); + pte =3D pte32; + } else { + ret =3D ldq_le_dma(s->target_as, pte_addr, &pte, attrs); + } + if (ret !=3D MEMTX_OK) + return ret; + + sc.step++; + hwaddr ppn =3D pte >> PTE_PPN_SHIFT; + + if (!(pte & PTE_V)) { + return MEMTX_ACCESS_ERROR; /* Invalid PTE */ + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { + return MEMTX_ACCESS_ERROR; /* Reserved leaf PTE flags: PTE_W */ + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X))= { + return MEMTX_ACCESS_ERROR; /* Reserved leaf PTE flags: PTE_W += PTE_X */ + } else if (ppn & ((1ULL << (va_skip - TARGET_PAGE_BITS)) - 1)) { + return MEMTX_ACCESS_ERROR; /* Misaligned PPN */ + } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { + base =3D PPN_PHYS(ppn); /* Inner PTE, continue walking */ + } else { + /* Leaf PTE, translation completed. */ + base =3D PPN_PHYS(ppn) | (addr & ((1ULL << va_skip) - 1)); + break; + } + + if (sc.step =3D=3D sc.levels) { + return MEMTX_ACCESS_ERROR; /* Can't find leaf PTE */ + } + } while (1); + +out: + return dma_memory_read(s->target_as, base, buf, len, attrs); +} + /* * RISC-V IOMMU Device Context Loopkup - Device Directory Tree Walk * @@ -1038,7 +1175,7 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, = RISCVIOMMUContext *ctx) */ const int split =3D depth * 9 + 8; addr |=3D ((ctx->process_id >> split) << 3) & ~TARGET_PAGE_MASK; - if (dma_memory_read(s->target_as, addr, &de, sizeof(de), + if (pdt_memory_read(s, ctx, addr, &de, sizeof(de), MEMTXATTRS_UNSPECIFIED) !=3D MEMTX_OK) { return RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT; } @@ -1053,7 +1190,7 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, = RISCVIOMMUContext *ctx) =20 /* Leaf entry in PDT */ addr |=3D (ctx->process_id << 4) & ~TARGET_PAGE_MASK; - if (dma_memory_read(s->target_as, addr, &dc.ta, sizeof(uint64_t) * 2, + if (pdt_memory_read(s, ctx, addr, &dc.ta, sizeof(uint64_t) * 2, MEMTXATTRS_UNSPECIFIED) !=3D MEMTX_OK) { return RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT; } --=20 2.40.1