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Sat, 02 Aug 2025 16:38:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 64/85] target/arm: Implement GCSSS1 Date: Sun, 3 Aug 2025 09:29:32 +1000 Message-ID: <20250802232953.413294-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250802232953.413294-1-richard.henderson@linaro.org> References: <20250802232953.413294-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754180083566124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 3 +++ target/arm/tcg/translate-a64.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 392a0a264f..ee8b870e17 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -52,6 +52,7 @@ enum { ARM_CP_GCSPUSHX =3D 0x000a, ARM_CP_GCSPOPX =3D 0x000b, ARM_CP_GCSPOPCX =3D 0x000c, + ARM_CP_GCSSS1 =3D 0x000d, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index ab53a4314f..bdafc60786 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -114,6 +114,9 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSPOPM", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 1, .access =3D PL0_R, .type =3D ARM_CP_GCSPOPM }, + { .name =3D "GCSSS1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 2, + .access =3D PL0_W, .type =3D ARM_CP_GCSSS1 }, { .name =3D "GCSPUSHX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 4, .access =3D PL1_W, .accessfn =3D access_gcspushx, .fgt =3D FGT_NGCSE= PP, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index af91b7f95f..e4c7801740 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2634,6 +2634,33 @@ static void gen_gcspopx(DisasContext *s) tcg_gen_st_i64(addr, tcg_env, sp_off); } =20 +static void gen_gcsss1(DisasContext *s, int rt) +{ + int sp_off =3D offsetof(CPUARMState, cp15.gcspr_el[s->current_el]); + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 inptr =3D cpu_reg(s, rt); + TCGv_i64 cmp =3D tcg_temp_new_i64(); + TCGv_i64 new =3D tcg_temp_new_i64(); + TCGv_i64 old =3D tcg_temp_new_i64(); + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSSS1, rt= )); + + /* Compute the valid cap entry that the new stack must have. */ + tcg_gen_ld_i64(new, tcg_env, sp_off); + tcg_gen_deposit_i64(cmp, inptr, tcg_constant_i64(1), 0, 12); + /* Compute the in-progress cap entry for the old stack. */ + tcg_gen_deposit_i64(new, new, tcg_constant_i64(5), 0, 3); + + /* Swap the valid cap the with the in-progress cap. */ + tcg_gen_atomic_cmpxchg_i64(old, inptr, cmp, new, mmuidx, mop); + tcg_gen_brcond_i64(TCG_COND_NE, old, cmp, fail_label); + + /* The new stack had a valid cap: change gcspr. */ + tcg_gen_andi_i64(new, inptr, ~7); + tcg_gen_st_i64(new, tcg_env, sp_off); +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2945,6 +2972,11 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcspopx(s); } return; + case ARM_CP_GCSSS1: + if (s->gcs_en) { + gen_gcsss1(s, rt); + } + return; default: g_assert_not_reached(); } --=20 2.43.0