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([172.58.111.133]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-741a71dc78asm380409a34.30.2025.08.02.16.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Aug 2025 16:36:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1754177808; x=1754782608; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pPOkQLbvkqPVPEJfSSp8FNRSZcEhCTwT9zh6ylUUUcE=; b=mKTmhvD2i3axDnt3++MlgTaY1iyD93I8zDBvzxov26ZgzILwFwDIg5aDm4MbJGiOil GFn6V+lCbMCR3IdlWVRsdztfLDfJCbjMG3nw6zYgFc8uC+9so8X4TjplCYobrS4wlYKh He3ezYWduafAZg0MhzsRPuEaTFTV8oC8P6Gw9WFItM9ZHGHS26MfB/7QHvMWfNr9NtHD xkH0LkU+0KuOYEPKqukeACTUGsy6DIpnGeeVjTBqtI+wmiY0JOQbQVZQX51rS0q+yG52 W6wSC8mRoPjU4wCddJjdGfE4yiEd45BaF2H0VxbX0xIpCB+YQGOF2sAhvGzngAKzgs/m iHWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754177808; x=1754782608; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pPOkQLbvkqPVPEJfSSp8FNRSZcEhCTwT9zh6ylUUUcE=; b=opQyxZs09jSaUPJylAk8XVceEDZAn8J0oljeR2UjkVtxjM7BMwg40lHWFzqBUovype 52nIuFqVKoZyU8pSlgJLrG3KTNyXMqA20c+5bZ7N/DLkTPgL4gJtD0CvsyLz0Ex2VEw2 k44N0XkRGS9GY3OpZXf77aqbbfFZzNfD72aS1L8X1nk+0vfic2RvJ887ao/HJLeBLr3w pWyJwJ+BpnDjdqVryKOcRRpcn2NX+P1CP3JJNg/zZM5vdF2MsLC09Mb8Kw6wqLzEcYgc /4Xd0WYNrnYJvHzfgFWjLVRDscRVKdJ67AspH0EDVi/x+PmVnZ9ySxo2BuYFzizaYEOJ KexA== X-Gm-Message-State: AOJu0YyIYGB7UMIuupgg3CWmbAW2KayaganH4+XDVyYT/7InONkbVhKH vYYUfWHWNexbi7aiLr3+GHK8sBVs6vWNvI54iM9l4pmSezs5h/7/BjBNmNMWoUrw3mYzrOr8Ao1 hQS7XiVs= X-Gm-Gg: ASbGncsEFo0YLrH9lerMJpY605jcIPcTr/vXhYLl/CnGuVJRucowX983Rm/EuOfJCGB MdACdGROr84ohfJdp/6c8Mw7KZWrYou7SpJILYmHWIEHxoVK98gYjjjjcrvOPprkolZ6wreSiO9 By8WftBooFTgSz0SZBf69grRFnltIfNgn1KS1RFYqi5iLEbt/Rjxp/LYFWACvSLaa0CLnPpY3MC pzRBJ3ypWnULufkVrhr8DP9igKuzX/Vxg6OHS4QICgm6TXc/aN4IYN0GymtHqg30ayMsXbQFZgr yToqvhQvKLbVZcV+U0T0/TkGJo1rbw1ehoBrZav4BoPrfUHBAMGuNEtMnMmOyGOykrlfUNIrhew 7zrTxwNooyzF9iS1G2wRvgjjnROJi1ItvX0UA7Y4Wq8+9+KHqZV9pcCDab0pM1U0= X-Google-Smtp-Source: AGHT+IHG1ISxY0xlxMUVz+SdWzgFLkkxUCfeT1YpjCd72I1UHDfLz+A6e3SBm4UTqm2z0u47fh5jpg== X-Received: by 2002:a05:6830:927:b0:73c:e29c:3fdc with SMTP id 46e09a7af769-7419d27d146mr2249149a34.18.1754177808001; Sat, 02 Aug 2025 16:36:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 47/85] target/arm: Add GCS cpregs Date: Sun, 3 Aug 2025 09:29:15 +1000 Message-ID: <20250802232953.413294-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250802232953.413294-1-richard.henderson@linaro.org> References: <20250802232953.413294-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754178668536116600 Content-Type: text/plain; charset="utf-8" Add isar_feature_aa64_gcs. Enable SCR_GCSEN in scr_write. Enable HCRX_GCSEN in hcrx_write. Default HCRX_GCSEN on if EL2 disabled. Add the GCSCR* and GCSPR* registers. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 2 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 12 ++++++ target/arm/internals.h | 3 ++ target/arm/cpregs-gcs.c | 79 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 3 ++ target/arm/helper.c | 10 +++++ target/arm/meson.build | 2 + 8 files changed, 116 insertions(+) create mode 100644 target/arm/cpregs-gcs.c diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 9efe9238c1..bc6adf5956 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -774,6 +774,8 @@ typedef enum FGTBit { DO_BIT(HFGRTR, VBAR_EL1), DO_BIT(HFGRTR, ICC_IGRPENN_EL1), DO_BIT(HFGRTR, ERRIDR_EL1), + DO_REV_BIT(HFGRTR, NGCS_EL0), + DO_REV_BIT(HFGRTR, NGCS_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), DO_REV_BIT(HFGRTR, NPIRE0_EL1), diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 83875c06bb..e3754df786 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -719,6 +719,11 @@ static inline bool isar_feature_aa64_nmi(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) !=3D 0; } =20 +static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index da42bd4466..1da73196f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -591,6 +591,9 @@ typedef struct CPUArchState { uint64_t mecid_rl_a_el3; uint64_t vmecid_p_el2; uint64_t vmecid_a_el2; + + uint64_t gcscr_el[4]; /* GCSCRE0_EL1, GCSCR_EL[123] */ + uint64_t gcspr_el[4]; /* GCSPR_EL[0123] */ } cp15; =20 struct { @@ -1735,6 +1738,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_ENAS0 (1ULL << 36) #define SCR_ADEN (1ULL << 37) #define SCR_HXEN (1ULL << 38) +#define SCR_GCSEN (1ULL << 39) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_TCR2EN (1ULL << 43) @@ -1744,6 +1748,14 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 +/* GCSCR_ELx fields */ +#define GCSCR_PCRSEL (1ULL << 0) +#define GCSCR_RVCHKEN (1ULL << 5) +#define GCSCR_EXLOCKEN (1ULL << 6) +#define GCSCR_PUSHMEN (1ULL << 8) +#define GCSCR_STREN (1ULL << 9) +#define GCSCRE0_NTR (1ULL << 10) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target/arm/internals.h b/target/arm/internals.h index 7a42f8be0b..350b8bc678 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -253,6 +253,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_MSCEN (1ULL << 11) #define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) +#define HCRX_GCSEN (1ULL << 22) =20 #define HPFAR_NS (1ULL << 63) =20 @@ -1778,6 +1779,8 @@ void define_tlb_insn_regs(ARMCPU *cpu); void define_at_insn_regs(ARMCPU *cpu); /* Add the cpreg definitions for PM cpregs */ void define_pm_cpregs(ARMCPU *cpu); +/* Add the cpreg definitions for GCS cpregs */ +void define_gcs_cpregs(ARMCPU *cpu); =20 /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c new file mode 100644 index 0000000000..9c06100d2b --- /dev/null +++ b/target/arm/cpregs-gcs.c @@ -0,0 +1,79 @@ +/* + * QEMU ARM CP Register GCS regiters and instructions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "exec/icount.h" +#include "hw/irq.h" +#include "cpu.h" +#include "cpu-features.h" +#include "cpregs.h" +#include "internals.h" + + +static CPAccessResult access_gcs(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_GCSEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_gcs_el0(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.gcscr_el[0] & GCSCRE0_= NTR)) { + return CP_ACCESS_TRAP_EL1; + } + return access_gcs(env, ri, isread); +} + +static const ARMCPRegInfo gcs_reginfo[] =3D { + { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL0, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[0]) }, + { .name =3D "GCSCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL1, + .nv2_redirect_offset =3D 0x8d0 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[1]) }, + { .name =3D "GCSCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_gcs, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[2]) }, + { .name =3D "GCSCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[3]) }, + + { .name =3D "GCSPR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL0_R | PL1_W, .accessfn =3D access_gcs_el0, .fgt =3D FG= T_NGCS_EL0, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[0]) }, + { .name =3D "GCSPR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL1, + .nv2_redirect_offset =3D 0x8c0 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[1]) }, + { .name =3D "GCSPR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_gcs, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, + { .name =3D "GCSPR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, +}; + +void define_gcs_cpregs(ARMCPU *cpu) +{ + if (cpu_isar_feature(aa64_gcs, cpu)) { + define_arm_cp_regs(cpu, gcs_reginfo); + } +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b472992b4a..d9318c5325 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -644,6 +644,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + env->cp15.scr_el3 |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { env->cp15.scr_el3 |=3D SCR_TCR2EN; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 1b21ae5d8e..14f7129607 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -743,6 +743,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { valid_mask |=3D SCR_TCR2EN; } @@ -3947,6 +3950,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPR= egInfo *ri, if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D HCRX_GCSEN; + } =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; @@ -4017,6 +4023,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) if (cpu_isar_feature(aa64_sctlr2, cpu)) { hcrx |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + hcrx |=3D HCRX_GCSEN; + } return hcrx; } if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXE= N)) { @@ -7574,6 +7583,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 define_pm_cpregs(cpu); + define_gcs_cpregs(cpu); =20 #ifndef CONFIG_USER_ONLY /* diff --git a/target/arm/meson.build b/target/arm/meson.build index 91630a1f72..8c82304fde 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,6 +27,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c', )) arm_user_ss.add(files( + 'cpregs-gcs.c', 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', @@ -42,6 +43,7 @@ arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'cortex-regs.c', + 'cpregs-gcs.c', 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', --=20 2.43.0