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Sat, 02 Aug 2025 16:32:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 34/85] target/arm: Remove unused env argument from regime_el Date: Sun, 3 Aug 2025 09:29:02 +1000 Message-ID: <20250802232953.413294-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250802232953.413294-1-richard.henderson@linaro.org> References: <20250802232953.413294-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754178233081116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 8 ++++---- target/arm/helper.c | 2 +- target/arm/ptw.c | 34 +++++++++++++++++----------------- target/arm/tcg/mte_helper.c | 2 +- 4 files changed, 23 insertions(+), 23 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2dc82330ec..4991d6ab7f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1076,7 +1076,7 @@ static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) } =20 /* Return the exception level which controls this address translation regi= me */ -static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline uint32_t regime_el(ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_E20_0: @@ -1130,7 +1130,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) /* Return the SCTLR value which controls this address translation regime */ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { - return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; + return env->cp15.sctlr_el[regime_el(mmu_idx)]; } =20 /* @@ -1162,13 +1162,13 @@ static inline uint64_t regime_tcr(CPUARMState *env,= ARMMMUIdx mmu_idx) v |=3D env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; return v; } - return env->cp15.tcr_el[regime_el(env, mmu_idx)]; + return env->cp15.tcr_el[regime_el(mmu_idx)]; } =20 /* Return true if the translation regime is using LPAE format page tables = */ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mm= u_idx) { - int el =3D regime_el(env, mmu_idx); + int el =3D regime_el(mmu_idx); if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { return true; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 8985ad8c8a..78f670314d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9633,7 +9633,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); bool stage2 =3D regime_is_stage2(mmu_idx); - int r_el =3D regime_el(env, mmu_idx); + int r_el =3D regime_el(mmu_idx); =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 820d5e65a0..30c83334b6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -232,9 +232,9 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx= mmu_idx, int ttbrn) return env->cp15.vsttbr_el2; } if (ttbrn =3D=3D 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + return env->cp15.ttbr0_el[regime_el(mmu_idx)]; } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + return env->cp15.ttbr1_el[regime_el(mmu_idx)]; } } =20 @@ -1023,7 +1023,7 @@ static bool get_phys_addr_v5(CPUARMState *env, S1Tran= slate *ptw, } type =3D (desc & 3); domain =3D (desc >> 5) & 0x0f; - if (regime_el(env, ptw->in_mmu_idx) =3D=3D 1) { + if (regime_el(ptw->in_mmu_idx) =3D=3D 1) { dacr =3D env->cp15.dacr_ns; } else { dacr =3D env->cp15.dacr_s; @@ -1163,7 +1163,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Tran= slate *ptw, /* Page or Section. */ domain =3D (desc >> 5) & 0x0f; } - if (regime_el(env, mmu_idx) =3D=3D 1) { + if (regime_el(mmu_idx) =3D=3D 1) { dacr =3D env->cp15.dacr_ns; } else { dacr =3D env->cp15.dacr_s; @@ -1454,7 +1454,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, xn =3D pxn || (user_rw & PAGE_WRITE); } } else if (arm_feature(env, ARM_FEATURE_V7)) { - switch (regime_el(env, mmu_idx)) { + switch (regime_el(mmu_idx)) { case 1: case 3: if (is_user) { @@ -1510,7 +1510,7 @@ static int get_S1prot_indirect(CPUARMState *env, S1Tr= anslate *ptw, /* F */ 0, /* reserved */ }; =20 - uint32_t el =3D regime_el(env, mmu_idx); + uint32_t el =3D regime_el(mmu_idx); uint64_t pir =3D env->cp15.pir_el[el]; uint64_t pire0 =3D 0; int perm; @@ -1585,7 +1585,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState= *env, uint32_t va, ARMMMUIdx mmu_idx) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - uint32_t el =3D regime_el(env, mmu_idx); + uint32_t el =3D regime_el(mmu_idx); int select, tsz; bool epd, hpd; =20 @@ -1811,7 +1811,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); int ap, prot; - uint32_t el =3D regime_el(env, mmu_idx); + uint32_t el =3D regime_el(mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; @@ -2259,7 +2259,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); - mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + mair =3D env->cp15.mair_el[regime_el(mmu_idx)]; assert(attrindx <=3D 7); result->cacheattrs.is_s2_format =3D false; result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); @@ -2737,7 +2737,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t secure) { - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { return env->pmsav8.hprbar; } else { return env->pmsav8.rbar[secure]; @@ -2747,7 +2747,7 @@ static uint32_t *regime_rbar(CPUARMState *env, ARMMMU= Idx mmu_idx, static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t secure) { - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { return env->pmsav8.hprlar; } else { return env->pmsav8.rlar[secure]; @@ -2779,7 +2779,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); int region_counter; =20 - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { region_counter =3D cpu->pmsav8r_hdregion; } else { region_counter =3D cpu->pmsav7_dregion; @@ -2905,7 +2905,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 1; } =20 - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { result->f.prot =3D simple_ap_to_rw_prot_is_user(ap, mmu_idx !=3D ARMMMUIdx_E2); } else { @@ -2914,7 +2914,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 if (!arm_feature(env, ARM_FEATURE_M)) { uint8_t attrindx =3D extract32(matched_rlar, 1, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + uint64_t mair =3D env->cp15.mair_el[regime_el(mmu_idx)]; uint8_t sh =3D extract32(matched_rlar, 3, 2); =20 if (regime_sctlr(env, mmu_idx) & SCTLR_WXN && @@ -2922,7 +2922,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 0x1; } =20 - if ((regime_el(env, mmu_idx) =3D=3D 1) && + if ((regime_el(mmu_idx) =3D=3D 1) && regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap =3D=3D 0x1) { pxn =3D 0x1; } @@ -3407,7 +3407,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, break; =20 default: - r_el =3D regime_el(env, mmu_idx); + r_el =3D regime_el(mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); uint64_t tcr =3D env->cp15.tcr_el[r_el]; @@ -3659,7 +3659,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, */ if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 && !arm_feature(env, ARM_FEATURE_V8)) { - if (regime_el(env, mmu_idx) =3D=3D 3) { + if (regime_el(mmu_idx) =3D=3D 3) { address +=3D env->cp15.fcseidr_s; } else { address +=3D env->cp15.fcseidr_ns; diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 0efc18a181..ed30026b7d 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -604,7 +604,7 @@ void mte_check_fail(CPUARMState *env, uint32_t desc, int el, reg_el, tcf; uint64_t sctlr; =20 - reg_el =3D regime_el(env, arm_mmu_idx); + reg_el =3D regime_el(arm_mmu_idx); sctlr =3D env->cp15.sctlr_el[reg_el]; =20 switch (arm_mmu_idx) { --=20 2.43.0