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([172.58.111.133]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-30b8e3c9b32sm71031fac.24.2025.08.02.16.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Aug 2025 16:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1754177517; x=1754782317; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TtfdJAKHkhBXVVur9KnTeJdEj0NKkUPLOFyccsCQyeU=; b=ja5tKzs6yXhp3ae36h5mQaZxwfZZJEfoxY1ZsAiosr0FKRKaFf6ZulY97coYxv6nN+ jYmaeoVulsbej6EqlD/o2by0sE7oeUKXAWOmPaWsWo3SCWl0/47svLjTtab6xdEHZo+l 8I08MGjnQUuXldGFQ7YH01UuL10tVWZQC8d/JKGqaJZMGNnnpwP4KYUj/aZQf9NlE1xf Otuit4h316JqEmGxIJ7bb/OeAOrOIJj2eB5ZPKQdpJDyYGX6bz2RTriJ/FtMc56yWN60 wZmM2DcxoKV2I7cIwwFV+bmkHYOkJ+fplAXGwAbem0jOHwy62sYQjwjuUruga0VK/JeH DYmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754177517; x=1754782317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TtfdJAKHkhBXVVur9KnTeJdEj0NKkUPLOFyccsCQyeU=; b=w0A74bNyjnUJczKj+Hjb4J50TaJnDt+iQUg9aM70HK1CXTBI55x/hvzN2kx9XO0BcI AvrYhRprcCWUl2mywSlrZFV6jwsVQusrBEnPR+f8IdFB5+8Wz/9l9Uj0goKdowQc9sQ3 KXauaRfO3bsnMivOe/WVUXN9PHnp1kc1n8Esfo/4LX/w/tUpyHV6BJ9P7opWF6vP0n1j iCH8dLPC1YI3RDFAcjbX71Zrny6YX4ODUWykw4xEQ7ebTHmlQtFRb+f1F8kU3xhbzVY4 aSIfGvAyskuwr6k9AjRNEBmu5p5jBdQ8Tsjq+YTWhIeT/rOn4lD7C7+Qu78iKr6mM2qT IklQ== X-Gm-Message-State: AOJu0Yyh06ablgIInl4Zv1CSCaE+uvQ05Hkgz6vNAcmhX84PnKchRUcx 4cpLVbVWVsqQvl3PXmfZM7rJ3JSZIlKWnXqHnHlsWMoH0TZ0uQpHpF2+1kpwOaz42zywlXcc2M8 GpMxzH6w= X-Gm-Gg: ASbGncsCAcuXTO4UNybrrFQHkluwWiQWrr3M9DZyUnVf4hXOtIAh+Np46xYJKDiT9/e vtS3UL0Ze/GxRBKmg6/KN2JVCVwSyWHd5NfVaWFhvJIeTzOYiocr9vmZyf3m8RyCWXTFINrIzrt 4Eex2VrkUtqIPx089qlA8UXx80ERurbSZ6H6QJ7PzNcfKjf/hbpXWbTydGLf3WN6UARALc+GUOH u2nJjRwwQqgly/NipCh3LuAEUgPtpYSXk7jluwc3MWJZjk/kgKwuzOmoHm+hs7/PjLF3T5ZumW/ bvbWb2DcoJN67XG6COtnls7JdutrJ9JuZrbE78j0znH34ttnu+02LZlEnWP7rFlL0nryYowcFfA oJKyxwYZngpZGDJ0kaElISx/aIGwYQYyTw8g+c+mOjZn1R1Hpm5Ka X-Google-Smtp-Source: AGHT+IGazccfX3NI/VYEnzo4AbEkGmch1ZTBvtJ6fLmfxKA3gMvnFQLPP+p/a9QEWaUbsXUWnGziEg== X-Received: by 2002:a05:6870:a44a:b0:2eb:9fe5:d06c with SMTP id 586e51a60fabf-30b6685b897mr2728877fac.3.1754177516873; Sat, 02 Aug 2025 16:31:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 24/85] target/arm: Implement dirtybit check for PIE Date: Sun, 3 Aug 2025 09:28:52 +1000 Message-ID: <20250802232953.413294-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250802232953.413294-1-richard.henderson@linaro.org> References: <20250802232953.413294-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754178680139124100 Content-Type: text/plain; charset="utf-8" Both S1PIE and S2PIE have a bit to make software tracking of dirty pages easier. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/ptw.c | 16 ++++++++++++++++ target/arm/tcg/tlb_helper.c | 12 +++++++++--- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fc82dd65e8..b6499683cc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -754,6 +754,7 @@ struct ARMMMUFaultInfo { bool s1ptw; bool s1ns; bool ea; + bool dirtybit; /* FEAT_S1PIE, FEAT_S2PIE */ }; =20 /** diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 323fc8052d..820d5e65a0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2306,6 +2306,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, goto do_fault; } =20 + /* S1PIE and S2PIE both have a bit for software dirty page tracking. */ + if (access_type =3D=3D MMU_DATA_STORE && param.pie) { + /* + * For S1PIE, bit 7 is nDirty and both HA and HD are checked. + * For S2PIE, bit 7 is Dirty and only HD is checked. + */ + bool bit7 =3D extract64(attrs, 7, 1); + if (regime_is_stage2(mmu_idx) + ? !bit7 && !param.hd + : bit7 && !(param.ha && param.hd)) { + fi->type =3D ARMFault_Permission; + fi->dirtybit =3D true; + goto do_fault; + } + } + /* If FEAT_HAFDBS has made changes, update the PTE. */ if (new_descriptor !=3D descriptor) { new_descriptor =3D arm_casq_ptw(env, descriptor, new_descriptor, p= tw, fi); diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 23c72a99f5..ae2acd6727 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -24,13 +24,13 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, = ARMMMUIdx mmu_idx) return regime_using_lpae_format(env, mmu_idx); } =20 -static inline uint32_t merge_syn_data_abort(uint32_t template_syn, +static inline uint64_t merge_syn_data_abort(uint32_t template_syn, ARMMMUFaultInfo *fi, unsigned int target_el, bool same_el, bool is_write, int fsc) { - uint32_t syn; + uint64_t syn; =20 /* * ISV is only set for stage-2 data aborts routed to EL2 and @@ -75,6 +75,10 @@ static inline uint32_t merge_syn_data_abort(uint32_t tem= plate_syn, /* Merge the runtime syndrome with the template syndrome. */ syn |=3D template_syn; } + + /* Form ISS2 at the top of the syndrome. */ + syn |=3D (uint64_t)fi->dirtybit << 37; + return syn; } =20 @@ -176,7 +180,9 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, int target_el =3D exception_target_el(env); int current_el =3D arm_current_el(env); bool same_el; - uint32_t syn, exc, fsr, fsc; + uint32_t exc, fsr, fsc; + uint64_t syn; + /* * We know this must be a data or insn abort, and that * env->exception.syndrome contains the template syndrome set --=20 2.43.0