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([172.58.111.133]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-61970693b48sm1093401eaf.19.2025.08.02.16.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Aug 2025 16:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1754175944; x=1754780744; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v2SfyAZc4XoY8CMkOgazi0gSdP78GuSA69fV6HrxMHw=; b=Z1KTQCOKDBKZwZUhUkQqSed41+Ad/FLrtut0UgAIJgrukZ+CdhoWSDbt1rIwYV+9iK Z5cGf0O8d7AZOQILao5eJkNTXShDQY/+ysVXWLeB+lh3d5XO8T4CiO4ujyXg45qfaAnz ag6H1FBxJEkEA9cBZ6KMWNBJnUaQnC8ChiML6eMkZjZVsTxaVpJppXprnD+gCYIx6wLe c2T4+JPIEo7l4VILR4Qafchl5pi//XlKrDHBIWV7XIzzvCG+srDWC+csv82pP/y6Vs23 A4r2v6Mhl0iJ6eBORpIxlmuG3RtUOJkbJYbpunMI7h+Lfnn4kYENbxXt8VdMjPN55qXr 5VUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754175944; x=1754780744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v2SfyAZc4XoY8CMkOgazi0gSdP78GuSA69fV6HrxMHw=; b=cvSA1vkDWSEoQwiRM87EFOrbzsGzeBodnCfCDfWsWJ7jSpALSXRo6w880P7YUgN5Gv ATpqTkSyMFh6Ltsjjz5KWLq+FwgneNA0iwsbe3Gg4feFDEkQcB636y81c2nMjDRHlmB3 8Agqa3/NI8Ua+C3NOowp/2GB7apj9+e7CJOgfSidWqlBAviaLMHjvo0tLX6XJKdRDmSS BP1ayAyKvYg07eq1MwsrogdhaKj5heLOZaVOXElWs/lXFmmY35sfydiXWURcdBB7jI7s iVO4QmTwkUw2wWJiFvuTTaWfxOXoVJ4QVB/HcvLKFFKtVuD2j2C7D2VJyxFn6rTalTTI OO4A== X-Gm-Message-State: AOJu0YxMZGpD6Bl0iEMa3OzJTVNnHAZQIKzwEKzEnlunZUS+YnJoAqZr fdYeNjV05p6PwKYyDPvkIwdep4cRoxcyElsyWhc0K76PgeO/0lN1hAX6HgvO5jUZ9mh5QPpMNuO TaZq1A9o= X-Gm-Gg: ASbGncvbdMGeq7z5K11AktTXbLUINGnLEvIl5tzxBpI2E2K+zGVHkbdSgWi5X8ioE8T Oz1CvrjasQQOJG4HSnGcZ6o34WRzCJsSjSn1DVgYGGYPbisiPMKpvOd+6QWsJTzJ6HJo2O0tZYN wu5jviYyI2Xt8HmGc1Q3DrQLQidKxqrIB8rSJXBTQ2Njw8MwFbEpvwc9ymLxKbQ8exbDgRPkH5k m0Z0N8bJEowmPTz8eo4RmMKbdO/5Dtbzc9g9uDKVML96n7Zw5+47Cws74Xr/st6t8lLI8Y0KJog J14udKLaS/DPsHbqlMIjGVIQsrDRmdz3A1D6Xr74X+Gb6C3FS7eoXRAikWyPJozwt7t6K8gP6Pe CxsZ3O2sdDdR5duBZW72k+D99QO07cStQRrXTF7BOoITI4qB9/B3+Vuxin0GMcS8= X-Google-Smtp-Source: AGHT+IGYCHMlcdLpCIHU7YtXdLVfGzhZp/DY2K8Jqadpygd1hJJU1AUuOJPxa5RHtVR8vO3eo3A7Rg== X-Received: by 2002:a05:6820:3093:b0:619:a34b:3e32 with SMTP id 006d021491bc7-619a34b4375mr797315eaf.0.1754175943768; Sat, 02 Aug 2025 16:05:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PATCH v2 09/95] linux-user: Move hwcap functions to ppc/elfload.c Date: Sun, 3 Aug 2025 09:03:33 +1000 Message-ID: <20250802230459.412251-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250802230459.412251-1-richard.henderson@linaro.org> References: <20250802230459.412251-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754176700788116600 Content-Type: text/plain; charset="utf-8" Change the return type to abi_ulong, and pass in the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/loader.h | 2 +- linux-user/ppc/target_elf.h | 3 + linux-user/elfload.c | 116 +----------------------------------- linux-user/ppc/elfload.c | 116 ++++++++++++++++++++++++++++++++++++ 4 files changed, 122 insertions(+), 115 deletions(-) diff --git a/linux-user/loader.h b/linux-user/loader.h index 2c8414e0e5..818c5e6d7d 100644 --- a/linux-user/loader.h +++ b/linux-user/loader.h @@ -102,7 +102,7 @@ extern unsigned long guest_stack_size; const char *get_elf_cpu_model(uint32_t eflags); =20 #if defined(TARGET_I386) || defined(TARGET_X86_64) || defined(TARGET_ARM) \ - || defined(TARGET_SPARC) + || defined(TARGET_SPARC) || defined(TARGET_PPC) abi_ulong get_elf_hwcap(CPUState *cs); abi_ulong get_elf_hwcap2(CPUState *cs); #endif diff --git a/linux-user/ppc/target_elf.h b/linux-user/ppc/target_elf.h index 8c0a8ea431..4203a89d66 100644 --- a/linux-user/ppc/target_elf.h +++ b/linux-user/ppc/target_elf.h @@ -8,4 +8,7 @@ #ifndef PPC_TARGET_ELF_H #define PPC_TARGET_ELF_H =20 +#define HAVE_ELF_HWCAP 1 +#define HAVE_ELF_HWCAP2 1 + #endif diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 16709865f7..843b1f7b6c 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -598,120 +598,8 @@ static inline void init_thread(struct target_pt_regs = *regs, =20 #define ELF_ARCH EM_PPC =20 -/* Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP). - See arch/powerpc/include/asm/cputable.h. */ -enum { - QEMU_PPC_FEATURE_32 =3D 0x80000000, - QEMU_PPC_FEATURE_64 =3D 0x40000000, - QEMU_PPC_FEATURE_601_INSTR =3D 0x20000000, - QEMU_PPC_FEATURE_HAS_ALTIVEC =3D 0x10000000, - QEMU_PPC_FEATURE_HAS_FPU =3D 0x08000000, - QEMU_PPC_FEATURE_HAS_MMU =3D 0x04000000, - QEMU_PPC_FEATURE_HAS_4xxMAC =3D 0x02000000, - QEMU_PPC_FEATURE_UNIFIED_CACHE =3D 0x01000000, - QEMU_PPC_FEATURE_HAS_SPE =3D 0x00800000, - QEMU_PPC_FEATURE_HAS_EFP_SINGLE =3D 0x00400000, - QEMU_PPC_FEATURE_HAS_EFP_DOUBLE =3D 0x00200000, - QEMU_PPC_FEATURE_NO_TB =3D 0x00100000, - QEMU_PPC_FEATURE_POWER4 =3D 0x00080000, - QEMU_PPC_FEATURE_POWER5 =3D 0x00040000, - QEMU_PPC_FEATURE_POWER5_PLUS =3D 0x00020000, - QEMU_PPC_FEATURE_CELL =3D 0x00010000, - QEMU_PPC_FEATURE_BOOKE =3D 0x00008000, - QEMU_PPC_FEATURE_SMT =3D 0x00004000, - QEMU_PPC_FEATURE_ICACHE_SNOOP =3D 0x00002000, - QEMU_PPC_FEATURE_ARCH_2_05 =3D 0x00001000, - QEMU_PPC_FEATURE_PA6T =3D 0x00000800, - QEMU_PPC_FEATURE_HAS_DFP =3D 0x00000400, - QEMU_PPC_FEATURE_POWER6_EXT =3D 0x00000200, - QEMU_PPC_FEATURE_ARCH_2_06 =3D 0x00000100, - QEMU_PPC_FEATURE_HAS_VSX =3D 0x00000080, - QEMU_PPC_FEATURE_PSERIES_PERFMON_COMPAT =3D 0x00000040, - - QEMU_PPC_FEATURE_TRUE_LE =3D 0x00000002, - QEMU_PPC_FEATURE_PPC_LE =3D 0x00000001, - - /* Feature definitions in AT_HWCAP2. */ - QEMU_PPC_FEATURE2_ARCH_2_07 =3D 0x80000000, /* ISA 2.07 */ - QEMU_PPC_FEATURE2_HAS_HTM =3D 0x40000000, /* Hardware Transactional Me= mory */ - QEMU_PPC_FEATURE2_HAS_DSCR =3D 0x20000000, /* Data Stream Control Regi= ster */ - QEMU_PPC_FEATURE2_HAS_EBB =3D 0x10000000, /* Event Base Branching */ - QEMU_PPC_FEATURE2_HAS_ISEL =3D 0x08000000, /* Integer Select */ - QEMU_PPC_FEATURE2_HAS_TAR =3D 0x04000000, /* Target Address Register */ - QEMU_PPC_FEATURE2_VEC_CRYPTO =3D 0x02000000, - QEMU_PPC_FEATURE2_HTM_NOSC =3D 0x01000000, - QEMU_PPC_FEATURE2_ARCH_3_00 =3D 0x00800000, /* ISA 3.00 */ - QEMU_PPC_FEATURE2_HAS_IEEE128 =3D 0x00400000, /* VSX IEEE Bin Float 12= 8-bit */ - QEMU_PPC_FEATURE2_DARN =3D 0x00200000, /* darn random number insn */ - QEMU_PPC_FEATURE2_SCV =3D 0x00100000, /* scv syscall */ - QEMU_PPC_FEATURE2_HTM_NO_SUSPEND =3D 0x00080000, /* TM w/o suspended s= tate */ - QEMU_PPC_FEATURE2_ARCH_3_1 =3D 0x00040000, /* ISA 3.1 */ - QEMU_PPC_FEATURE2_MMA =3D 0x00020000, /* Matrix-Multiply Assist */ -}; - -#define ELF_HWCAP get_elf_hwcap() - -static uint32_t get_elf_hwcap(void) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(thread_cpu); - uint32_t features =3D 0; - - /* We don't have to be terribly complete here; the high points are - Altivec/FP/SPE support. Anything else is just a bonus. */ -#define GET_FEATURE(flag, feature) \ - do { if (cpu->env.insns_flags & flag) { features |=3D feature; } } whi= le (0) -#define GET_FEATURE2(flags, feature) \ - do { \ - if ((cpu->env.insns_flags2 & flags) =3D=3D flags) { \ - features |=3D feature; \ - } \ - } while (0) - GET_FEATURE(PPC_64B, QEMU_PPC_FEATURE_64); - GET_FEATURE(PPC_FLOAT, QEMU_PPC_FEATURE_HAS_FPU); - GET_FEATURE(PPC_ALTIVEC, QEMU_PPC_FEATURE_HAS_ALTIVEC); - GET_FEATURE(PPC_SPE, QEMU_PPC_FEATURE_HAS_SPE); - GET_FEATURE(PPC_SPE_SINGLE, QEMU_PPC_FEATURE_HAS_EFP_SINGLE); - GET_FEATURE(PPC_SPE_DOUBLE, QEMU_PPC_FEATURE_HAS_EFP_DOUBLE); - GET_FEATURE(PPC_BOOKE, QEMU_PPC_FEATURE_BOOKE); - GET_FEATURE(PPC_405_MAC, QEMU_PPC_FEATURE_HAS_4xxMAC); - GET_FEATURE2(PPC2_DFP, QEMU_PPC_FEATURE_HAS_DFP); - GET_FEATURE2(PPC2_VSX, QEMU_PPC_FEATURE_HAS_VSX); - GET_FEATURE2((PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206= | - PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206), - QEMU_PPC_FEATURE_ARCH_2_06); -#undef GET_FEATURE -#undef GET_FEATURE2 - - return features; -} - -#define ELF_HWCAP2 get_elf_hwcap2() - -static uint32_t get_elf_hwcap2(void) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(thread_cpu); - uint32_t features =3D 0; - -#define GET_FEATURE(flag, feature) \ - do { if (cpu->env.insns_flags & flag) { features |=3D feature; } } whi= le (0) -#define GET_FEATURE2(flag, feature) \ - do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) - - GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); - GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR); - GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07 | - QEMU_PPC_FEATURE2_VEC_CRYPTO); - GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | - QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); - GET_FEATURE2(PPC2_ISA310, QEMU_PPC_FEATURE2_ARCH_3_1 | - QEMU_PPC_FEATURE2_MMA); - -#undef GET_FEATURE -#undef GET_FEATURE2 - - return features; -} +#define ELF_HWCAP get_elf_hwcap(thread_cpu) +#define ELF_HWCAP2 get_elf_hwcap2(thread_cpu) =20 /* * The requirements here are: diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c index 7775dc06fa..a214675650 100644 --- a/linux-user/ppc/elfload.c +++ b/linux-user/ppc/elfload.c @@ -13,3 +13,119 @@ const char *get_elf_cpu_model(uint32_t eflags) return "750"; #endif } + +/* + * Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP). + * See arch/powerpc/include/asm/cputable.h. + */ +enum { + QEMU_PPC_FEATURE_32 =3D 0x80000000, + QEMU_PPC_FEATURE_64 =3D 0x40000000, + QEMU_PPC_FEATURE_601_INSTR =3D 0x20000000, + QEMU_PPC_FEATURE_HAS_ALTIVEC =3D 0x10000000, + QEMU_PPC_FEATURE_HAS_FPU =3D 0x08000000, + QEMU_PPC_FEATURE_HAS_MMU =3D 0x04000000, + QEMU_PPC_FEATURE_HAS_4xxMAC =3D 0x02000000, + QEMU_PPC_FEATURE_UNIFIED_CACHE =3D 0x01000000, + QEMU_PPC_FEATURE_HAS_SPE =3D 0x00800000, + QEMU_PPC_FEATURE_HAS_EFP_SINGLE =3D 0x00400000, + QEMU_PPC_FEATURE_HAS_EFP_DOUBLE =3D 0x00200000, + QEMU_PPC_FEATURE_NO_TB =3D 0x00100000, + QEMU_PPC_FEATURE_POWER4 =3D 0x00080000, + QEMU_PPC_FEATURE_POWER5 =3D 0x00040000, + QEMU_PPC_FEATURE_POWER5_PLUS =3D 0x00020000, + QEMU_PPC_FEATURE_CELL =3D 0x00010000, + QEMU_PPC_FEATURE_BOOKE =3D 0x00008000, + QEMU_PPC_FEATURE_SMT =3D 0x00004000, + QEMU_PPC_FEATURE_ICACHE_SNOOP =3D 0x00002000, + QEMU_PPC_FEATURE_ARCH_2_05 =3D 0x00001000, + QEMU_PPC_FEATURE_PA6T =3D 0x00000800, + QEMU_PPC_FEATURE_HAS_DFP =3D 0x00000400, + QEMU_PPC_FEATURE_POWER6_EXT =3D 0x00000200, + QEMU_PPC_FEATURE_ARCH_2_06 =3D 0x00000100, + QEMU_PPC_FEATURE_HAS_VSX =3D 0x00000080, + QEMU_PPC_FEATURE_PSERIES_PERFMON_COMPAT =3D 0x00000040, + + QEMU_PPC_FEATURE_TRUE_LE =3D 0x00000002, + QEMU_PPC_FEATURE_PPC_LE =3D 0x00000001, + + /* Feature definitions in AT_HWCAP2. */ + QEMU_PPC_FEATURE2_ARCH_2_07 =3D 0x80000000, /* ISA 2.07 */ + QEMU_PPC_FEATURE2_HAS_HTM =3D 0x40000000, /* Hardware Transactional Me= mory */ + QEMU_PPC_FEATURE2_HAS_DSCR =3D 0x20000000, /* Data Stream Control Regi= ster */ + QEMU_PPC_FEATURE2_HAS_EBB =3D 0x10000000, /* Event Base Branching */ + QEMU_PPC_FEATURE2_HAS_ISEL =3D 0x08000000, /* Integer Select */ + QEMU_PPC_FEATURE2_HAS_TAR =3D 0x04000000, /* Target Address Register */ + QEMU_PPC_FEATURE2_VEC_CRYPTO =3D 0x02000000, + QEMU_PPC_FEATURE2_HTM_NOSC =3D 0x01000000, + QEMU_PPC_FEATURE2_ARCH_3_00 =3D 0x00800000, /* ISA 3.00 */ + QEMU_PPC_FEATURE2_HAS_IEEE128 =3D 0x00400000, /* VSX IEEE Bin Float 12= 8-bit */ + QEMU_PPC_FEATURE2_DARN =3D 0x00200000, /* darn random number insn */ + QEMU_PPC_FEATURE2_SCV =3D 0x00100000, /* scv syscall */ + QEMU_PPC_FEATURE2_HTM_NO_SUSPEND =3D 0x00080000, /* TM w/o suspended s= tate */ + QEMU_PPC_FEATURE2_ARCH_3_1 =3D 0x00040000, /* ISA 3.1 */ + QEMU_PPC_FEATURE2_MMA =3D 0x00020000, /* Matrix-Multiply Assist */ +}; + +abi_ulong get_elf_hwcap(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + uint32_t features =3D 0; + + /* + * We don't have to be terribly complete here; the high points are + * Altivec/FP/SPE support. Anything else is just a bonus. + */ +#define GET_FEATURE(flag, feature) \ + do { if (cpu->env.insns_flags & flag) { features |=3D feature; } } whi= le (0) +#define GET_FEATURE2(flags, feature) \ + do { \ + if ((cpu->env.insns_flags2 & flags) =3D=3D flags) { \ + features |=3D feature; \ + } \ + } while (0) + GET_FEATURE(PPC_64B, QEMU_PPC_FEATURE_64); + GET_FEATURE(PPC_FLOAT, QEMU_PPC_FEATURE_HAS_FPU); + GET_FEATURE(PPC_ALTIVEC, QEMU_PPC_FEATURE_HAS_ALTIVEC); + GET_FEATURE(PPC_SPE, QEMU_PPC_FEATURE_HAS_SPE); + GET_FEATURE(PPC_SPE_SINGLE, QEMU_PPC_FEATURE_HAS_EFP_SINGLE); + GET_FEATURE(PPC_SPE_DOUBLE, QEMU_PPC_FEATURE_HAS_EFP_DOUBLE); + GET_FEATURE(PPC_BOOKE, QEMU_PPC_FEATURE_BOOKE); + GET_FEATURE(PPC_405_MAC, QEMU_PPC_FEATURE_HAS_4xxMAC); + GET_FEATURE2(PPC2_DFP, QEMU_PPC_FEATURE_HAS_DFP); + GET_FEATURE2(PPC2_VSX, QEMU_PPC_FEATURE_HAS_VSX); + GET_FEATURE2((PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206= | + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206), + QEMU_PPC_FEATURE_ARCH_2_06); + +#undef GET_FEATURE +#undef GET_FEATURE2 + + return features; +} + +abi_ulong get_elf_hwcap2(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + uint32_t features =3D 0; + +#define GET_FEATURE(flag, feature) \ + do { if (cpu->env.insns_flags & flag) { features |=3D feature; } } whi= le (0) +#define GET_FEATURE2(flag, feature) \ + do { if (cpu->env.insns_flags2 & flag) { features |=3D feature; } } wh= ile (0) + + GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL); + GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR); + GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07 | + QEMU_PPC_FEATURE2_VEC_CRYPTO); + GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 | + QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128); + GET_FEATURE2(PPC2_ISA310, QEMU_PPC_FEATURE2_ARCH_3_1 | + QEMU_PPC_FEATURE2_MMA); + +#undef GET_FEATURE +#undef GET_FEATURE2 + + return features; +} --=20 2.43.0