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([38.41.223.211]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3207eca6d3asm5628217a91.23.2025.08.01.16.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Aug 2025 16:26:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1754090782; x=1754695582; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=891inftKOdhey3sFn9UdQanwKebbfZAQKRLupw103tU=; b=QL+7DQjgbFxSdgTGjmpHLfi2rWIqmcnNhIOV1LYbwIxrfWJuU3/G2j+MWoFNSv6fuP pmNWK6sfL4TpEqNH3XFkce8VQgd+a5GntuTrQ5AGZw7SnRIzd8fGiDmiwoZVa3moRq7e bMjhhMGfQvvzC0EieBmz+tPXk9w1J5cP1bFsm5QBvEjGYdwqoAwSUtvj0IGXhIbKkPeW zEC9vhaTufKOXWaFNFizI0i0M8XBeDEAlDUl5456Z5O8038s5xZWnBf7an5uta144hMu 0UjXbsXX0A30P+jbq1ADCGyILMT7tbNtTPogAiwJFEJUxZJjScn4CpNzCWF7o24cLbWL rB/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754090782; x=1754695582; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=891inftKOdhey3sFn9UdQanwKebbfZAQKRLupw103tU=; b=dwRHkBQKVh3qVnz1bzDHQJccIU807Emg2Ol9+QcObsBiFY2sHngD3oey0nWc4Ww3Wk HBJRP1fi8AiKyqiyO98umNFbn5MWcSe7s3Nv8T2n8jxHDO7U8AOHRMnudfAknBGzZuRo QOg9IIUOnrkZMUNvGAy4Zz1QoSoo2T7EgKe7PcuK2qd/4uQaApQ+eoWrDXV2UZyPFMwC pnPAwppAx5ym9UV94MIwgJmHooZ5nTAn90mZQJj08eCPHKbsciCZa9+9uoxCUKZlTR55 3ulRtbmvDFIC6BwtY9xJ1uUjvEIz3Jy0yKWqz0KUCGVH/KIHGGa+dfBLMMnkkMOgrNzY i78w== X-Gm-Message-State: AOJu0YyUq+cS8sqeYjzyxXvxxKuKDxhiJTD/WYxIeOBMmJkCRIn22Px8 uOmkE97nmLIVAxsBnqJn4JWwiOoa8t3i0E8MDONaYs8RiHI92S08USULxyK038ud6HRiVnwf3iX HjYPITco= X-Gm-Gg: ASbGnculo3SAXAiLZlcJrKwcgy3IMd6wS66yMjBwaPJk5kC+LJ+6Ji4h26w4aRiQy0e npAlQp2q2barwgl+za0vLjVs0oHAu5+FBGBA3ndMnDef7jW+bpRC+kF9u9IMJktWIt0yLkozQEP iIFRN0LoHeVerUApKQUbB+bId4TwxBVG152kSWNjaaGjdPndxaaWcIkNbf4mbbejmd/Wpc9o+PH WS8+e8f3ZwEZ0BBGdqxNCL7EIhP8es3aRpJm57rmyXlA4zDkWfmx3121szCnLQk6J4LgHeHj3lU OEzqsCPdPj11bc34Zm60Zigo1AIA4CRVC/NEgUam+Ry6MWrxc/7CVJMkARUyqjAoerRF5qMRXVx 7qTwfT0Tk0/vF/NxE6FHBpiIICrdFDtqo X-Google-Smtp-Source: AGHT+IGmYipqmpxEtASa/avLaJh40RAU9aY60Z7HLO5dSmByyj2neLGqTYGsncyN1sDyCRHVP5BLlg== X-Received: by 2002:a17:90b:53cf:b0:31f:ca:63cd with SMTP id 98e67ed59e1d1-321161d9cfamr2006709a91.2.1754090781912; Fri, 01 Aug 2025 16:26:21 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Liu Zhiwei , richard.henderson@linaro.org, Palmer Dabbelt , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Weiwei Li , qemu-arm@nongnu.org, Peter Maydell , philmd@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Pierrick Bouvier Subject: [PATCH v2 06/11] include/semihosting/common-semi: extract common_semi API Date: Fri, 1 Aug 2025 16:26:04 -0700 Message-ID: <20250801232609.2744557-7-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250801232609.2744557-1-pierrick.bouvier@linaro.org> References: <20250801232609.2744557-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754091203115124100 Content-Type: text/plain; charset="utf-8" We transform target/{arm,riscv}/common-semi-target.h headers to proper compilation units, and use them in arm-compat-semi.c. This way, we can include only the declaration header (which is target agnostic), and selectively link the appropriate implementation based on current target. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- include/semihosting/common-semi.h | 5 +++++ semihosting/arm-compat-semi.c | 3 +-- ...mmon-semi-target.h =3D> common-semi-target.c} | 18 ++++++++---------- ...mmon-semi-target.h =3D> common-semi-target.c} | 17 ++++++++--------- target/arm/meson.build | 4 ++++ target/riscv/meson.build | 4 ++++ 6 files changed, 30 insertions(+), 21 deletions(-) rename target/arm/{common-semi-target.h =3D> common-semi-target.c} (66%) rename target/riscv/{common-semi-target.h =3D> common-semi-target.c} (60%) diff --git a/include/semihosting/common-semi.h b/include/semihosting/common= -semi.h index 0a91db7c414..9b8524dca13 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -35,5 +35,10 @@ #define COMMON_SEMI_H =20 void do_common_semihosting(CPUState *cs); +uint64_t common_semi_arg(CPUState *cs, int argno); +void common_semi_set_ret(CPUState *cs, uint64_t ret); +bool is_64bit_semihosting(CPUArchState *env); +uint64_t common_semi_stack_bottom(CPUState *cs); +bool common_semi_has_synccache(CPUArchState *env); =20 #endif /* COMMON_SEMI_H */ diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index ef57d7205c8..e44e910696b 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -174,8 +174,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) =20 #endif =20 -#include "cpu.h" -#include "common-semi-target.h" +#include "semihosting/common-semi.h" =20 /* * Read the input value from the argument block; fail the semihosting diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-targe= t.c similarity index 66% rename from target/arm/common-semi-target.h rename to target/arm/common-semi-target.c index b900121272c..bad33a711d7 100644 --- a/target/arm/common-semi-target.h +++ b/target/arm/common-semi-target.c @@ -7,12 +7,12 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H -#define TARGET_ARM_COMMON_SEMI_TARGET_H - +#include "qemu/osdep.h" +#include "cpu.h" +#include "semihosting/common-semi.h" #include "target/arm/cpu-qom.h" =20 -static inline uint64_t common_semi_arg(CPUState *cs, int argno) +uint64_t common_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -23,7 +23,7 @@ static inline uint64_t common_semi_arg(CPUState *cs, int = argno) } } =20 -static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +void common_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -34,22 +34,20 @@ static inline void common_semi_set_ret(CPUState *cs, ui= nt64_t ret) } } =20 -static inline bool is_64bit_semihosting(CPUArchState *env) +bool is_64bit_semihosting(CPUArchState *env) { return is_a64(env); } =20 -static inline uint64_t common_semi_stack_bottom(CPUState *cs) +uint64_t common_semi_stack_bottom(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; return is_a64(env) ? env->xregs[31] : env->regs[13]; } =20 -static inline bool common_semi_has_synccache(CPUArchState *env) +bool common_semi_has_synccache(CPUArchState *env) { /* Ok for A64, invalid for A32/T32 */ return is_a64(env); } - -#endif diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-t= arget.c similarity index 60% rename from target/riscv/common-semi-target.h rename to target/riscv/common-semi-target.c index 2e6d6a659a3..7ac8b9164ee 100644 --- a/target/riscv/common-semi-target.h +++ b/target/riscv/common-semi-target.c @@ -8,38 +8,37 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H -#define TARGET_RISCV_COMMON_SEMI_TARGET_H +#include "qemu/osdep.h" +#include "cpu.h" +#include "semihosting/common-semi.h" =20 -static inline uint64_t common_semi_arg(CPUState *cs, int argno) +uint64_t common_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xA0 + argno]; } =20 -static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) +void common_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; env->gpr[xA0] =3D ret; } =20 -static inline bool is_64bit_semihosting(CPUArchState *env) +bool is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) !=3D MXL_RV32; } =20 -static inline uint64_t common_semi_stack_bottom(CPUState *cs) +uint64_t common_semi_stack_bottom(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xSP]; } =20 -static inline bool common_semi_has_synccache(CPUArchState *env) +bool common_semi_has_synccache(CPUArchState *env) { return true; } - -#endif diff --git a/target/arm/meson.build b/target/arm/meson.build index 07d9271aa4d..688b50a2e26 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,12 +27,16 @@ arm_user_ss.add(files( 'helper.c', 'vfp_fpscr.c', )) +arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) =20 arm_common_system_ss.add(files('cpu.c')) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) +arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a4bd61e52a9..fdefe88ccdd 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -8,6 +8,10 @@ gen =3D [ =20 riscv_ss =3D ss.source_set() riscv_ss.add(gen) + +riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', + if_true: files('common-semi-target.c')) + riscv_ss.add(files( 'cpu.c', 'cpu_helper.c', --=20 2.47.2