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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c4a2f03sm6176670f8f.72.2025.08.01.08.52.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Aug 2025 08:52:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1754063527; x=1754668327; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oirmS+SjrCLZzQhC+0iWfATmWhPBgexkPGpM/2V1o2c=; b=J6GSg2E6hpmAFIHuqS17d1eilb3THXxgYSNkT/N0jUUkhKAwHgFkhuGwmHbUb2MGyn GFer1Fi1vhTTuJBaUUVjKGxXkTmgzXORmeQgQ1xo+46Q6VNVZMlGD6/YvvMcIVGHS7w5 G+BMLE9MbciWR/01vVPWyg4Csv+VKWDT0UqZpLwHLmIkLqmPmj1nU8SJb32ByjNWgDO8 uGoBjut0FUAGsvijsZy8pLtwkv5t3agvRii1zp8VggAsNSEp5XQvFAWHqY/342kh+Vt8 NPmZB6si2oDA1wn63FNcRKp1FjF9L0LmliVxrARH4oG9AagNUHJx09LwLsiOAazWnYoa 09OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754063527; x=1754668327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oirmS+SjrCLZzQhC+0iWfATmWhPBgexkPGpM/2V1o2c=; b=kFWOYhBRLZ+8jhqHCuKs+OlwwCc/Q7fSkDWL45ZcMKaEqM5P2Kyv2AkdXkGJxkA3zl 7xBU/UwoHzPYKvJ6PGNv0NBUOXcw0GDhpmeHpO1kSw7UKBjUDKmuxRWDqKfuCNE6e5QO JYBAWXTdH7bgR47vhqX+mIEJ/UF4hDrrQc+7itlFuY2RDgZDl+omnNPtm9hqimAh3vNh l+yE4Sqzvv552ugFR42QtM0HmaPbJfWIKwhxUZifUKnZufIqzre4aJvrSYEeQ35huptC 2ItWKUBFrQr8YAceNqbBjlejp7xV5GcmZ5gl6km6HTyGo1MIvVCjNXUQNHsbxUD+n1Am CCjg== X-Gm-Message-State: AOJu0YyMEcFn41da8DmshkbKJHJJgNHUTcoiGM9A5JM7odoYi8ndvWFc U6vXEYSErRtL4lKeTcXlq4AhtU7VtYpzfVDhRWTmiXgshxI+AFNti3jlCk4AP1hhNewzKZsZ2+8 2SN0N X-Gm-Gg: ASbGnctjuHEVuG1Bp2O1Tyeefo9D3PKDRYDgtvuKC5gyXNMrbeM6sePMscfKYIHTfVI 2eeWTNXhDBPuBXTmTjPug00WgzIHPiJCWOUlnRWOslO+HOuA9oSQj7daAfc0JkfYzAbRRfRlRK1 UTC80DyH1pbTzYWh2kv3ZapksYMSM1JQunGx+05mmoBPg1NGxxkXjy5wazdonGN1QF0f5taLmdF jyBTEButKXZ6hjVCpnJpEdIvFRHI8GoTPueqjdFWqTWuA1v+OQVcHhUhtLaJH7olEkICOb3+rsC J+OFg7MAYAhKi5vM0WbOSPvNM8dz3yRALjYnbiznNA8VSDZe7cBohQ2tgF1czYMnx5Jag+eYsG5 U+caob8Tv163In3ZYoPCPHNCj/3J+vCTYCGw+tpg= X-Google-Smtp-Source: AGHT+IHW0vOblllVcKa68jQyOFI0cWRD1HmFFx/yH7oYznBv22D84R7ZXbC5UXHLoXzELcANtSUfow== X-Received: by 2002:a05:6000:2584:b0:3b8:893f:a17d with SMTP id ffacd0b85a97d-3b8d94d35d6mr178504f8f.49.1754063527452; Fri, 01 Aug 2025 08:52:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/8] hw/intc/arm_gicv3_kvm: Write all 1's to clear enable/active Date: Fri, 1 Aug 2025 16:51:54 +0100 Message-ID: <20250801155159.400947-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250801155159.400947-1-peter.maydell@linaro.org> References: <20250801155159.400947-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1754069092951116600 Content-Type: text/plain; charset="utf-8" From: Zenghui Yu KVM's userspace access interface to the GICD enable and active bits is via set/clear register pairs which implement the hardware's "write 1s to the clear register to clear the 0 bits, and write 1s to the set register to set the 1 bits" semantics. We didn't get this right, because we were writing 0 to the clear register. Writing 0 to GICD_IC{ENABLE,ACTIVE}R architecturally has no effect on interrupt status (all writes are simply ignored by KVM) and doesn't comply with the intention of "first write to the clear-reg to clear all bits". Write all 1's to actually clear the enable/active status. This didn't have any adverse effects on migration because there we start with a clean VM state; it would be guest-visible when doing a system reset, but since Linux always cleans up the register state of the GIC during bootup before it enables it most users won't have run into a problem here. Cc: qemu-stable@nongnu.org Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions") Signed-off-by: Zenghui Yu Message-id: 20250729161650.43758-3-zenghui.yu@linux.dev Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index f798a6e28ca..6166283cd1a 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -295,7 +295,7 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t off= set, * the 1 bits. */ if (clroffset !=3D 0) { - reg =3D 0; + reg =3D ~0; kvm_gicd_access(s, clroffset, ®, true); clroffset +=3D 4; } --=20 2.43.0