From nobody Sat Nov 15 08:44:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1754039554; cv=none; d=zohomail.com; s=zohoarc; b=ZHsNgfY2MP/A16DNZCRqkr4ZLUVkXVxY0Ql+09itjC7oX0rmqB/FDwW2BeX5rIjgchW8oxV1F3kQlPRQzAtuFMzgor0ouZdWd9q5+YaF4hTI8FM7fSQwSPbklP65Gg/OZTlZw7gvg5aCva+q9qgWV8HBm8uCxpAuDPBD581qDLQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754039554; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=WM03leiGkABlL2ylKx+POihVeZnT75PmalcD3kE2i7U=; b=fNSIhj7ODm1zM7F68GqvhnTXxzkNPfkJijvm1FFerz2mt0S8Bj4KNtqt3qQQBLUcA9VQaR1H80Mq4iqxZ6xREJpR4J0TQHaI5L3RSUq1ETPi8mEv/p8OMbuajjy7mAPHV4IqKMwbPyjbWB7eK6fMLT/1g7gouU2OOdMrYdSDzsY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1754039554947492.79183204375704; Fri, 1 Aug 2025 02:12:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uhlnr-0000aQ-QX; Fri, 01 Aug 2025 05:11:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uhljY-00057y-GB; Fri, 01 Aug 2025 05:07:24 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uhljV-000766-AS; Fri, 01 Aug 2025 05:07:24 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4btg2V6rTDz6L5Jq; Fri, 1 Aug 2025 17:02:42 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 1ECB21402EB; Fri, 1 Aug 2025 17:07:01 +0800 (CST) Received: from china (7.182.10.167) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 1 Aug 2025 11:06:56 +0200 To: CC: , , Peter Maydell , , , , Subject: [PATCH v2 1/2] target/arm: Trap PMCR when MDCR_EL2.TPMCR is set Date: Fri, 1 Aug 2025 17:06:44 +0800 Message-ID: <20250801090645.2205449-2-smail.aider@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250801090645.2205449-1-smail.aider@huawei.com> References: <20250801090645.2205449-1-smail.aider@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [7.182.10.167] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=smail.aider@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Smail AIDER From: Smail AIDER via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754039558792124100 Content-Type: text/plain; charset="utf-8" From: Smail AIDER via Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set. Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1 accesses to the PMCR register to EL2. Signed-off-by: Smail AIDER Message-Id: <20250722131925.2119169-1-smail.aider@huawei.com> --- target/arm/cpregs-pmu.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c index 0f295b1376..3aacd4f652 100644 --- a/target/arm/cpregs-pmu.c +++ b/target/arm/cpregs-pmu.c @@ -252,6 +252,26 @@ static CPAccessResult pmreg_access(CPUARMState *env, c= onst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* + * Check for traps to PMCR register, which are controlled by PMUSERENR.EN + * for EL1, MDCR_EL2.TPM/TPMCR for EL2 and MDCR_EL3.TPM for EL3. + */ +static CPAccessResult pmreg_access_pmcr(CPUARMState *env, const ARMCPRegIn= fo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + + CPAccessResult ret =3D pmreg_access(env, ri, isread); + + /* Check MDCR_TPMCR if not already trapped to EL1 */ + if (ret !=3D CP_ACCESS_TRAP_EL1 && el < 2 && (mdcr_el2 & MDCR_TPMCR)) { + ret =3D CP_ACCESS_TRAP_EL2; + } + + return ret; +} + static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -1192,14 +1212,14 @@ void define_pm_cpregs(ARMCPU *cpu) .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, + .accessfn =3D pmreg_access_pmcr, .readfn =3D pmcr_read, .raw_readfn =3D raw_read, .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; const ARMCPRegInfo pmcr64 =3D { .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, + .access =3D PL0_RW, .accessfn =3D pmreg_access_pmcr, .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), --=20 2.34.1 From nobody Sat Nov 15 08:44:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 1 Aug 2025 17:07:06 +0800 (CST) Received: from china (7.182.10.167) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 1 Aug 2025 11:07:01 +0200 To: CC: , , Peter Maydell , , , , Subject: [PATCH v2 2/2] target/arm: Code refactoring of pmreg_access/pmcr Date: Fri, 1 Aug 2025 17:06:45 +0800 Message-ID: <20250801090645.2205449-3-smail.aider@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250801090645.2205449-1-smail.aider@huawei.com> References: <20250801090645.2205449-1-smail.aider@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [7.182.10.167] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=smail.aider@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Smail AIDER From: Smail AIDER via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1754039558369124100 Content-Type: text/plain; charset="utf-8" Create a common helper for pmreg_access and pmreg_access_pmcr to improve readability. Signed-off-by: Smail AIDER Reviewed-by: Richard Henderson --- target/arm/cpregs-pmu.c | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c index 3aacd4f652..adaaaf2517 100644 --- a/target/arm/cpregs-pmu.c +++ b/target/arm/cpregs-pmu.c @@ -228,22 +228,28 @@ static bool event_supported(uint16_t number) return supported_event_map[number] !=3D UNSUPPORTED_EVENT; } =20 -static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) +static CPAccessResult do_pmreg_access(CPUARMState *env, bool is_pmcr) { /* * Performance monitor registers user accessibility is controlled - * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable + * by PMUSERENR. MDCR_EL2.TPM/TPMCR and MDCR_EL3.TPM allow configurable * trapping to EL2 or EL3 for other accesses. */ int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + uint64_t mdcr_el2; =20 if (el =3D=3D 0 && !(env->cp15.c9_pmuserenr & 1)) { return CP_ACCESS_TRAP_EL1; } - if (el < 2 && (mdcr_el2 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL2; + if (el < 2) { + mdcr_el2 =3D arm_mdcr_el2_eff(env); + + if (mdcr_el2 & MDCR_TPM) { + return CP_ACCESS_TRAP_EL2; + } + if (is_pmcr && (mdcr_el2 & MDCR_TPMCR)) { + return CP_ACCESS_TRAP_EL2; + } } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { return CP_ACCESS_TRAP_EL3; @@ -252,24 +258,16 @@ static CPAccessResult pmreg_access(CPUARMState *env, = const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -/* - * Check for traps to PMCR register, which are controlled by PMUSERENR.EN - * for EL1, MDCR_EL2.TPM/TPMCR for EL2 and MDCR_EL3.TPM for EL3. - */ -static CPAccessResult pmreg_access_pmcr(CPUARMState *env, const ARMCPRegIn= fo *ri, +static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - - CPAccessResult ret =3D pmreg_access(env, ri, isread); - - /* Check MDCR_TPMCR if not already trapped to EL1 */ - if (ret !=3D CP_ACCESS_TRAP_EL1 && el < 2 && (mdcr_el2 & MDCR_TPMCR)) { - ret =3D CP_ACCESS_TRAP_EL2; - } + return do_pmreg_access(env, false); +} =20 - return ret; +static CPAccessResult pmreg_access_pmcr(CPUARMState *env, const ARMCPRegIn= fo *ri, + bool isread) +{ + return do_pmreg_access(env, true); } =20 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, --=20 2.34.1