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Fri, 01 Aug 2025 00:47:46 -0700 (PDT) From: Shameer Kolothum To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: eric.auger@redhat.com, peter.maydell@linaro.org, cohuck@redhat.com, sebott@redhat.com, berrange@redhat.com, maz@kernel.org, oliver.upton@linux.dev, armbru@redhat.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, salil.mehta@huawei.com, yangjinqian1@huawei.com, shameerkolothum@gmail.com, shameerali.kolothum.thodi@huawei.com Subject: [RFC PATCH RESEND 3/4] target/arm/kvm: Handle KVM Target Imp CPU hypercalls Date: Fri, 1 Aug 2025 08:47:29 +0100 Message-ID: <20250801074730.28329-4-shameerkolothum@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250801074730.28329-1-shameerkolothum@gmail.com> References: <20250801074730.28329-1-shameerkolothum@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=shameerkolothum@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 01 Aug 2025 09:35:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1754055426169116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum When target implementation CPUs are set, handle the related hyper calls correctly by returning the information requested. Signed-off-by: Shameer Kolothum --- target/arm/kvm.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8f325c4ca4..5adecc864e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1697,6 +1697,71 @@ static bool kvm_arm_handle_debug(ARMCPU *cpu, return false; } =20 +/* Only supports HYP_KVM_DISCOVER_IMPL_XXX hypercalls */ +static void arm_handle_smccc_kvm_vendor_hypercall(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + uint64_t param[4] =3D { }; + uint64_t idx; + + if (!is_a64(env)) { + env->regs[0] =3D SMCCC_RET_NOT_SUPPORTED; + return; + } + + memcpy(param, env->xregs, sizeof(param)); + + switch (param[0]) { + case ARM_SMCCC_VENDOR_HYP_KVM_DISCOVER_IMPL_VER_FUNC_ID: + if (!target_impl_cpus_num) { + env->xregs[0] =3D SMCCC_RET_NOT_SUPPORTED; + return; + } + env->xregs[0] =3D SMCCC_RET_SUCCESS; + env->xregs[1] =3D PSCI_VERSION(1, 0); + env->xregs[2] =3D target_impl_cpus_num; + break; + case ARM_SMCCC_VENDOR_HYP_KVM_DISCOVER_IMPL_CPUS_FUNC_ID: + idx =3D param[1]; + + if (!target_impl_cpus_num || idx >=3D target_impl_cpus_num) { + env->xregs[0] =3D SMCCC_RET_INVALID_PARAMETER; + return; + } + + env->xregs[0] =3D SMCCC_RET_SUCCESS; + env->xregs[1] =3D target_impl_cpus[idx].midr; + env->xregs[2] =3D target_impl_cpus[idx].revidr; + env->xregs[3] =3D target_impl_cpus[idx].aidr; + break; + default: + env->xregs[0] =3D SMCCC_RET_NOT_SUPPORTED; + } +} + +static int kvm_arm_handle_hypercall(CPUState *cs, struct kvm_run *run) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + kvm_cpu_synchronize_state(cs); + + if (run->hypercall.flags =3D=3D KVM_HYPERCALL_EXIT_SMC) { + cs->exception_index =3D EXCP_SMC; + env->exception.syndrome =3D syn_aa64_smc(0); + } else { + cs->exception_index =3D EXCP_HVC; + env->exception.syndrome =3D syn_aa64_hvc(0); + } + env->exception.target_el =3D 1; + + bql_lock(); + arm_handle_smccc_kvm_vendor_hypercall(cpu); + bql_unlock(); + + return EXCP_INTERRUPT; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -1713,6 +1778,9 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run= *run) ret =3D kvm_arm_handle_dabt_nisv(cpu, run->arm_nisv.esr_iss, run->arm_nisv.fault_ipa); break; + case KVM_EXIT_HYPERCALL: + ret =3D kvm_arm_handle_hypercall(cs, run); + break; default: qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", __func__, run->exit_reason); @@ -2212,6 +2280,29 @@ static int kvm_arm_sve_set_vls(ARMCPU *cpu) return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); } =20 +/* + * Supported Target Implementation CPU hypercalls: + * KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_VER =3D 0, + * KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_CPUS =3D 1 + * + * Setting these bits advertises the availability of the corresponding + * Target Implementation CPU hypercalls to the guest. + */ +#define BMAP_2_DISCOVER_IMPL_BITS 0x3ULL +static int kvm_arm_target_impl_cpus_set_hyp_bmap2(ARMCPU *cpu) +{ + uint64_t bmap2; + int ret; + + ret =3D kvm_get_one_reg(CPU(cpu), KVM_REG_ARM_VENDOR_HYP_BMAP_2, &bmap= 2); + if (ret) { + return ret; + } + + bmap2 |=3D BMAP_2_DISCOVER_IMPL_BITS; + return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM_VENDOR_HYP_BMAP_2, &bmap2= ); +} + #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 =20 int kvm_arch_init_vcpu(CPUState *cs) @@ -2293,6 +2384,14 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 + /* Set KVM_REG_ARM_VENDOR_HYP_BMAP_2 if target impl CPUs are required = */ + if (target_impl_cpus_num) { + ret =3D kvm_arm_target_impl_cpus_set_hyp_bmap2(cpu); + if (ret) { + return ret; + } + } + ret =3D kvm_arm_init_cpreg_list(cpu); if (ret) { return ret; --=20 2.34.1