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There is no semantic change, and allows us to extract a proper API from this set of functions. Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/arm/common-semi-target.h | 6 +++--- target/riscv/common-semi-target.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-targe= t.h index 7ebd2136d93..b900121272c 100644 --- a/target/arm/common-semi-target.h +++ b/target/arm/common-semi-target.h @@ -12,7 +12,7 @@ =20 #include "target/arm/cpu-qom.h" =20 -static inline target_ulong common_semi_arg(CPUState *cs, int argno) +static inline uint64_t common_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -23,7 +23,7 @@ static inline target_ulong common_semi_arg(CPUState *cs, = int argno) } } =20 -static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) +static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -39,7 +39,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) return is_a64(env); } =20 -static inline target_ulong common_semi_stack_bottom(CPUState *cs) +static inline uint64_t common_semi_stack_bottom(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-t= arget.h index 63bbcd2d5fa..2e6d6a659a3 100644 --- a/target/riscv/common-semi-target.h +++ b/target/riscv/common-semi-target.h @@ -11,14 +11,14 @@ #ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H #define TARGET_RISCV_COMMON_SEMI_TARGET_H =20 -static inline target_ulong common_semi_arg(CPUState *cs, int argno) +static inline uint64_t common_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xA0 + argno]; } =20 -static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) +static inline void common_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -30,7 +30,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) return riscv_cpu_mxl(env) !=3D MXL_RV32; } =20 -static inline target_ulong common_semi_stack_bottom(CPUState *cs) +static inline uint64_t common_semi_stack_bottom(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; --=20 2.47.2