From nobody Sat Jun 27 22:56:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17538447179031022.0704315458717; Tue, 29 Jul 2025 20:05:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugx5d-0004Vr-Hm; Tue, 29 Jul 2025 23:02:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugx5L-0004Mn-6w for qemu-devel@nongnu.org; Tue, 29 Jul 2025 23:02:31 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugx5I-0007IP-Te for qemu-devel@nongnu.org; Tue, 29 Jul 2025 23:02:30 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxQK83i4lo87o0AQ--.5035S3; Wed, 30 Jul 2025 11:02:15 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxE+Qri4loJ_AsAA--.30108S10; Wed, 30 Jul 2025 11:02:14 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte() Date: Wed, 30 Jul 2025 11:01:51 +0800 Message-Id: <20250730030202.3425934-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250730030202.3425934-1-maobibo@loongson.cn> References: <20250730030202.3425934-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+Qri4loJ_AsAA--.30108S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1753844718598116600 Content-Type: text/plain; charset="utf-8" Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge if found. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/cpu-mmu.h | 10 +++++ target/loongarch/cpu_helper.c | 61 ++++++++++++++++++++++++++++ target/loongarch/tcg/tlb_helper.c | 66 ++++++------------------------- 3 files changed, 83 insertions(+), 54 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index dffc12820f..be3d11d3c1 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -19,7 +19,17 @@ typedef enum TLBRet { TLBRET_PE, } TLBRet; =20 +typedef struct MMUContext { + vaddr addr; + uint64_t pte; + hwaddr physical; + int ps; /* page size shift */ + int prot; +} MMUContext; + bool check_ps(CPULoongArchState *ent, uint8_t ps); +TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, + MMUAccessType access_type, int mmu_idx); TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, vaddr address, MMUAccessType access_type, int mmu_idx, diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 547b9a0877..5b140316bc 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -44,6 +44,67 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t= *dir_base, } } =20 +TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, + MMUAccessType access_type, int mmu_idx) +{ + uint64_t plv =3D mmu_idx; + uint64_t tlb_entry, tlb_ppn; + uint8_t tlb_ps, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + + tlb_entry =3D context->pte; + tlb_ps =3D context->ps; + tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); + tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); + if (is_la64(env)) { + tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); + tlb_nx =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NX); + tlb_nr =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NR); + tlb_rplv =3D FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV); + } else { + tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_32, PPN); + tlb_nx =3D 0; + tlb_nr =3D 0; + tlb_rplv =3D 0; + } + + /* Remove sw bit between bit12 -- bit PS*/ + tlb_ppn =3D tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1)); + + /* Check access rights */ + if (!tlb_v) { + return TLBRET_INVALID; + } + + if (access_type =3D=3D MMU_INST_FETCH && tlb_nx) { + return TLBRET_XI; + } + + if (access_type =3D=3D MMU_DATA_LOAD && tlb_nr) { + return TLBRET_RI; + } + + if (((tlb_rplv =3D=3D 0) && (plv > tlb_plv)) || + ((tlb_rplv =3D=3D 1) && (plv !=3D tlb_plv))) { + return TLBRET_PE; + } + + if ((access_type =3D=3D MMU_DATA_STORE) && !tlb_d) { + return TLBRET_DIRTY; + } + + context->physical =3D (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | + (context->addr & MAKE_64BIT_MASK(0, tlb_ps)); + context->prot =3D PAGE_READ; + if (tlb_d) { + context->prot |=3D PAGE_WRITE; + } + if (!tlb_nx) { + context->prot |=3D PAGE_EXEC; + } + return TLBRET_MATCH; +} + static TLBRet loongarch_page_table_walker(CPULoongArchState *env, hwaddr *physical, int *prot, vaddr address) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 915b1aadb5..10322da62e 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -654,64 +654,22 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchSta= te *env, hwaddr *physical, int mmu_idx) { LoongArchTLB *tlb =3D &env->tlb[index]; - uint64_t plv =3D mmu_idx; - uint64_t tlb_entry, tlb_ppn; - uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + uint8_t tlb_ps, n; + MMUContext context; + TLBRet ret; =20 tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); n =3D (address >> tlb_ps) & 0x1;/* Odd or even */ + context.pte =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; + context.addr =3D address; + context.ps =3D tlb_ps; + ret =3D loongarch_check_pte(env, &context, access_type, mmu_idx); + if (ret =3D=3D TLBRET_MATCH) { + *physical =3D context.physical; + *prot =3D context.prot; + } =20 - tlb_entry =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; - tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); - tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); - tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); - if (is_la64(env)) { - tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); - tlb_nx =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NX); - tlb_nr =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NR); - tlb_rplv =3D FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV); - } else { - tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_32, PPN); - tlb_nx =3D 0; - tlb_nr =3D 0; - tlb_rplv =3D 0; - } - - /* Remove sw bit between bit12 -- bit PS*/ - tlb_ppn =3D tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1)); - - /* Check access rights */ - if (!tlb_v) { - return TLBRET_INVALID; - } - - if (access_type =3D=3D MMU_INST_FETCH && tlb_nx) { - return TLBRET_XI; - } - - if (access_type =3D=3D MMU_DATA_LOAD && tlb_nr) { - return TLBRET_RI; - } - - if (((tlb_rplv =3D=3D 0) && (plv > tlb_plv)) || - ((tlb_rplv =3D=3D 1) && (plv !=3D tlb_plv))) { - return TLBRET_PE; - } - - if ((access_type =3D=3D MMU_DATA_STORE) && !tlb_d) { - return TLBRET_DIRTY; - } - - *physical =3D (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | - (address & MAKE_64BIT_MASK(0, tlb_ps)); - *prot =3D PAGE_READ; - if (tlb_d) { - *prot |=3D PAGE_WRITE; - } - if (!tlb_nx) { - *prot |=3D PAGE_EXEC; - } - return TLBRET_MATCH; + return ret; } =20 TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physica= l, --=20 2.39.3