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Mon, 28 Jul 2025 11:16:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mjt@tls.msk.ru, Fabiano Rosas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH 1/9] target/arm/sme: Reorg SME access handling in handle_msr_i() Date: Mon, 28 Jul 2025 08:16:42 -1000 Message-ID: <20250728181650.165114-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250728181650.165114-1-richard.henderson@linaro.org> References: <20250728181650.165114-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753726835374116600 Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230112102436.1913-2-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell (cherry picked from commit 535ca76425fc1ffa4311b3a47518b06c596a55c6) --- target/arm/translate-a64.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7210a9cc4d..b66561a5cf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1855,18 +1855,20 @@ static void handle_msr_i(DisasContext *s, uint32_t = insn, goto do_unallocated; } if (sme_access_check(s)) { - bool i =3D crm & 1; - bool changed =3D false; + int old =3D s->pstate_sm | (s->pstate_za << 1); + int new =3D (crm & 1) * 3; + int msk =3D (crm >> 1) & 3; =20 - if ((crm & 2) && i !=3D s->pstate_sm) { - gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i)); - changed =3D true; - } - if ((crm & 4) && i !=3D s->pstate_za) { - gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i)); - changed =3D true; - } - if (changed) { + if ((old ^ new) & msk) { + /* At least one bit changes. */ + bool i =3D crm & 1; + + if ((crm & 2) && i !=3D s->pstate_sm) { + gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i)); + } + if ((crm & 4) && i !=3D s->pstate_za) { + gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i)); + } gen_rebuild_hflags(s); } else { s->base.is_jmp =3D DISAS_NEXT; --=20 2.43.0 From nobody Sat Nov 15 07:40:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 28 Jul 2025 11:16:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mjt@tls.msk.ru, Fabiano Rosas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH 2/9] target/arm/sme: Rebuild hflags in set_pstate() helpers Date: Mon, 28 Jul 2025 08:16:43 -1000 Message-ID: <20250728181650.165114-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250728181650.165114-1-richard.henderson@linaro.org> References: <20250728181650.165114-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753727097196116600 Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230112102436.1913-3-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell (cherry picked from commit 3c9ee548948870c14235e3fa8fb235c0c1c20822) --- target/arm/sme_helper.c | 2 ++ target/arm/translate-a64.c | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index e8b4ca38ff..8ba3f3a247 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -45,6 +45,7 @@ void helper_set_pstate_sm(CPUARMState *env, uint32_t i) } env->svcr ^=3D R_SVCR_SM_MASK; arm_reset_sve_state(env); + arm_rebuild_hflags(env); } =20 void helper_set_pstate_za(CPUARMState *env, uint32_t i) @@ -65,6 +66,7 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) if (i) { memset(env->zarray, 0, sizeof(env->zarray)); } + arm_rebuild_hflags(env); } =20 void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b66561a5cf..fa568aa647 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1869,7 +1869,6 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, if ((crm & 4) && i !=3D s->pstate_za) { gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i)); } - gen_rebuild_hflags(s); } else { s->base.is_jmp =3D DISAS_NEXT; } --=20 2.43.0 From nobody Sat Nov 15 07:40:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 28 Jul 2025 11:16:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mjt@tls.msk.ru, Fabiano Rosas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH 3/9] target/arm/sme: Introduce aarch64_set_svcr() Date: Mon, 28 Jul 2025 08:16:44 -1000 Message-ID: <20250728181650.165114-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250728181650.165114-1-richard.henderson@linaro.org> References: <20250728181650.165114-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753726899734116600 Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230112102436.1913-4-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell (cherry picked from commit 2a8af3825958e5d8c98b3ca92ac42a10e25db9e1) --- target/arm/cpu.h | 1 + linux-user/aarch64/cpu_loop.c | 2 +- linux-user/aarch64/signal.c | 2 +- target/arm/helper.c | 8 ++++++++ target/arm/sme_helper.c | 4 ++-- 5 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32b0bf8e2d..8acfd3af4c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1118,6 +1118,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uin= t8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); +void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); void arm_reset_sve_state(CPUARMState *env); =20 /* diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 9875d609a9..d53742e10b 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -93,8 +93,8 @@ void cpu_loop(CPUARMState *env) * On syscall, PSTATE.ZA is preserved, along with the ZA matri= x. * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. */ + aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); if (FIELD_EX64(env->svcr, SVCR, SM)) { - env->svcr =3D FIELD_DP64(env->svcr, SVCR, SM, 0); arm_rebuild_hflags(env); arm_reset_sve_state(env); } diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 6a2c6e06d2..b6e4dcb494 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -669,11 +669,11 @@ static void target_setup_frame(int usig, struct targe= t_sigaction *ka, * Invoke the signal handler with both SM and ZA disabled. * When clearing SM, ResetSVEState, per SMSTOP. */ + aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); if (FIELD_EX64(env->svcr, SVCR, SM)) { arm_reset_sve_state(env); } if (env->svcr) { - env->svcr =3D 0; arm_rebuild_hflags(env); } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 6cffbcb276..86b97daf7e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6429,11 +6429,19 @@ static CPAccessResult access_esm(CPUARMState *env, = const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask) +{ + uint64_t change =3D (env->svcr ^ new) & mask; + + env->svcr ^=3D change; +} + static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM)); helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA)); + aarch64_set_svcr(env, value, -1); arm_rebuild_hflags(env); } =20 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 8ba3f3a247..7717dab64f 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -43,7 +43,7 @@ void helper_set_pstate_sm(CPUARMState *env, uint32_t i) if (i =3D=3D FIELD_EX64(env->svcr, SVCR, SM)) { return; } - env->svcr ^=3D R_SVCR_SM_MASK; + aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); arm_reset_sve_state(env); arm_rebuild_hflags(env); } @@ -53,7 +53,7 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) if (i =3D=3D FIELD_EX64(env->svcr, SVCR, ZA)) { return; } - env->svcr ^=3D R_SVCR_ZA_MASK; + aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK); =20 /* * ResetSMEState. --=20 2.43.0 From nobody Sat Nov 15 07:40:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753726911; cv=none; d=zohomail.com; s=zohoarc; b=GJyGvBeTVckBErGhGUgT7TEVTJBxBbOwr4yrg1z0GNsc6CKcLuswOBEChnttz8OoVz3IA0rGEMYf4oAoE6KLkSrhk4ekP7nsp/LC5yBTdQQY5lXQffmpMGrgMYVb+gInQauLTI+E+pGDBR59wVjJpr5aP4RYlTj2dBQ1LVxdpWo= ARC-Message-Signature: i=1; a=rsa-sha256; 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Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230112102436.1913-5-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell (cherry picked from commit 7f2a01e7368f960fadea38f437d0f6de7f249686) --- target/arm/cpu.h | 1 - linux-user/aarch64/cpu_loop.c | 1 - linux-user/aarch64/signal.c | 8 +------- target/arm/helper.c | 13 +++++++++++++ target/arm/sme_helper.c | 10 ---------- 5 files changed, 14 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8acfd3af4c..02a084c962 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1119,7 +1119,6 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned= vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); -void arm_reset_sve_state(CPUARMState *env); =20 /* * SVE registers are encoded in KVM's memory in an endianness-invariant fo= rmat. diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index d53742e10b..5e93d27d8f 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -96,7 +96,6 @@ void cpu_loop(CPUARMState *env) aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); if (FIELD_EX64(env->svcr, SVCR, SM)) { arm_rebuild_hflags(env); - arm_reset_sve_state(env); } ret =3D do_syscall(env, env->xregs[8], diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index b6e4dcb494..a326a6def5 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -665,14 +665,8 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, env->btype =3D 2; } =20 - /* - * Invoke the signal handler with both SM and ZA disabled. - * When clearing SM, ResetSVEState, per SMSTOP. - */ + /* Invoke the signal handler with both SM and ZA disabled. */ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); - if (FIELD_EX64(env->svcr, SVCR, SM)) { - arm_reset_sve_state(env); - } if (env->svcr) { arm_rebuild_hflags(env); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 86b97daf7e..94a6f431a9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6429,11 +6429,24 @@ static CPAccessResult access_esm(CPUARMState *env, = const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* ResetSVEState */ +static void arm_reset_sve_state(CPUARMState *env) +{ + memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); + /* Recall that FFR is stored as pregs[16]. */ + memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); + vfp_set_fpcr(env, 0x0800009f); +} + void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask) { uint64_t change =3D (env->svcr ^ new) & mask; =20 env->svcr ^=3D change; + + if (change & R_SVCR_SM_MASK) { + arm_reset_sve_state(env); + } } =20 static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 7717dab64f..56a8fbe691 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -29,22 +29,12 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" =20 -/* ResetSVEState */ -void arm_reset_sve_state(CPUARMState *env) -{ - memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); - /* Recall that FFR is stored as pregs[16]. */ - memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); - vfp_set_fpsr(env, 0x0800009f); -} - void helper_set_pstate_sm(CPUARMState *env, uint32_t i) { if (i =3D=3D FIELD_EX64(env->svcr, SVCR, SM)) { return; } aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); - arm_reset_sve_state(env); arm_rebuild_hflags(env); } =20 --=20 2.43.0 From nobody Sat Nov 15 07:40:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753727062; cv=none; d=zohomail.com; s=zohoarc; b=QUdtJa2oFCIR/+4It/ibo2hX6y9cSfN3IMlZLMrA5ddPVUM/EkXyLyt6jDcG4xfpA+u3Rl9Nl4A4yMRYdsIMKqwW3sUiqm9D87N1h4EfeY96xraJvao1++wDYx1wMWTB/p1EogfDnV8ofe/g3Fl3CClSZSsH2TMmrSqqgHcs1R4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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We can zero this only + * on enable: while disabled, the storage is inaccessible and the + * value does not matter. We're not saving the storage in vmstate + * when disabled either. + */ + if (change & new & R_SVCR_ZA_MASK) { + memset(env->zarray, 0, sizeof(env->zarray)); + } } =20 static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 56a8fbe691..247c2823ac 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -44,18 +44,6 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) return; } aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK); - - /* - * ResetSMEState. - * - * SetPSTATE_ZA zeros on enable and disable. We can zero this only - * on enable: while disabled, the storage is inaccessible and the - * value does not matter. We're not saving the storage in vmstate - * when disabled either. - */ - if (i) { - memset(env->zarray, 0, sizeof(env->zarray)); - } arm_rebuild_hflags(env); } =20 --=20 2.43.0 From nobody Sat Nov 15 07:40:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753726920; cv=none; d=zohomail.com; s=zohoarc; b=Kk2rwv3JZ4qiGCJ8tx2lh+tOFmnz52HAx2pkfe4SYsDc1/pz2DDAukoxO2mf5CskaWAm5J37c8aAjTRkQY92t2huPYY867JXFFKE1H8C/SAcbDw0Fzmay833UdurBuZ5D2FZaBbMx7y7jteT3cy6MChCQykjYZUUxz7MvmjxANs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753726920; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=c4+S7J9BtCEfIMC9GTPfnu5U0/LIAxmsC+ABvyfodl8=; b=S0hYtIrzrnK2nJhwCY0gT5S4BtG6ge8P3k1LlcgUoqlGjL5Lnr9y7DPFjXNl5lj9Iz0tlSKjVpAV3+vTW9rMvtPShKNviALH/ONMbuLkF0HH4eAfBu35opvgaly+uuOIWbTppnXe1S7CRLAJUd67XzNmiDj7peEpXlqKg9zD3PA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17537269205511010.2135900496493; Mon, 28 Jul 2025 11:22:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugSTs-00028V-R1; Mon, 28 Jul 2025 14:21:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugSPQ-0004rp-IP for qemu-devel@nongnu.org; Mon, 28 Jul 2025 14:17:28 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ugSPI-0002oX-OT for qemu-devel@nongnu.org; Mon, 28 Jul 2025 14:17:07 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-7425bd5a83aso4491142b3a.0 for ; Mon, 28 Jul 2025 11:17:03 -0700 (PDT) Received: from localhost.localdomain (syn-098-150-199-049.res.spectrum.com. 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Mon, 28 Jul 2025 11:17:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mjt@tls.msk.ru, Fabiano Rosas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH 6/9] target/arm/sme: Rebuild hflags in aarch64_set_svcr() Date: Mon, 28 Jul 2025 08:16:47 -1000 Message-ID: <20250728181650.165114-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250728181650.165114-1-richard.henderson@linaro.org> References: <20250728181650.165114-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753726921929116600 Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230112102436.1913-7-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell (cherry picked from commit f4318557149184d6dac99e561acabcb602a84ee1) --- linux-user/aarch64/cpu_loop.c | 8 +------- linux-user/aarch64/signal.c | 3 --- target/arm/helper.c | 6 +++++- target/arm/sme_helper.c | 8 -------- 4 files changed, 6 insertions(+), 19 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 5e93d27d8f..2e2f7cf218 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -89,14 +89,8 @@ void cpu_loop(CPUARMState *env) =20 switch (trapnr) { case EXCP_SWI: - /* - * On syscall, PSTATE.ZA is preserved, along with the ZA matri= x. - * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. - */ + /* On syscall, PSTATE.ZA is preserved, PSTATE.SM is cleared. */ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); - if (FIELD_EX64(env->svcr, SVCR, SM)) { - arm_rebuild_hflags(env); - } ret =3D do_syscall(env, env->xregs[8], env->xregs[0], diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index a326a6def5..b265cfd470 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -667,9 +667,6 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, =20 /* Invoke the signal handler with both SM and ZA disabled. */ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); - if (env->svcr) { - arm_rebuild_hflags(env); - } =20 if (info) { tswap_siginfo(&frame->info, info); diff --git a/target/arm/helper.c b/target/arm/helper.c index 37e018e765..bc1c5a1f17 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6442,6 +6442,9 @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new,= uint64_t mask) { uint64_t change =3D (env->svcr ^ new) & mask; =20 + if (change =3D=3D 0) { + return; + } env->svcr ^=3D change; =20 if (change & R_SVCR_SM_MASK) { @@ -6459,6 +6462,8 @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new,= uint64_t mask) if (change & new & R_SVCR_ZA_MASK) { memset(env->zarray, 0, sizeof(env->zarray)); } + + arm_rebuild_hflags(env); } =20 static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6467,7 +6472,6 @@ static void svcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM)); helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA)); aarch64_set_svcr(env, value, -1); - arm_rebuild_hflags(env); } =20 static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 247c2823ac..bbda651974 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -31,20 +31,12 @@ =20 void helper_set_pstate_sm(CPUARMState *env, uint32_t i) { - if (i =3D=3D FIELD_EX64(env->svcr, SVCR, SM)) { - return; - } aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); - arm_rebuild_hflags(env); } =20 void helper_set_pstate_za(CPUARMState *env, uint32_t i) { - if (i =3D=3D FIELD_EX64(env->svcr, SVCR, ZA)) { - return; - } aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK); - arm_rebuild_hflags(env); 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Do not call helper_* functions from svcr_write. Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230112102436.1913-8-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell (cherry picked from commit 5c922ec5b136b452fe9d21e7581c99554ce650ed) --- target/arm/helper-sme.h | 3 +-- target/arm/helper.c | 2 -- target/arm/sme_helper.c | 9 ++------- target/arm/translate-a64.c | 10 ++-------- 4 files changed, 5 insertions(+), 19 deletions(-) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index d33fbcd8fd..d22bf9d21b 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -17,8 +17,7 @@ * License along with this library; if not, see . */ =20 -DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) -DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_3(set_svcr, TCG_CALL_NO_RWG, void, env, i32, i32) =20 DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index bc1c5a1f17..cd501929d7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6469,8 +6469,6 @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new,= uint64_t mask) static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM)); - helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA)); aarch64_set_svcr(env, value, -1); } =20 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index bbda651974..3b7c6cd317 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -29,14 +29,9 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" =20 -void helper_set_pstate_sm(CPUARMState *env, uint32_t i) +void helper_set_svcr(CPUARMState *env, uint32_t val, uint32_t mask) { - aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); -} - -void helper_set_pstate_za(CPUARMState *env, uint32_t i) -{ - aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK); + aarch64_set_svcr(env, val, mask); } =20 void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fa568aa647..9830fe70cf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1861,14 +1861,8 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, =20 if ((old ^ new) & msk) { /* At least one bit changes. */ - bool i =3D crm & 1; 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This is necessary for the userspace ZA lazy saving scheme to work correctly when unwinding exceptions across a signal boundary. (For the essay-length description of the incorrect behaviour and why this is the correct fix, see the commit message for the kernel commit.) Make QEMU also clear TPIDR2_EL0 on signal entry, applying the equivalent bugfix to our implementation. Note that getting this unwinding to work correctly also requires changes to the userspace code, e.g. as implemented in gcc in https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3Db5ffc8e75a8 This change is technically an ABI change; from the kernel's point of view SME was never enabled (it was hidden behind CONFIG_BROKEN) before the change. From QEMU's point of view our SME-related signal handling was broken anyway as we weren't saving and restoring TPIDR2_EL0. Cc: qemu-stable@nongnu.org Fixes: 78011586b90d1 ("target/arm: Enable SME for user-only") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250725175510.3864231-2-peter.maydell@linaro.org> (cherry picked from commit 3cdd990aa920ec8f2994b634f758dab4a86ac167) --- linux-user/aarch64/signal.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index b265cfd470..85cb25ae91 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -665,8 +665,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, env->btype =3D 2; } =20 - /* Invoke the signal handler with both SM and ZA disabled. */ + /* + * Invoke the signal handler with a clean SME state: both SM and ZA + * disabled and TPIDR2_EL0 cleared. + */ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + env->cp15.tpidr2_el0 =3D 0; =20 if (info) { tswap_siginfo(&frame->info, info); --=20 2.43.0 From nobody Sat Nov 15 07:40:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753727177; cv=none; d=zohomail.com; s=zohoarc; b=HkfwlhTzFFBjw359DhFTCshm5O1Z/9XTp/weU+IsIdI2tCwC+Nu4+KJXl45mCx9tLT9Q5IYdGuKQbuJdaq+UvXDjRipt7riPZWd9PisczAVJUKYsADwCH5+nlz1+SpvYEQs3BJNKvoX+EY5ENVvMhVxt6Id6varVW9ooqKmXwJ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753727177; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kVSdrHVg+gZm9GUqSrLIm0OvO9Omr02nYyCD4B9AD/U=; b=D0mRROXu77mIUmGVGuSfLEEVRs0H/ENjXVUv01P2TTHeUrEu1ws/dvh1jxZOScMbZAq02SqRSoU+GBEQpy1/JFHUfEfqbyZtsy5A370g+eUbZAJpyiLde8rIQpRdaaP6FFFPZwRIPvGUUau3L4KOFYLLrMf34Dj+bG35u6VxDzI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753727177930665.3067531813315; Mon, 28 Jul 2025 11:26:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugSTr-00024A-P6; Mon, 28 Jul 2025 14:21:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugSPT-0004tS-LO for qemu-devel@nongnu.org; Mon, 28 Jul 2025 14:17:28 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ugSPP-0002pQ-TE for qemu-devel@nongnu.org; Mon, 28 Jul 2025 14:17:15 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-748e81d37a7so3162498b3a.1 for ; Mon, 28 Jul 2025 11:17:08 -0700 (PDT) Received: from localhost.localdomain (syn-098-150-199-049.res.spectrum.com. [98.150.199.49]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7640adfeb83sm5985103b3a.66.2025.07.28.11.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Jul 2025 11:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753726627; x=1754331427; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kVSdrHVg+gZm9GUqSrLIm0OvO9Omr02nYyCD4B9AD/U=; b=cV3B1wTgbUERLhzxV2nC/bqVibrH93C0UUDqD+cis86vuKfxZyVmL0+0cvPgM+NAib +cTSDVyj3+b3rMGubsIlAYlKznJ3HUTu+oG0LUwWmKgEXlDoPYfbOdOvfjP6Vs6GdX2w IgJPUctjNvDpXRmjGLVpRytqGzavLxEEYv9noCogpwcJKdXPcV1KIlPRShO6d8GjzaRx EbG1ppwO0G8k7oTvS04CX866Sj/1rQylRwCcfmzqPMKYmQSlSm+J0knQdWH0B2HCmq+5 FienY1y5pIcr7zNBpusMez7Bbey0fA9vDwiDkJLqlQmjpICb8ey49WTwcblgWsNpXWPD xsVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753726627; x=1754331427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kVSdrHVg+gZm9GUqSrLIm0OvO9Omr02nYyCD4B9AD/U=; b=UNMko1BEJC07spbYH85RwddkY6TawOdYGIbE9nmEe5KEVeV9brDZqs4K7NMW6ZysKy CVXLB781QlhJSRj3lBySCA4S9mAxYDLVpdk/8ct2tnxWR2Tq+JwG0VXn1SYIA1hKxd6T tXNIcU50Byjvt2xDDrHLFSAR6U79WVaFUVtzmpgiAtX05QxkDfOPqPreoFhTRf432Kcf boBTXg8bBvy/GYL5IivNkYiaqBKr13dqkaKSGuiqinsWYDMLxthI6czRKQUOepcBvLc7 kaunERfCJV0sxE2PzrTDdjgRsickxLRlunW0FgfqZuiL+lHFvs/Ij8KctWUVus4i/lOR Vl3g== X-Gm-Message-State: AOJu0YyYdzxLLyTcXS0wY9Ow0n3xFXMF6ZMdbGX7gAjN987YK5YYloIN opTywRuPOS+AdzfI5iGlg7qpTokho90d1X1tbVAX6q/SR06b+kbAm+pS5RakBrXEiN5Xv8cLnIm 2xgfq X-Gm-Gg: ASbGncuV8kJ1GxMS9fukQJ5Z/HkA9Sn9fnc+4hgBjAacAHxb/uhQdCzkCkQLX5rkSwD lnTt+koLEDtNA1+wcUnAP4bc3rPcg+b79xz1J31zrUX/MleyXW7LfNmEvFWY5w8qY+1f9RWgswj oMgTybw/sp3scsHQUdExkHlzCrE8Lqx1eQN90wqrSSqCIjV5AHSyGTEE2BS457GpeLbRmeTVFUr 99XXQ5YdUoJkAnvOajcDX3A8eZMOgp4wN4OKFR6MMcdi+0b2dJ18WZKgABdj6SAzHtGhk1VTKE9 Ojfv/sgiaAErcz6BPAbyv+1BB4O7rjCo0qvu1JyjOV5a6raWOELd06sp+z5O0XKXf1vYylJA2RB 84XRleuOjXmJXLgjgWrIpbI7n4DM4yR7ZSpGlpMr9e09hsvrddmtQVbVSBlWU/jMrWU78oRfVRU Ff8859+BAj/g== X-Google-Smtp-Source: AGHT+IGCwBqKOYm16KITns4JMIF/GhzMF8ZAIPJUUGu+bAhbne3snjAJ0zgzkhQUvh9vZYCwT0Mfkw== X-Received: by 2002:a05:6a20:4327:b0:23d:35f2:4e69 with SMTP id adf61e73a8af0-23d70151064mr20143935637.23.1753726627185; Mon, 28 Jul 2025 11:17:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mjt@tls.msk.ru, Peter Maydell , qemu-stable@nongnu.org, Pierrick Bouvier Subject: [PATCH 9/9] linux-user/aarch64: Support TPIDR2_MAGIC signal frame record Date: Mon, 28 Jul 2025 08:16:50 -1000 Message-ID: <20250728181650.165114-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250728181650.165114-1-richard.henderson@linaro.org> References: <20250728181650.165114-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753727180115116600 Content-Type: text/plain; charset="utf-8" From: Peter Maydell FEAT_SME adds the TPIDR2 userspace-accessible system register, which is used as part of the procedure calling standard's lazy saving scheme for the ZA registers: https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#66the= -za-lazy-saving-scheme The Linux kernel has a signal frame record for saving and restoring this value when calling signal handlers, but we forgot to implement this. The result is that code which tries to unwind an exception out of a signal handler will not work correctly. Add support for the missing record. Cc: qemu-stable@nongnu.org Fixes: 78011586b90d1 ("target/arm: Enable SME for user-only") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250725175510.3864231-3-peter.maydell@linaro.org> (cherry picked from commit 99870aff907b1c863cd32558b543f0ab0d0e74ba) --- linux-user/aarch64/signal.c | 42 +++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 85cb25ae91..34168c967a 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -120,6 +120,13 @@ struct target_za_context { #define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) =20 +#define TARGET_TPIDR2_MAGIC 0x54504902 + +struct target_tpidr2_context { + struct target_aarch64_ctx head; + uint64_t tpidr2; +}; + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -252,6 +259,14 @@ static void target_setup_za_record(struct target_za_co= ntext *za, } } =20 +static void target_setup_tpidr2_record(struct target_tpidr2_context *tpidr= 2, + CPUARMState *env) +{ + __put_user(TARGET_TPIDR2_MAGIC, &tpidr2->head.magic); + __put_user(sizeof(struct target_tpidr2_context), &tpidr2->head.size); + __put_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -402,6 +417,12 @@ static bool target_restore_za_record(CPUARMState *env, return true; } =20 +static void target_restore_tpidr2_record(CPUARMState *env, + struct target_tpidr2_context *tpi= dr2) +{ + __get_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -409,6 +430,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_fpsimd_context *fpsimd =3D NULL; struct target_sve_context *sve =3D NULL; struct target_za_context *za =3D NULL; + struct target_tpidr2_context *tpidr2 =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; @@ -459,6 +481,14 @@ static int target_restore_sigframe(CPUARMState *env, za_size =3D size; break; =20 + case TARGET_TPIDR2_MAGIC: + if (tpidr2 || size !=3D sizeof(struct target_tpidr2_context) || + !cpu_isar_feature(aa64_sme, env_archcpu(env))) { + goto err; + } + tpidr2 =3D (struct target_tpidr2_context *)ctx; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -496,6 +526,9 @@ static int target_restore_sigframe(CPUARMState *env, if (za && !target_restore_za_record(env, za, za_size, &svcr)) { goto err; } + if (tpidr2) { + target_restore_tpidr2_record(env, tpidr2); + } if (env->svcr !=3D svcr) { env->svcr =3D svcr; arm_rebuild_hflags(env); @@ -567,8 +600,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, .total_size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0; - int sve_size =3D 0, za_size =3D 0; + int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -584,6 +617,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, sve_ofs =3D alloc_sigframe_space(sve_size, &layout); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + tpidr2_size =3D sizeof(struct target_tpidr2_context); + tpidr2_ofs =3D alloc_sigframe_space(tpidr2_size, &layout); /* ZA state needs saving only if it is enabled. */ if (FIELD_EX64(env->svcr, SVCR, ZA)) { za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env)); @@ -643,6 +678,9 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, if (za_ofs) { target_setup_za_record((void *)frame + za_ofs, env, za_size); } + if (tpidr2_ofs) { + target_setup_tpidr2_record((void *)frame + tpidr2_ofs, env); + } =20 /* Set up the stack frame for unwinding. */ fr =3D (void *)frame + fr_ofs; --=20 2.43.0