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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 01/13] hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU Date: Mon, 28 Jul 2025 15:41:02 +0200 Message-Id: <20250728134114.77545-2-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: DlD8bujUAqPAVRAo3ArRiyJMxufGe4r3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX6xg9GT7/c7fr zqp0bhqsKa+cE9HorY1FOT+NzlLbuRYISeCrvpizFB271peX86o6Z+FXsAjDCDDTta+BhzpnltW i83SOgufz6bIqlBy6xG54boY3eSu7S5TjugF77oRTrP36PZPBPKBDfZbKsMMH4LdGMtpJqZ7fSM IQ3cnWX0/MTt8svMfy1TnWvcDbXuEtYmsViph4r9LW37g34gEa3ON6/0rz9Inn9QTp/oJwiz74K hP5GqEAt3+XjJlOJucP/Qm5iSWswPtMzpkgUZK+wKstgM4A2kzB3eT/Uv6pS2vSdzk9nsbgVU= X-Proofpoint-ORIG-GUID: DlD8bujUAqPAVRAo3ArRiyJMxufGe4r3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 phishscore=0 spamscore=0 mlxlogscore=986 adultscore=0 mlxscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.83; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710402353116600 Content-Type: text/plain; charset="utf-8" Creating a vCPU locks out APIs such as hv_gic_create(). As a result, switch to using the hv_vcpu_config_get_feature_reg interface. Hardcode MIDR because Apple deliberately doesn't expose a divergent MIDR ac= ross systems. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 47b0cd3a35..5ee0df17e3 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -864,24 +864,24 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) { ARMISARegisters host_isar =3D {}; const struct isar_regs { - int reg; + hv_feature_reg_t reg; uint64_t *val; } regs[] =3D { - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, + { HV_FEATURE_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_= EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_= EL1_IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_= IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_= EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_= EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_= EL1_IDX] }, /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; - hv_vcpu_t fd; + hv_return_t r =3D HV_SUCCESS; - hv_vcpu_exit_t *exit; + hv_vcpu_config_t hv_vcpu_config =3D hv_vcpu_config_create(); int i; =20 ahcf->dtb_compatible =3D "arm,armv8"; @@ -891,17 +891,10 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) (1ULL << ARM_FEATURE_PMU) | (1ULL << ARM_FEATURE_GENERIC_TIMER); =20 - /* We set up a small vcpu to extract host registers */ - - if (hv_vcpu_create(&fd, &exit, NULL) !=3D HV_SUCCESS) { - return false; - } - for (i =3D 0; i < ARRAY_SIZE(regs); i++) { - r |=3D hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); + r |=3D hv_vcpu_config_get_feature_reg(hv_vcpu_config, regs[i].reg,= regs[i].val); } - r |=3D hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); - r |=3D hv_vcpu_destroy(fd); + ahcf->midr =3D 0x610f0000; =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 --=20 2.39.5 (Apple Git-154)