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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 01/13] hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU Date: Mon, 28 Jul 2025 15:41:02 +0200 Message-Id: <20250728134114.77545-2-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: DlD8bujUAqPAVRAo3ArRiyJMxufGe4r3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX6xg9GT7/c7fr zqp0bhqsKa+cE9HorY1FOT+NzlLbuRYISeCrvpizFB271peX86o6Z+FXsAjDCDDTta+BhzpnltW i83SOgufz6bIqlBy6xG54boY3eSu7S5TjugF77oRTrP36PZPBPKBDfZbKsMMH4LdGMtpJqZ7fSM IQ3cnWX0/MTt8svMfy1TnWvcDbXuEtYmsViph4r9LW37g34gEa3ON6/0rz9Inn9QTp/oJwiz74K hP5GqEAt3+XjJlOJucP/Qm5iSWswPtMzpkgUZK+wKstgM4A2kzB3eT/Uv6pS2vSdzk9nsbgVU= X-Proofpoint-ORIG-GUID: DlD8bujUAqPAVRAo3ArRiyJMxufGe4r3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 phishscore=0 spamscore=0 mlxlogscore=986 adultscore=0 mlxscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.83; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710402353116600 Content-Type: text/plain; charset="utf-8" Creating a vCPU locks out APIs such as hv_gic_create(). As a result, switch to using the hv_vcpu_config_get_feature_reg interface. Hardcode MIDR because Apple deliberately doesn't expose a divergent MIDR ac= ross systems. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 47b0cd3a35..5ee0df17e3 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -864,24 +864,24 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) { ARMISARegisters host_isar =3D {}; const struct isar_regs { - int reg; + hv_feature_reg_t reg; uint64_t *val; } regs[] =3D { - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, + { HV_FEATURE_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL= 1_IDX] }, + { HV_FEATURE_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_= EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_= EL1_IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_= IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_= EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_= EL1_IDX] }, + { HV_FEATURE_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_= EL1_IDX] }, /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; - hv_vcpu_t fd; + hv_return_t r =3D HV_SUCCESS; - hv_vcpu_exit_t *exit; + hv_vcpu_config_t hv_vcpu_config =3D hv_vcpu_config_create(); int i; =20 ahcf->dtb_compatible =3D "arm,armv8"; @@ -891,17 +891,10 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) (1ULL << ARM_FEATURE_PMU) | (1ULL << ARM_FEATURE_GENERIC_TIMER); =20 - /* We set up a small vcpu to extract host registers */ - - if (hv_vcpu_create(&fd, &exit, NULL) !=3D HV_SUCCESS) { - return false; - } - for (i =3D 0; i < ARRAY_SIZE(regs); i++) { - r |=3D hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); + r |=3D hv_vcpu_config_get_feature_reg(hv_vcpu_config, regs[i].reg,= regs[i].val); } - r |=3D hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); - r |=3D hv_vcpu_destroy(fd); + ahcf->midr =3D 0x610f0000; =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 02/13] accel, hw/arm, include/system/hvf: infrastructure changes for HVF vGIC Date: Mon, 28 Jul 2025 15:41:03 +0200 Message-Id: <20250728134114.77545-3-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: VrPSHydl8gVL1U6WCxXCAtQZhPtjxuH8 X-Proofpoint-GUID: VrPSHydl8gVL1U6WCxXCAtQZhPtjxuH8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfXxABIGEFBtH8t ADFBzVgbHsE4OBC7zddJl/h5K3sTxNFJnoplcrTXbN/6KOcjPuLROIQm+O3qm6hfNVuHcbG8NLF a6OMGJfdedDBB837wjRWoPUQvXU/8FMwnwIYGdCuCE/0V3V0WdQ2NuVW+0TQa7+qXkLDOA4+QqN Hs4V6vk+zzotbzrX7SGEOgXxWcBDXAtfrTQFKfx8mc8rUlukQxguNILdYar1bQdo4k6C38PCv6r +n7MioJLQCKXBEHbX+DRsCug/jaMNO9XA7BDP6UKJTqIVUkjlXNljaf9SZ9bpUY6gEmS9jFXw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 clxscore=1030 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.236; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710242774116600 Content-Type: text/plain; charset="utf-8" Misc changes needed for HVF vGIC enablement. Signed-off-by: Mohamed Mediouni --- accel/hvf/hvf-all.c | 44 ++++++++++++++++++++++++++++++++++++++ accel/stubs/hvf-stub.c | 1 + hw/arm/virt.c | 16 +++++++++----- hw/intc/arm_gicv3_common.c | 3 +++ include/system/hvf.h | 3 +++ system/vl.c | 2 ++ 6 files changed, 64 insertions(+), 5 deletions(-) diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index 0a4b498e83..5af76ba7a6 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -10,6 +10,8 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-common.h" #include "accel/accel-ops.h" #include "system/address-spaces.h" #include "system/memory.h" @@ -20,6 +22,7 @@ #include "trace.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; =20 struct mac_slot { int present; @@ -290,6 +293,41 @@ static int hvf_gdbstub_sstep_flags(AccelState *as) return SSTEP_ENABLE | SSTEP_NOIRQ; } =20 +static void hvf_set_kernel_irqchip(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ +#ifdef __aarch64__ + OnOffSplit mode; + if (!visit_type_OnOffSplit(v, name, &mode, errp)) { + return; + } + + switch (mode) { + case ON_OFF_SPLIT_ON: + hvf_kernel_irqchip =3D true; + break; + + case ON_OFF_SPLIT_OFF: + hvf_kernel_irqchip =3D false; + break; + + case ON_OFF_SPLIT_SPLIT: + error_setg(errp, "HVF: split irqchip is not supported on Arm."); + break; + + default: + /* + * The value was checked in visit_type_OnOffSplit() above. If + * we get here, then something is wrong in QEMU. + */ + abort(); + } +#else + error_setg(errp, "HVF: setting irqchip configuration not supported on = x86_64."); +#endif +} + static void hvf_accel_class_init(ObjectClass *oc, const void *data) { AccelClass *ac =3D ACCEL_CLASS(oc); @@ -297,6 +335,12 @@ static void hvf_accel_class_init(ObjectClass *oc, cons= t void *data) ac->init_machine =3D hvf_accel_init; ac->allowed =3D &hvf_allowed; ac->gdbstub_supported_sstep_flags =3D hvf_gdbstub_sstep_flags; + hvf_kernel_irqchip =3D true; + object_class_property_add(oc, "kernel-irqchip", "on|off|split", + NULL, hvf_set_kernel_irqchip, + NULL, NULL); + object_class_property_set_description(oc, "kernel-irqchip", + "Configure HVF irqchip"); } =20 static const TypeInfo hvf_accel_type =3D { diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c index 42eadc5ca9..6bd08759ba 100644 --- a/accel/stubs/hvf-stub.c +++ b/accel/stubs/hvf-stub.c @@ -10,3 +10,4 @@ #include "system/hvf.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ef6be3660f..7da1176cda 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -830,7 +830,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 @@ -853,8 +853,9 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count); =20 - if (!kvm_irqchip_in_kernel()) { - if (vms->tcg_its) { + if (!kvm_irqchip_in_kernel() && + !(hvf_enabled() && hvf_irqchip_in_kernel())) { + if (vms->its && vms->tcg_its) { object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem), &error_fatal); qdev_prop_set_bit(vms->gic, "has-lpi", true); @@ -864,7 +865,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) ARCH_GIC_MAINT_IRQ); } } else { - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->virt); } @@ -2058,7 +2059,12 @@ static void finalize_gic_version(VirtMachineState *v= ms) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; - } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { + } else if (hvf_enabled()) { + if (!hvf_irqchip_in_kernel()) { + gics_supported |=3D VIRT_GIC_VERSION_2_MASK; + } + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; + } else if (tcg_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { gics_supported |=3D VIRT_GIC_VERSION_3_MASK; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index e438d8c042..b8eee27260 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/hvf.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -662,6 +663,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (hvf_enabled() && hvf_irqchip_in_kernel()) { + return "hvf-arm-gicv3"; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/include/system/hvf.h b/include/system/hvf.h index d3dcf088b3..dc8da85979 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -26,8 +26,11 @@ #ifdef CONFIG_HVF_IS_POSSIBLE extern bool hvf_allowed; #define hvf_enabled() (hvf_allowed) +extern bool hvf_kernel_irqchip; +#define hvf_irqchip_in_kernel() (hvf_kernel_irqchip) #else /* !CONFIG_HVF_IS_POSSIBLE */ #define hvf_enabled() 0 +#define hvf_irqchip_in_kernel() 0 #endif /* !CONFIG_HVF_IS_POSSIBLE */ =20 #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf") diff --git a/system/vl.c b/system/vl.c index 3b7057e6c6..1c072d15a4 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1773,6 +1773,8 @@ static void qemu_apply_legacy_machine_options(QDict *= qdict) false); object_register_sugar_prop(ACCEL_CLASS_NAME("whpx"), "kernel-irqch= ip", value, false); + object_register_sugar_prop(ACCEL_CLASS_NAME("hvf"), "kernel-irqchi= p", value, + false); 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 03/13] hw/intc: Add hvf vGIC interrupt controller support Date: Mon, 28 Jul 2025 15:41:04 +0200 Message-Id: <20250728134114.77545-4-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: KKWb1oxwh8ZlBQAc7Vy8i7Rfa-6S1wRJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX6vF5lkDhcE07 j+kYFuovkM7YCTw+WG4daRr0d865GOtj9jVdQufIfxmbYSOuqu3mC03OLyM+v5nwJXtADR5bvo/ c61udX0odl4nTeW7vViQAL3cqZS/K1re6meNxeFlOLy7MF9MoMSP9QUPmsTRLeehzYJVFUUvFJX 4aVtU6h3qAs4O/ehYJUidUe5bxoxHemnZuJjIl5oJFzCufOp8FcYZd06ZYghrpn/dmT7rJj9NWo ti2lSp3hBV10HL72JQxQ/5Ex1RWi3FBvfWD0L4fZqcpve2eU6AV3Ae/vkZF2gc9vt/TjL4UxY= X-Proofpoint-ORIG-GUID: KKWb1oxwh8ZlBQAc7Vy8i7Rfa-6S1wRJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 adultscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 suspectscore=0 clxscore=1030 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.151; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710500091116600 Content-Type: text/plain; charset="utf-8" This opens up the door to nested virtualisation support. Signed-off-by: Mohamed Mediouni --- hw/intc/arm_gicv3_hvf.c | 722 ++++++++++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + 2 files changed, 723 insertions(+) create mode 100644 hw/intc/arm_gicv3_hvf.c diff --git a/hw/intc/arm_gicv3_hvf.c b/hw/intc/arm_gicv3_hvf.c new file mode 100644 index 0000000000..1e9662230d --- /dev/null +++ b/hw/intc/arm_gicv3_hvf.c @@ -0,0 +1,722 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller using HVF platform support + * + * Copyright (c) 2025 Mohamed Mediouni + * Based on vGICv3 KVM code by Pavel Fedin + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "system/runstate.h" +#include "system/hvf.h" +#include "system/hvf_int.h" +#include "hvf_arm.h" +#include "gicv3_internal.h" +#include "vgic_common.h" +#include "qom/object.h" +#include "target/arm/cpregs.h" +#include + +struct HVFARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#define TYPE_HVF_GICV3 "hvf-arm-gicv3" +typedef struct HVFARMGICv3Class HVFARMGICv3Class; + +/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ +DECLARE_OBJ_CHECKERS(GICv3State, HVFARMGICv3Class, + HVF_GICV3, TYPE_HVF_GICV3); + +/* + * Loop through each distributor IRQ related register; since bits + * corresponding to SPIs and PPIs are RAZ/WI when affinity routing + * is enabled, we skip those. + */ +#define for_each_dist_irq_reg(_irq, _max, _field_width) \ + for (_irq =3D GIC_INTERNAL; _irq < _max; _irq +=3D (32 / _field_width)) + +static void hvf_dist_get_priority(GICv3State *s, hv_gic_distributor_reg_t = offset + , uint8_t *bmp) +{ + uint64_t reg; + uint32_t *field; + int irq; + field =3D (uint32_t *)(bmp); + + for_each_dist_irq_reg(irq, s->num_irq, 8) { + hv_gic_get_distributor_reg(offset, ®); + *field =3D reg; + offset +=3D 4; + field++; + } +} + +static void hvf_dist_put_priority(GICv3State *s, hv_gic_distributor_reg_t = offset + , uint8_t *bmp) +{ + uint32_t reg, *field; + int irq; + field =3D (uint32_t *)(bmp); + + for_each_dist_irq_reg(irq, s->num_irq, 8) { + reg =3D *field; + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + field++; + } +} + +static void hvf_dist_get_edge_trigger(GICv3State *s, hv_gic_distributor_re= g_t offset, + uint32_t *bmp) +{ + uint64_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 2) { + hv_gic_get_distributor_reg(offset, ®); + reg =3D half_unshuffle32(reg >> 1); + if (irq % 32 !=3D 0) { + reg =3D (reg << 16); + } + *gic_bmp_ptr32(bmp, irq) |=3D reg; + offset +=3D 4; + } +} + +static void hvf_dist_put_edge_trigger(GICv3State *s, hv_gic_distributor_re= g_t offset, + uint32_t *bmp) +{ + uint32_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 2) { + reg =3D *gic_bmp_ptr32(bmp, irq); + if (irq % 32 !=3D 0) { + reg =3D (reg & 0xffff0000) >> 16; + } else { + reg =3D reg & 0xffff; + } + reg =3D half_shuffle32(reg) << 1; + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + } +} + +/* Read a bitmap register group from the kernel VGIC. */ +static void hvf_dist_getbmp(GICv3State *s, hv_gic_distributor_reg_t offset= , uint32_t *bmp) +{ + uint64_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 1) { + + hv_gic_get_distributor_reg(offset, ®); + *gic_bmp_ptr32(bmp, irq) =3D reg; + offset +=3D 4; + } +} + +static void hvf_dist_putbmp(GICv3State *s, hv_gic_distributor_reg_t offset, + hv_gic_distributor_reg_t clroffset, uint32_t *= bmp) +{ + uint32_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 1) { + /* + * If this bitmap is a set/clear register pair, first write to the + * clear-reg to clear all bits before using the set-reg to write + * the 1 bits. + */ + if (clroffset !=3D 0) { + reg =3D 0; + hv_gic_set_distributor_reg(clroffset, reg); + clroffset +=3D 4; + } + reg =3D *gic_bmp_ptr32(bmp, irq); + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + } +} + +static void hvf_gicv3_check(GICv3State *s) +{ + uint64_t reg; + uint32_t num_irq; + + /* Sanity checking s->num_irq */ + hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_TYPER, ®); + num_irq =3D ((reg & 0x1f) + 1) * 32; + + if (num_irq < s->num_irq) { + error_report("Model requests %u IRQs, but HVF supports max %u", + s->num_irq, num_irq); + abort(); + } +} + +static void hvf_gicv3_put_cpu(CPUState *cpu_state, run_on_cpu_data arg) +{ + uint32_t reg; + uint64_t reg64; + int i, num_pri_bits; + + /* Redistributor state */ + GICv3CPUState *c =3D arg.host_ptr; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + + reg =3D c->gicr_waker; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROU= PR0, reg); + + reg =3D c->gicr_igroupr0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROU= PR0, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICENA= BLER0, reg); + reg =3D c->gicr_ienabler0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISENA= BLER0, reg); + + /* Restore config before pending so we treat level/edge correctly */ + reg =3D half_shuffle32(c->edge_trigger >> 16) << 1; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICFGR= 1, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICPEN= DR0, reg); + reg =3D c->gicr_ipendr0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISPEN= DR0, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICACT= IVER0, reg); + reg =3D c->gicr_iactiver0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISACT= IVER0, reg); + + for (i =3D 0; i < GIC_INTERNAL; i +=3D 4) { + reg =3D c->gicr_ipriorityr[i] | + (c->gicr_ipriorityr[i + 1] << 8) | + (c->gicr_ipriorityr[i + 2] << 16) | + (c->gicr_ipriorityr[i + 3] << 24); + hv_gic_set_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, reg); + } + + /* CPU interface state */ + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, c->icc_sre_el1); + + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1, + c->icc_ctlr_el1[GICV3_NS]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1, + c->icc_igrpen[GICV3_G0]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1, + c->icc_igrpen[GICV3_G1NS]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1, c->icc_pmr_el1); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1, c->icc_bpr[GICV3_G0]= ); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1, c->icc_bpr[GICV3_G1N= S]); + + num_pri_bits =3D ((c->icc_ctlr_el1[GICV3_NS] & + ICC_CTLR_EL1_PRIBITS_MASK) >> + ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; + + switch (num_pri_bits) { + case 7: + reg64 =3D c->icc_apr[GICV3_G0][3]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3, reg64); + reg64 =3D c->icc_apr[GICV3_G0][2]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2, reg64); + /* fall through */ + case 6: + reg64 =3D c->icc_apr[GICV3_G0][1]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1, reg64); + /* fall through */ + default: + reg64 =3D c->icc_apr[GICV3_G0][0]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1, reg64); + } + + switch (num_pri_bits) { + case 7: + reg64 =3D c->icc_apr[GICV3_G1NS][3]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3, reg64); + reg64 =3D c->icc_apr[GICV3_G1NS][2]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2, reg64); + /* fall through */ + case 6: + reg64 =3D c->icc_apr[GICV3_G1NS][1]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1, reg64); + /* fall through */ + default: + reg64 =3D c->icc_apr[GICV3_G1NS][0]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, reg64); + } + + if (!hvf_arm_el2_enabled()) { + return; + } + + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, c->ich_vmcr_el2); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, c->ich_hcr_el2); + + for (int i =3D 0; i < GICV3_LR_MAX; i++) { + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, c->ich_lr_el2[i]); + } + + num_pri_bits =3D c->vpribits; + + switch (num_pri_bits) { + case 7: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3, + c->ich_apr[GICV3_G0][3]); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2, + c->ich_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1, + c->ich_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2, + c->ich_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3, + c->ich_apr[GICV3_G1NS][3]); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2, + c->ich_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1, + c->ich_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2, + c->ich_apr[GICV3_G1NS][0]); + } +} + +static void hvf_gicv3_put(GICv3State *s) +{ + uint32_t reg; + uint64_t redist_typer; + int ncpu, i; + + hvf_gicv3_check(s); + + hv_vcpu_t vcpu0 =3D s->cpu[0].cpu->accel->fd; + hv_gic_get_redistributor_reg(vcpu0, HV_GIC_REDISTRIBUTOR_REG_GICR_TYPER + , &redist_typer); + + reg =3D s->gicd_ctlr; + hv_gic_set_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, reg); + + if (redist_typer & GICR_TYPER_PLPIS) { + error_report("ITS is not supported on HVF."); + abort(); + } + + /* per-CPU state */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + run_on_cpu_data data; + data.host_ptr =3D &s->cpu[ncpu]; + run_on_cpu(s->cpu[ncpu].cpu, hvf_gicv3_put_cpu, data); + } + + /* s->enable bitmap -> GICD_ISENABLERn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0 + , HV_GIC_DISTRIBUTOR_REG_GICD_ICENABLER0, s->enabled); + + /* s->group bitmap -> GICD_IGROUPRn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0 + , 0, s->group); + + /* Restore targets before pending to ensure the pending state is set on + * the appropriate CPU interfaces in the kernel + */ + + /* s->gicd_irouter[irq] -> GICD_IROUTERn */ + for (i =3D GIC_INTERNAL; i < s->num_irq; i++) { + uint32_t offset =3D HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32 + (8 * i) + - (8 * GIC_INTERNAL); + hv_gic_set_distributor_reg(offset, s->gicd_irouter[i]); + } + + /* + * s->trigger bitmap -> GICD_ICFGRn + * (restore configuration registers before pending IRQs so we treat + * level/edge correctly) + */ + hvf_dist_put_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0, s->ed= ge_trigger); + + /* s->pending bitmap -> GICD_ISPENDRn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0, + HV_GIC_DISTRIBUTOR_REG_GICD_ICPENDR0, s->pending); + + /* s->active bitmap -> GICD_ISACTIVERn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0, + HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0, s->active); + + /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ + hvf_dist_put_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0, s->g= icd_ipriority); +} + +static void hvf_gicv3_get_cpu(CPUState *cpu_state, run_on_cpu_data arg) +{ + uint64_t reg; + int i, num_pri_bits; + + /* Redistributor state */ + GICv3CPUState *c =3D arg.host_ptr; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + + hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROU= PR0, + ®); + c->gicr_igroupr0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISENA= BLER0, + ®); + c->gicr_ienabler0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICFGR= 1, + ®); + c->edge_trigger =3D half_unshuffle32(reg >> 1) << 16; + hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISPEN= DR0, + ®); + c->gicr_ipendr0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISACT= IVER0, + ®); + c->gicr_iactiver0 =3D reg; + + for (i =3D 0; i < GIC_INTERNAL; i +=3D 4) { + hv_gic_get_redistributor_reg( + vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, ®); + c->gicr_ipriorityr[i] =3D extract32(reg, 0, 8); + c->gicr_ipriorityr[i + 1] =3D extract32(reg, 8, 8); + c->gicr_ipriorityr[i + 2] =3D extract32(reg, 16, 8); + c->gicr_ipriorityr[i + 3] =3D extract32(reg, 24, 8); + } + + /* CPU interface */ + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, &c->icc_sre_el1); + + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1, + &c->icc_ctlr_el1[GICV3_NS]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1, + &c->icc_igrpen[GICV3_G0]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1, + &c->icc_igrpen[GICV3_G1NS]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1, &c->icc_pmr_el1); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1, &c->icc_bpr[GICV3_G0= ]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1, &c->icc_bpr[GICV3_G1= NS]); + num_pri_bits =3D ((c->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_PRIBITS_MA= SK) >> + ICC_CTLR_EL1_PRIBITS_SHIFT) + + 1; + + switch (num_pri_bits) { + case 7: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3, + &c->icc_apr[GICV3_G0][3]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2, + &c->icc_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1, + &c->icc_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1, + &c->icc_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3, + &c->icc_apr[GICV3_G1NS][3]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2, + &c->icc_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1, + &c->icc_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, + &c->icc_apr[GICV3_G1NS][0]); + } + + /* Registers beyond this are with nested virt only */ + if (!hvf_arm_el2_enabled()) { + return; + } + + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, &c->ich_vmcr_el2); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, &c->ich_hcr_el2); + + for (int i =3D 0; i < GICV3_LR_MAX; i++) { + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, &c->ich_lr_el2[i]= ); + } + + num_pri_bits =3D c->vpribits; + + switch (num_pri_bits) { + case 7: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3, + &c->ich_apr[GICV3_G0][3]); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2, + &c->ich_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1, + &c->ich_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2, + &c->ich_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3, + &c->ich_apr[GICV3_G1NS][3]); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2, + &c->ich_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1, + &c->ich_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2, + &c->ich_apr[GICV3_G1NS][0]); + } +} + +static void hvf_gicv3_get(GICv3State *s) +{ + uint64_t reg, redist_typer; + int ncpu, i; + + hvf_gicv3_check(s); + + hv_vcpu_t vcpu0 =3D s->cpu[0].cpu->accel->fd; + hv_gic_get_redistributor_reg(vcpu0, + HV_GIC_REDISTRIBUTOR_REG_GICR_TYPER, &redist_typer); + + hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, ®); + s->gicd_ctlr =3D reg; + + /* Redistributor state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + run_on_cpu_data data; + data.host_ptr =3D &s->cpu[ncpu]; + run_on_cpu(s->cpu[ncpu].cpu, hvf_gicv3_get_cpu, data); + } + + if (redist_typer & GICR_TYPER_PLPIS) { + error_report("ITS is not supported on HVF."); + abort(); + } + + /* GICD_IGROUPRn -> s->group bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0, s->group); + + /* GICD_ISENABLERn -> s->enabled bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0, s->enabled); + + /* GICD_ISPENDRn -> s->pending bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0, s->pending); + + /* GICD_ISACTIVERn -> s->active bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0, s->active); + + /* GICD_ICFGRn -> s->trigger bitmap */ + hvf_dist_get_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0 + , s->edge_trigger); + + /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ + hvf_dist_get_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0 + , s->gicd_ipriority); + + /* GICD_IROUTERn -> s->gicd_irouter[irq] */ + for (i =3D GIC_INTERNAL; i < s->num_irq; i++) { + uint32_t offset =3D HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32 + + (8 * i) - (8 * GIC_INTERNAL); + hv_gic_get_distributor_reg(offset, &s->gicd_irouter[i]); + } +} + +static void hvf_gicv3_set_irq(void *opaque, int irq, int level) +{ + GICv3State *s =3D (GICv3State *)opaque; + if (irq > s->num_irq) { + return; + } + hv_gic_set_spi(GIC_INTERNAL + irq, !!level); +} + +static void hvf_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3State *s; + GICv3CPUState *c; + + c =3D (GICv3CPUState *)env->gicv3state; + s =3D c->gic; + + c->icc_pmr_el1 =3D 0; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; + + c->icc_sre_el1 =3D 0x7; + memset(c->icc_apr, 0, sizeof(c->icc_apr)); + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); + + if (s->migration_blocker) { + return; + } + + /* Initialize to actual HW supported configuration */ + hv_gic_get_icc_reg(c->cpu->accel->fd, + HV_GIC_ICC_REG_CTLR_EL1, &c->icc_ctlr_el1[GICV3_NS]); + + c->icc_ctlr_el1[GICV3_S] =3D c->icc_ctlr_el1[GICV3_NS]; +} + +static void hvf_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + HVFARMGICv3Class *kgc =3D HVF_GICV3_GET_CLASS(s); + + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj, type); + } + + hvf_gicv3_put(s); +} + + +/* + * CPU interface registers of GIC needs to be reset on CPU reset. + * For the calling arm_gicv3_icc_reset() on CPU reset, we register + * below ARMCPRegInfo. As we reset the whole cpu interface under single + * register reset, we define only one register of CPU interface instead + * of defining all the registers. + */ +static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { + { .name =3D "ICC_CTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 4, + /* + * If ARM_CP_NOP is used, resetfn is not called, + * So ARM_CP_NO_RAW is appropriate type. + */ + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, + .readfn =3D arm_cp_read_zero, + .writefn =3D arm_cp_write_ignore, + /* + * We hang the whole cpu interface reset routine off here + * rather than parcelling it out into one little function + * per register + */ + .resetfn =3D hvf_gicv3_icc_reset, + }, +}; + +static void hvf_gicv3_realize(DeviceState *dev, Error **errp) +{ + GICv3State *s =3D HVF_GICV3(dev); + HVFARMGICv3Class *kgc =3D HVF_GICV3_GET_CLASS(s); + Error *local_err =3D NULL; + int i; + + kgc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by HVF"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, hvf_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); + + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + } + + if (s->maint_irq && s->maint_irq !=3D HV_GIC_INT_MAINTENANCE) { + error_setg(errp, "vGIC maintenance IRQ mismatch with the hardcoded= one in HVF."); + return; + } +} + +static void hvf_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + HVFARMGICv3Class *kgc =3D HVF_GICV3_CLASS(klass); + + agcc->pre_save =3D hvf_gicv3_get; + agcc->post_load =3D hvf_gicv3_put; + + device_class_set_parent_realize(dc, hvf_gicv3_realize, + &kgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, hvf_gicv3_reset_hold, NUL= L, + &kgc->parent_phases); +} + +static const TypeInfo hvf_arm_gicv3_info =3D { + .name =3D TYPE_HVF_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D hvf_gicv3_class_init, + .class_size =3D sizeof(HVFARMGICv3Class), +}; + +static void hvf_gicv3_register_types(void) +{ + type_register_static(&hvf_arm_gicv3_info); +} + +type_init(hvf_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3137521a4a..f446e966e3 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -42,6 +42,7 @@ specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('a= rm_gicv3_cpuif_common.c specific_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.= c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_true: files('= arm_gicv3_hvf.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 04/13] hw/arm, target/arm: nested virtualisation on HVF Date: Mon, 28 Jul 2025 15:41:05 +0200 Message-Id: <20250728134114.77545-5-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: hmJqNe0pQ8U2Vn9W8HMGn4NQKZjNURTK X-Proofpoint-ORIG-GUID: hmJqNe0pQ8U2Vn9W8HMGn4NQKZjNURTK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfXwKVI6URmPhdq ZrOsyxt4xqw7mmmVHxUMw2AHCGL6l69Cq8m8Kg4MHKs7X3/dHAb35woAVq2rJYtZg40BOvDusIv qfs8Yz83b0TqO7u7aYDTYjlg+oThZY1+HZmzOup2ztSp+55UAv0/R/O9Y588gruBoGNq4UCzWFf KUo6QTMB+qxgdFAv3fdIs8HRuCdsuo5eJTyZXa8owuKazrz3WHiqcR7M0TWvJD4xPV0gC/gRzm3 i4mlLOk5WU9eTpSwbJRSePyl0DEu7qbE+tH9fWVY6BM5Egq4FEbbFS+ImyIp5rX7sSJUv4BNM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1030 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.48; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710168092116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni --- hw/arm/virt.c | 9 ++++++--- target/arm/hvf-stub.c | 15 +++++++++++++++ target/arm/hvf/hvf.c | 41 +++++++++++++++++++++++++++++++++++++++-- target/arm/hvf_arm.h | 3 +++ 4 files changed, 63 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7da1176cda..7348d55104 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -817,8 +817,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) g_assert_not_reached(); } =20 - if (kvm_enabled() && vms->virt && - (revision !=3D 3 || !kvm_irqchip_in_kernel())) { + if (kvm_enabled() && vms->virt && (revision !=3D 3 || !kvm_irqchip_in_= kernel())) { error_report("KVM EL2 is only supported with in-kernel GICv3"); exit(1); } @@ -2279,7 +2278,8 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled())= { + if (vms->virt && !kvm_enabled() && !tcg_enabled() + && !hvf_enabled() && !qtest_enabled()) { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", current_accel_name()); @@ -2549,6 +2549,9 @@ static void virt_set_virt(Object *obj, bool value, Er= ror **errp) VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 vms->virt =3D value; +#if defined(CONFIG_HVF) && defined(__aarch64__) + hvf_arm_el2_enable(value); +#endif } =20 static bool virt_get_highmem(Object *obj, Error **errp) diff --git a/target/arm/hvf-stub.c b/target/arm/hvf-stub.c index ff137267a0..95ec4ea62f 100644 --- a/target/arm/hvf-stub.c +++ b/target/arm/hvf-stub.c @@ -18,3 +18,18 @@ uint32_t hvf_arm_get_max_ipa_bit_size(void) { g_assert_not_reached(); } + +bool hvf_arm_el2_supported(void) +{ + g_assert_not_reached(); +} + +bool hvf_arm_el2_enabled(void) +{ + g_assert_not_reached(); +} + +void hvf_arm_el2_enable(bool) +{ + g_assert_not_reached(); +} diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 5ee0df17e3..4ac42bda32 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -26,6 +26,7 @@ #include "system/address-spaces.h" #include "system/memory.h" #include "hw/boards.h" +#include "hw/arm/virt.h" #include "hw/irq.h" #include "qemu/main-loop.h" #include "system/cpus.h" @@ -891,6 +892,10 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) (1ULL << ARM_FEATURE_PMU) | (1ULL << ARM_FEATURE_GENERIC_TIMER); =20 + if (hvf_arm_el2_enabled()) { + ahcf->features |=3D 1ULL << ARM_FEATURE_EL2; + } + for (i =3D 0; i < ARRAY_SIZE(regs); i++) { r |=3D hv_vcpu_config_get_feature_reg(hv_vcpu_config, regs[i].reg,= regs[i].val); } @@ -957,6 +962,25 @@ uint32_t hvf_arm_get_max_ipa_bit_size(void) return round_down_to_parange_bit_size(max_ipa_size); } =20 +bool hvf_arm_el2_supported(void) +{ + bool is_nested_virt_supported; + hv_return_t ret =3D hv_vm_config_get_el2_supported(&is_nested_virt_sup= ported); + assert_hvf_ok(ret); + return is_nested_virt_supported; +} + +static bool is_nested_virt_enabled =3D false; +bool hvf_arm_el2_enabled(void) +{ + return is_nested_virt_enabled; +} + +void hvf_arm_el2_enable(bool enable) +{ + is_nested_virt_enabled =3D enable; +} + void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) { if (!arm_host_cpu_features.dtb_compatible) { @@ -993,6 +1017,13 @@ hv_return_t hvf_arch_vm_create(MachineState *ms, uint= 32_t pa_range) } chosen_ipa_bit_size =3D pa_range; =20 + if (hvf_arm_el2_enabled()) { + ret =3D hv_vm_config_set_el2_enabled(config, true); + if (ret !=3D HV_SUCCESS) { + goto cleanup; + } + } + ret =3D hv_vm_create(config); =20 cleanup: @@ -1100,6 +1131,13 @@ static void hvf_psci_cpu_off(ARMCPU *arm_cpu) assert(ret =3D=3D QEMU_ARM_POWERCTL_RET_SUCCESS); } =20 +static int hvf_psci_get_target_el(void) +{ + if (hvf_arm_el2_enabled()) { + return 2; + } + return 1; +} /* * Handle a PSCI call. * @@ -1121,7 +1159,6 @@ static bool hvf_handle_psci_call(CPUState *cpu) CPUState *target_cpu_state; ARMCPU *target_cpu; target_ulong entry; - int target_el =3D 1; int32_t ret =3D 0; =20 trace_hvf_psci_call(param[0], param[1], param[2], param[3], @@ -1175,7 +1212,7 @@ static bool hvf_handle_psci_call(CPUState *cpu) entry =3D param[2]; context_id =3D param[3]; ret =3D arm_set_cpu_on(mpidr, entry, context_id, - target_el, target_aarch64); + hvf_psci_get_target_el(), target_aarch64); break; case QEMU_PSCI_0_1_FN_CPU_OFF: case QEMU_PSCI_0_2_FN_CPU_OFF: diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea82f2691d..bf55e7ae28 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -24,5 +24,8 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 uint32_t hvf_arm_get_default_ipa_bit_size(void); uint32_t hvf_arm_get_max_ipa_bit_size(void); +bool hvf_arm_el2_supported(void); +bool hvf_arm_el2_enabled(void); +void hvf_arm_el2_enable(bool); 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 05/13] hvf: save/restore Apple GIC state Date: Mon, 28 Jul 2025 15:41:06 +0200 Message-Id: <20250728134114.77545-6-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX1/9G4goj5Z55 6a5qTEJVDJtNSge/9cLm8qy8rIc0aDQENwUGzJ4yxYlUER1HXN0UiLI53HCda+KiSbbG/Ttg38+ H3yk+wsfMHnISsn8kwzMyW7EyOG0oUI5ryFrgE0Xt2p5ssvdzORzSiGElATzsiK3M9yuC+rM3KU Cb7FVSPW9PPBiwHYih4c9aoctw/z1uPc7YboKgCwvs7V3D1GjG8NL6P1TmnuKh4pyAvSnsCIy2g 4ysR5Fv2SIniv10C+hlq8Att/qwBKjKmUXmNxkbBJC5YjguwPAoDN060CBR66Amx+qRzYOkPE= X-Proofpoint-GUID: HvT7R71efXJ-TgKqpbSyaKfkjTDjQolQ X-Proofpoint-ORIG-GUID: HvT7R71efXJ-TgKqpbSyaKfkjTDjQolQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 clxscore=1030 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 mlxlogscore=820 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.231; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710148282116600 Content-Type: text/plain; charset="utf-8" On HVF, some of the GIC state is in an opaque Apple-provided structure. Save/restore that state to be able to save/restore VMs. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 73 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 4ac42bda32..f14a3a3cbd 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -22,6 +22,7 @@ #include "cpu-sysregs.h" =20 #include +#include =20 #include "system/address-spaces.h" #include "system/memory.h" @@ -2174,15 +2175,83 @@ static const VMStateDescription vmstate_hvf_vtimer = =3D { }, }; =20 +/* Apple specific opaque state for the vGIC */ + +typedef struct HVGICState { + void *state; + uint32_t size; +} HVGICState; + +static HVGICState gic; + +static int hvf_gic_opaque_state_get(void) +{ + hv_gic_state_t gic_state; + hv_return_t err; + size_t size; + + gic_state =3D hv_gic_state_create(); + if (gic_state =3D=3D NULL) { + error_report("hvf: vgic: failed to create hv_gic_state_create."); + return 1; + } + err =3D hv_gic_state_get_size(gic_state, &size); + gic.size =3D size; + if (err !=3D HV_SUCCESS) { + error_report("hvf: vgic: failed to get GIC state size."); + return 1; + } + gic.state =3D malloc(gic.size); + err =3D hv_gic_state_get_data(gic_state, gic.state); + if (err !=3D HV_SUCCESS) { + error_report("hvf: vgic: failed to get GIC state."); + return 1; + } + return 0; +} + +static int hvf_gic_opaque_state_set(void) +{ + hv_return_t err; + if (!gic.size) { + return 0; + } + err =3D hv_gic_set_state(gic.state, gic.size); + if (err !=3D HV_SUCCESS) { + error_report("hvf: vgic: failed to restore GIC state."); + return 1; + } + return 0; +} + +static const VMStateDescription vmstate_hvf_gic =3D { + .name =3D "hvf-gic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(size, HVGICState), + VMSTATE_VBUFFER_UINT32(state, + HVGICState, 0, 0, + size), + VMSTATE_END_OF_LIST() + }, +}; + static void hvf_vm_state_change(void *opaque, bool running, RunState state) { HVFVTimer *s =3D opaque; =20 if (running) { + if (hvf_irqchip_in_kernel()) { + hvf_gic_opaque_state_set(); + } /* Update vtimer offset on all CPUs */ hvf_state->vtimer_offset =3D mach_absolute_time() - s->vtimer_val; cpu_synchronize_all_states(); } else { + if (hvf_irqchip_in_kernel()) { + hvf_gic_opaque_state_get(); + } /* Remember vtimer value on every pause */ s->vtimer_val =3D hvf_vtimer_val_raw(); } @@ -2192,6 +2261,10 @@ int hvf_arch_init(void) { hvf_state->vtimer_offset =3D mach_absolute_time(); vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); + if (hvf_irqchip_in_kernel()) { + gic.size =3D 0; + vmstate_register(NULL, 0, &vmstate_hvf_gic, &gic); + } qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); =20 hvf_arm_init_debug(); --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 06/13] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Date: Mon, 28 Jul 2025 15:41:07 +0200 Message-Id: <20250728134114.77545-7-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX1EN/VPEZY3uH TCtYN+dqcbrpYeTZBHA+5Pi8tKPVRf1EG447afdTmB70tNbmbzo6g2Ah58UJv+bVyfwHtioZP8Y nLoutllkpmBOFG4rjgx29Em5Ysn/dp5kG2U0lmrNaM5JIqEQDiHxMoChkCjl0NxCO1EK82hoOTP KntIpNHvYCdo6a98AG2r+9MzUQvgNpvhlQEkRUBmS+Fg5d37LIXalvr6dcIpoxTFlKrzDULPvEr YW7xO716m+/drAuo4YPFOy3taCTTBddeMFKszpmd9qIOKs+SAFyr0D0oUnZlDJkNtn/HJp7oU= X-Proofpoint-GUID: xM2gIMa7PrOQFPnzpAeKgNAlysrLsJxk X-Proofpoint-ORIG-GUID: xM2gIMa7PrOQFPnzpAeKgNAlysrLsJxk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=676 malwarescore=0 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1030 adultscore=0 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.157; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710616936116600 Content-Type: text/plain; charset="utf-8" HVF traps accesses to CNTHCTL_EL2. For nested guests, HVF traps accesses to= MDCCINT_EL1. Pass through those accesses to the Hypervisor.framework library. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f14a3a3cbd..eefae3069f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -297,6 +297,10 @@ void hvf_arm_init_debug(void) #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) =20 +/* EL2 registers */ +#define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0) +#define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0) + #define WFX_IS_WFE (1 << 0) =20 #define TMR_CTL_ENABLE (1 << 0) @@ -1372,6 +1376,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t r= eg, uint64_t *val) case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; + case SYSREG_CNTHCTL_EL2: + assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); + return 0; + case SYSREG_MDCCINT_EL1: + assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1689,6 +1699,12 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t = reg, uint64_t val) case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; + case SYSREG_CNTHCTL_EL2: + assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); + return 0; + case SYSREG_MDCCINT_EL1: + assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); + return 0; case SYSREG_LORC_EL1: /* Dummy register */ return 0; --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753710387; cv=none; d=zohomail.com; s=zohoarc; b=kNfnRfLX/J7CvW8NYZ8a1lozxiczTBx+Azk4IhTITQ+wuIf2Y+Hr2+TRyBm/32ew9I05ViTA/T3ZZ7AJvKsRRc6BuFzw+3RDIkMzcohz3QzPsH6oV/AtNGtrjbGpr7quZd8yTOnQq6OkmxYL8EsNlPyMOHkUcPSUmzRWLFXTOJg= ARC-Message-Signature: i=1; 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 07/13] hw/arm: virt: add GICv2m for the case when ITS is not available Date: Mon, 28 Jul 2025 15:41:08 +0200 Message-Id: <20250728134114.77545-8-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: C837ey0UgWhrqOKHVNXjJbUR2ew6xm3o X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX1L3O3WcCk1dR aZY0OWLcozmSz5Ce2OltwwPXaLVNsU3tlQeRFp4kNabOQGp2pvQYv/ljg1ZKOKefrj4uBaPv8AJ pIcS0zFkd6yp3KtIRjeHhPrF60I+01MmVyNZiwTcIIiEq7hXCM+zXMTkCimNDNfZ23hwXxdOv/u 2avrBn6rKItf7yZ1IUlb1Q1F5XY0PTNBqUNvEF+dC3O9MzsrnmkUuusEp0wVwkEBzyRqShcG/QM +QrY+Sfa4TTMi3kQLo9UPUPL5TIioOMfWUt/hfLHb0NbF/ZKqM4NmCJwWLI3i+sB1/K+luKDQ= X-Proofpoint-GUID: C837ey0UgWhrqOKHVNXjJbUR2ew6xm3o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1030 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.84.4; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710388678116600 Content-Type: text/plain; charset="utf-8" On Hypervisor.framework for macOS and WHPX for Windows, the provided enviro= nment is a GICv3 without ITS. As such, support a GICv3 w/ GICv2m for that scenario. Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 4 +++- hw/arm/virt.c | 8 ++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b01fc4f8ef..969fa3f686 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -848,7 +848,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } - } else { + } + + if (!vms->its && !vms->no_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7348d55104..91d8cd9363 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -953,6 +953,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { create_its(vms); + } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { + create_v2m(vms); } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { create_v2m(vms); } @@ -2408,6 +2410,8 @@ static void machvirt_init(MachineState *machine) vms->ns_el2_virt_timer_irq =3D ns_el2_virt_timer_present() && !vmc->no_ns_el2_virt_timer_irq; =20 + vms->no_gicv3_with_gicv2m =3D vmc->no_gicv3_with_gicv2m; + fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); =20 @@ -3419,6 +3423,7 @@ static void virt_instance_init(Object *obj) vms->its =3D true; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; + vms->no_gicv3_with_gicv2m =3D false; =20 /* Default disallows iommu instantiation */ vms->iommu =3D VIRT_IOMMU_NONE; @@ -3471,8 +3476,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(10, 1) =20 static void virt_machine_10_0_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_10_1_options(mc); compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len); + vmc->no_gicv3_with_gicv2m =3D true; } DEFINE_VIRT_MACHINE(10, 0) =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 365a28b082..725ec18fd2 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -131,6 +131,7 @@ struct VirtMachineClass { bool no_cpu_topology; bool no_tcg_lpa2; bool no_ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; bool no_nested_smmu; }; =20 @@ -178,6 +179,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; CXLState cxl_devices_state; }; =20 --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753710272; cv=none; d=zohomail.com; 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 08/13] hw/arm: virt: cleanly fail on attempt to use the platform vGIC together with ITS Date: Mon, 28 Jul 2025 15:41:09 +0200 Message-Id: <20250728134114.77545-9-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfXwwUaBYlV/YvV PTvo4RJqI2f/WpoYVYyBxJGZAk/ujktDzbDt26VoR8c5xNmFWiB0tv2qhiXkfn5XzbPEhYoeETk C+ApqdOOnZSXJv9mBSetC3HGOhZTR15z5lDYiN9uClfdPRIqJuZZNYPKD/X9/MmyykVAnfNarzz d6MqaQ1xQHXZkKxmt/zG04hRfpGBatYwuANTBG9TFjNmC8Q4QhXpptstmquflLLyeVWrL8XQlus UkD79V5Xscim8KRiFVyTYhNbsfM7yXHaOgCszDahUti1j9I4/bEcQkcl7r8VJgaB3gWtmfmZo= X-Proofpoint-GUID: cc6peUVDvD9J9IhEie9tVw1GigIk7ENC X-Proofpoint-ORIG-GUID: cc6peUVDvD9J9IhEie9tVw1GigIk7ENC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 suspectscore=0 malwarescore=0 bulkscore=0 phishscore=0 clxscore=1030 mlxlogscore=881 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.84.73; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710272935116600 Content-Type: text/plain; charset="utf-8" Apple's platform vGIC doesn't support ITS. Deal with this by reporting to t= he user and not creating the ITS device. Signed-off-by: Mohamed Mediouni --- hw/arm/virt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 91d8cd9363..005e923a22 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -740,6 +740,16 @@ static void create_its(VirtMachineState *vms) return; } =20 + if (hvf_enabled() && hvf_irqchip_in_kernel() && vms->tcg_its) { + /* + * In the HVF case, inform the user that they can use the + * user-mode GIC if they want to have an ITS. + */ + info_report("ITS not supported without kernel-irqchip=3Doff on HVF= "); + info_report("Disabling ITS"); + return; + } + dev =3D qdev_new(its_class_name()); =20 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753710146; cv=none; d=zohomail.com; s=zohoarc; b=aAR1hqnp9qZZr209fn9jeRANMwcajvdmjWQGSiQZON8YQ466DamoOZVRBEP95swzDmkxl7fvFk5wTV2DbKMlsXq17HWtdOXaFu7+PoosxQd1KJiU33MyN+lN75xoNUwRRaxn8yKE+3sL/z3Y+MH8o5Y85ltg3MXvginKLEaUxrU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753710146; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L1qOyHhqDgGsOLJo1zy700C7fqSb1OJFMO/RUzccOn4=; b=NrjyeGhQSbFk7+nq+fZ5zKzVC6+N22LIKmdvmo/W9/hIe97ZJdapzJ1noR9y/JqCvM7f8NtyF8AkteI2Svgaxg5Qt63H7eNxByyp3nwobGCfC/Iftlde54KIeGrkBpsNPF5Mt2YoBZyMpCSuu1+GTMeROVWY8zxfToW1ceGJxdI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753710146602816.6092735294407; Mon, 28 Jul 2025 06:42:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugO6v-0005Yg-FQ; Mon, 28 Jul 2025 09:41:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6r-00056H-KZ for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:46 -0400 Received: from p-east3-cluster5-host4-snip4-5.eps.apple.com ([57.103.86.166] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6o-0004JI-FJ for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:44 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPS id 28ACD1819D2F; Mon, 28 Jul 2025 13:41:35 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPSA id EA34B1819D0A; Mon, 28 Jul 2025 13:41:32 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=L1qOyHhqDgGsOLJo1zy700C7fqSb1OJFMO/RUzccOn4=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=ZuTTVaxp8kHsEq8tTgLNLAmptYgfD73kLEF5is7Hf1afV5OKTL/4ujtwv+1+S5oV/iJ8r5J6zZ7VP+KKo1Gm5a7LgkzyuL04D+VYR/98FDjGJw+OtKQKnBHWlL54HGeTAaFWvgFXhzbPLFEWRai3PQ0/bEfjJJwOUhwLH5phis+IlBx0IIcoqnhukIzhviRYr/KS7ekL+rhtpOixYTU1u3v/4Bvt4fP1ro3wF6m/gh1xvBdYDzedSxwcpMce3xHuuApa5aBXCbsQsww/rXPX0cI8UYXVJS1Kl+qx548MoxN0P/dLlB1ixJcULDQdcSOFHdIhSX10kB45KQHqNu1GaQ== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , Paolo Bonzini , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Alexander Graf , Roman Bolshakov , Peter Maydell , "Michael S. Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 09/13] hvf: only call hvf_sync_vtimer() when running without the platform vGIC Date: Mon, 28 Jul 2025 15:41:10 +0200 Message-Id: <20250728134114.77545-10-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: yFMkwnrESG6E3MH_tkeOfzhdOZas7QsF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfXx1FN1qOTI1ZX NTJGotKEKYmMMkwC/xfgWmTN0aOyg6mIuGeqSrn1NIhT5/hrhdq6QyGjARVRmw/YkprQg++IM1H sAot1VqD2t0dSlBQ9AukiSEbIicbGgrAgHsba9GUaAEI3EI3xxf8QwzLODJYBpRFwOl1/H3OvOs RaARoTQRtnDOv/kSxEc+IqWVQ4xIunmS5AzSM3qcL3VIOZIv/JdJYq9ltwWXSkh2YyCvEwkPlgr 8q10Wu9nnzLmo9k3I7Lhj1zAIRoL3gdLe1k7BuDVtxtTZHGRDQ558xXuZQHKj8kl3v6BaDRhY= X-Proofpoint-GUID: yFMkwnrESG6E3MH_tkeOfzhdOZas7QsF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 mlxlogscore=890 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1030 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.166; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710149879116600 Content-Type: text/plain; charset="utf-8" When running with the Apple vGIC, the EL1 vtimer is handled by the platform. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index eefae3069f..7699669e73 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2007,7 +2007,8 @@ int hvf_vcpu_exec(CPUState *cpu) g_assert_not_reached(); } =20 - hvf_sync_vtimer(cpu); + if (!hvf_irqchip_in_kernel()) + hvf_sync_vtimer(cpu); =20 switch (ec) { case EC_SOFTWARESTEP: { --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753710220; cv=none; d=zohomail.com; s=zohoarc; b=Z/D9b3ZFHgFaJAk2w/iwgp4VRk0XmPx5q8ByY+XduEKOy23ZwbbYbSfbHxXE1WvDtk51nBr03sJ8Ur0cdWnt0tpUAgDSZ+R4y8AWxvKcGqa1hQudbS8HIzHizz35x3vsoaCbXdcc05Ih+cWfLGSU5LtYwk6TEhlgCgb82967tlg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753710220; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YG7xyF6TQr9/wUm8Ggc33KCpY36/UF39gGxsJLfJmEM=; b=e70OmicDfasftt8bNQA4rQbVHQywFsbEhmni6sGXUAHv/y2/af4tw3MIKufr/S9rjxQH7yJeP4mmnvir6MshrIXnAtn0DEp/uKZokJGOAhruYpvATjlfXRxd8nqVuQz3g7Bg4b9MFajHBTmSsnkbmJjPq+TxphS3I9B2CDgdBAg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753710220465694.8209051788878; Mon, 28 Jul 2025 06:43:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugO7n-0003KQ-KO; Mon, 28 Jul 2025 09:42:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6r-000560-KQ for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:46 -0400 Received: from p-east3-cluster6-host10-snip4-10.eps.apple.com ([57.103.85.231] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6n-0004JZ-LR for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:44 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPS id E0C9A1819758; Mon, 28 Jul 2025 13:41:36 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPSA id B90F818001D9; Mon, 28 Jul 2025 13:41:34 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=YG7xyF6TQr9/wUm8Ggc33KCpY36/UF39gGxsJLfJmEM=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=B6AWkOOhupBC+Le6E40ts/0oMVef9jC5ylZetgBXI8jqOXZw75mk5Gsz/Mnknnp2qYk5UBeLMWxdk8MLwvnEg7A43eDs5F4yo+hvRC6MZROCG6UAJT30AQ729NqKbWGdfxcrbvy3DhD4aNt4NS932HmH8G9GaXkahrYS+YelsBAOUY/19c4wIHUVc+yeZp1eNWgTuhOhNyqeCS3XKOt7+VYOtUcrmFXwrdwlLuC+Y6iWg/HgUdkRyB0FJZaqHWyj3Pa8BYyGLIOjyfzH00l4V+zfDwGE3SbgFI9VihfzuwNY+dUHJLO+eZsCUMCvSvbRVlEN5upUJrX64+H9B9pokA== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , Paolo Bonzini , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Alexander Graf , Roman Bolshakov , Peter Maydell , "Michael S. Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 10/13] hvf: sync registers used at EL2 Date: Mon, 28 Jul 2025 15:41:11 +0200 Message-Id: <20250728134114.77545-11-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: IYrNxncVSx-pylN7_MN-5K4dJrI6GiVb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX1ct6rwaWGKnV vgoEUuQVLNV2f4qJVqI6fPSAMwJzREmaNLvQlDsupg5kaM30NeKzgcJunzHxt4lMLIlWRtc6Cmm eAukzkjNlVkIGh08BNCn5FR0JLpNyOuqyKSGQHsCMciO1bI1qlCzSJ55DSgZwm4HrcEH9KOQWiq AunjgXgL0cYv8FfRWgEXBNQHWm4V5Qvj2ghCO5923wa9uIrq7eVvwlVAzWBTkO6ClHkPLniyCAD aMOcohEZIPvC2+yYAThbAfjBYiGbgt6+hDhTIf4G970XfP3vKuW1BksJWjjWdHmfJvNIZnqCU= X-Proofpoint-GUID: IYrNxncVSx-pylN7_MN-5K4dJrI6GiVb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 bulkscore=0 spamscore=0 clxscore=1030 mlxlogscore=887 adultscore=0 mlxscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.231; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710223054116600 Content-Type: text/plain; charset="utf-8" When starting up the VM at EL2, more sysregs are available. Sync the state = of those. In addition, sync the state of the EL1 physical timer when the vGIC is used= , even if running at EL1. However, no OS running at EL1 is expected to use those r= egisters. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 7699669e73..a1e928ddfa 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -406,6 +406,8 @@ static const struct hvf_reg_match hvf_fpreg_match[] =3D= { struct hvf_sreg_match { int reg; uint32_t key; + bool vgic; + bool el2; uint32_t cp_idx; }; =20 @@ -551,6 +553,41 @@ static struct hvf_sreg_match hvf_sreg_match[] =3D { { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, + /* vGIC */ + { HV_SYS_REG_CNTP_CTL_EL0, HVF_SYSREG(14, 2, 3, 3, 1), true }, + { HV_SYS_REG_CNTP_CVAL_EL0, HVF_SYSREG(14, 2, 3, 3, 2), true }, +#ifdef SYNC_NO_RAW_REGS + { HV_SYS_REG_CNTP_TVAL_EL0, HVF_SYSREG(14, 2, 3, 3, 0), true}, +#endif + /* vGIC + EL2 */ + { HV_SYS_REG_CNTHCTL_EL2, HVF_SYSREG(14, 1, 3, 4, 0), true, true }, + { HV_SYS_REG_CNTHP_CVAL_EL2, HVF_SYSREG(14, 2, 3, 4, 2), true, true }, + { HV_SYS_REG_CNTHP_CTL_EL2, HVF_SYSREG(14, 2, 3, 4, 1), true, true }, +#ifdef SYNC_NO_RAW_REGS + { HV_SYS_REG_CNTHP_TVAL_EL2, HVF_SYSREG(14, 2, 3, 4, 0), true, true }, +#endif + { HV_SYS_REG_CNTVOFF_EL2, HVF_SYSREG(14, 0, 3, 4, 3), true, true }, + /* EL2 */ + { HV_SYS_REG_CPTR_EL2, HVF_SYSREG(1, 1, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_ELR_EL2, HVF_SYSREG(4, 0, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_ESR_EL2, HVF_SYSREG(5, 2, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_FAR_EL2, HVF_SYSREG(6, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_HCR_EL2, HVF_SYSREG(1, 1, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_HPFAR_EL2, HVF_SYSREG(6, 0, 3, 4, 4), .el2 =3D true }, + { HV_SYS_REG_MAIR_EL2, HVF_SYSREG(10, 2, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_MDCR_EL2, HVF_SYSREG(1, 1, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_SCTLR_EL2, HVF_SYSREG(1, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_SPSR_EL2, HVF_SYSREG(4, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_SP_EL2, HVF_SYSREG(4, 1, 3, 6, 0), .el2 =3D true}, + { HV_SYS_REG_TCR_EL2, HVF_SYSREG(2, 0, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_TPIDR_EL2, HVF_SYSREG(13, 0, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_TTBR0_EL2, HVF_SYSREG(2, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_TTBR1_EL2, HVF_SYSREG(2, 0, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_VBAR_EL2, HVF_SYSREG(12, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_VMPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 5), .el2 =3D true }, + { HV_SYS_REG_VPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_VTCR_EL2, HVF_SYSREG(2, 1, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_VTTBR_EL2, HVF_SYSREG(2, 1, 3, 4, 0), .el2 =3D true }, }; =20 int hvf_get_registers(CPUState *cpu) @@ -594,6 +631,14 @@ int hvf_get_registers(CPUState *cpu) continue; } =20 + if (hvf_sreg_match[i].vgic && !hvf_irqchip_in_kernel()) { + continue; + } + + if (hvf_sreg_match[i].el2 && !hvf_arm_el2_enabled()) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { @@ -731,6 +776,14 @@ int hvf_put_registers(CPUState *cpu) continue; } =20 + if (hvf_sreg_match[i].vgic && !hvf_irqchip_in_kernel()) { + continue; + } + + if (hvf_sreg_match[i].el2 && !hvf_arm_el2_enabled()) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 11/13] hvf: gate ARM_FEATURE_PMU register emulation behind not being at EL2 Date: Mon, 28 Jul 2025 15:41:12 +0200 Message-Id: <20250728134114.77545-12-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX4FpretWVjPQd YjgZEI8yjbJnAt6eqNpvrTy6j6P0Ob3m2rO/UFsAFoe+LTfpHmyGViNPeNSABEn1SPpjZy09Kz7 UnYldOhZ6ZFpciOdMsSfq0SjkM+R8FvUkf5quNA3GroWjC7qJNpso95xqGEQyywSXLXQI6tclHB 12rs+BC/L6zJg/GUkdCIqxres0D7WvsJM1yrw41gkyoWXWIG2ximuMMTnvumH7E1ip6nDq8688N Ty6Th8jwQR20D3hCfGXNg3bnl5JEkgVDmXTgE5i0VGusLWGTRIZ1/oncI2g0KXU9o+dj8BAOo= X-Proofpoint-GUID: vF3sOsrB9ORjJmIqU01mq9Av2tXvxBn3 X-Proofpoint-ORIG-GUID: vF3sOsrB9ORjJmIqU01mq9Av2tXvxBn3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 suspectscore=0 malwarescore=0 spamscore=0 mlxlogscore=766 bulkscore=0 mlxscore=0 clxscore=1030 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.136; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710493933116600 From Apple documentation: > When EL2 is disabled, PMU register accesses trigger "Trapped MSR, MRS, or > System Instruction" exceptions. When this happens, hv_vcpu_run()=E2=80=AF= returns, and the > =E2=80=AFhv_vcpu_exit_t=E2=80=AFobject contains the information about thi= s exception. > When EL2 is enabled, the handling of PMU register accesses is determined = by the PMUVer > field of ID_AA64DFR0_EL1=E2=80=AFregister. > If the PMUVer=E2=80=AFfield value is zero or is invalid, PMU register acc= esses generate "Undefined" > exceptions, which are sent to the guest. > If the PMUVer=E2=80=AFfield value is non-zero and valid, PMU register acc= esses are emulated by the framework. > The ID_AA64DFR0_EL1=E2=80=AFregister can be modified via hv_vcpu_set_sys_= reg=E2=80=AFAPI. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index a1e928ddfa..f70870fb62 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1379,7 +1379,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; =20 - if (arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_arm_el2_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCR_EL0: *val =3D env->cp15.c9_pmcr; @@ -1676,7 +1676,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) SYSREG_OP2(reg), val); =20 - if (arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_arm_el2_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCCNTR_EL0: pmu_op_start(env); --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753710269; cv=none; d=zohomail.com; s=zohoarc; b=CJWKJTo2i1McRIup72sYEFx+O051SKN3Iqs4YWOef7ozCwqQ8yiOQvdClbv5pdS37lXZ+ywY8QcJ+JjyDJXXm05wW1SryhhaY9fopBWfc15ECT/sWgCASF6q8hiEDRkoHfTHLCjJPxbCtZruKPI5c9gpBSakdk6Ft4Xt0+83TaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753710269; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ssd6YNHgtSnjqPta+M8MbDoQ9g9wz27kHCDbsfNdBos=; b=GGG9wSQYtsZKcMQZKre6LU38HDPKvRA18NiZ2BW6PHGTaZrhNLe120Fu7JP2vgI3qh1yAtZwvahySUvmdx+g6sLfleY+AGXqFrqbMv6iEMU7fkwu8s8GSuJiO9zErwur6k+ApNzutHhS2mJ4yqoUHO/y07MMIXsUSeeIPwf7nu8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753710269689906.695533271234; Mon, 28 Jul 2025 06:44:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugO7s-0003zJ-CS; Mon, 28 Jul 2025 09:42:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6s-0005BK-Bh for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:46 -0400 Received: from p-east3-cluster5-host3-snip4-10.eps.apple.com ([57.103.86.161] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6p-0004KD-Ge for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:46 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPS id 7373B1819D0A; Mon, 28 Jul 2025 13:41:40 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPSA id 43FD81800219; Mon, 28 Jul 2025 13:41:38 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=Ssd6YNHgtSnjqPta+M8MbDoQ9g9wz27kHCDbsfNdBos=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=HGBLiUl3GNb6k0GKTObw46HDSgexxFwvbCHXzkV/tugo0tqDR2zNJrFKsccxXW65EyBBcq0EfyaljydJ/OwVhXP7D2QBBlzTS41AywPpu4OFhN7WYNoFgO03ncPXj+VHi+ZLEpb83tIJVmrlw1rPuCxjruzRrSt6+uGCtiPIZPDSxvAEMmsUMMtIVcO+/mNmMFyJ20/POBOmKkULW5Kzn4l7FhcGqF39NOo56oi9EAIMFGOBrNCuRRmY3kEDKNHMNB6/xxdbLbJSWSfmpq64IwCoelX5UDWxR45wIp8bHJdSZTMvNtkuvbj9RtIw6iGBXfGpWIWV+pQpaXBxa3qWBA== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , Paolo Bonzini , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Alexander Graf , Roman Bolshakov , Peter Maydell , "Michael S. Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 12/13] target/arm: hvf: instantiate GIC early Date: Mon, 28 Jul 2025 15:41:13 +0200 Message-Id: <20250728134114.77545-13-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX4RDHg2TP2nZg WnrkzLeAgJ0FgxIydcgsCyet69GE/MRmqa4TPb4U+Nbg5LuOmZXwxGQRiafig1NXb59vMn4XiZr FSwCPFJlYJbt3p1pQ1mbhd++VFjHNdB56DOwifH2w0g+cEg4Fj47hTiTN+CcKFis6nNfIBai9Iy ETfHiX4Vn6CFpwv8DsOhlDU6hp4u6WRax2DpO6hI2oJabZ0cXNBiIHfGOlP+SGQ8KVPcQlSzcZ3 fbPY3hNTPvon7d5yG9O5hC0wauhaQME879IGyP3m1SkJOS548au6a3MVJssZHzeDQoKRtwyng= X-Proofpoint-GUID: a7O7H2l8ysik6BdoXL8lHuvV0RJ-z63x X-Proofpoint-ORIG-GUID: a7O7H2l8ysik6BdoXL8lHuvV0RJ-z63x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 mlxscore=0 phishscore=0 bulkscore=0 mlxlogscore=732 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.161; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710270943116600 Content-Type: text/plain; charset="utf-8" While figuring out a better spot for it, put it in hv_arch_vm_create(). After hv_vcpu_create is documented as too late, and deferring vCPU initialization isn't enough either. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f70870fb62..1fd9517f3e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1083,6 +1083,21 @@ hv_return_t hvf_arch_vm_create(MachineState *ms, uin= t32_t pa_range) } =20 ret =3D hv_vm_create(config); + if (hvf_irqchip_in_kernel()) { + /* + * Instantiate GIC. + * This must be done prior to the creation of any vCPU + * but past hv_vm_create() + */ + hv_gic_config_t cfg =3D hv_gic_config_create(); + hv_gic_config_set_distributor_base(cfg, 0x08000000); + hv_gic_config_set_redistributor_base(cfg, 0x080A0000); + hv_return_t err =3D hv_gic_create(cfg); + if (err !=3D HV_SUCCESS) { + error_report("error creating platform VGIC"); + goto cleanup; + } + } =20 cleanup: os_release(config); --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:43:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753710538; cv=none; d=zohomail.com; s=zohoarc; b=lCqn3g5QZvQP8Ff0r6Ics44yDaBSIVeVBiyhn5oITh32mXGxM/OzAuAsKtKo653x0TaoCcgQMbmgUfVPZOIJOx5fuUigW+9l9mtSV9+M6fRZ5JaZ7OrIvCUw29nmlycpCYGB6Zw7SqLC7ZNfRHnje3ZgEnHTomfBODHr1nl/CBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753710538; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mPWTN385R6FZfouZZinJrVOLlU3HnBlA0ntuqA5utf4=; b=kqP1PEIB7/rs72GDqDrFnGapxear/bM53p4JxBQHI6ErBO7B33YigYGvUMxVAXzdMApHP25DctFhrxM50ZqWllB7kmHJW1y6itejfhdT0xXUZEolKITg2nNK0xLJCncDuYC7DhvdW8P1XE8H6zg7IaI881h6Z7+52aa9aYUk1MI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753710538233570.154157892116; Mon, 28 Jul 2025 06:48:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugO7U-0000qB-Qe; Mon, 28 Jul 2025 09:42:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6s-0005G8-Tk for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:47 -0400 Received: from p-east3-cluster3-host8-snip4-7.eps.apple.com ([57.103.86.80] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugO6q-0004KU-Du for qemu-devel@nongnu.org; Mon, 28 Jul 2025 09:41:46 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPS id 3FE0018001FF; Mon, 28 Jul 2025 13:41:42 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-3 (Postfix) with ESMTPSA id 3FDB9181977E; Mon, 28 Jul 2025 13:41:40 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=mPWTN385R6FZfouZZinJrVOLlU3HnBlA0ntuqA5utf4=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=PM1a2xEEwolU2+5eKrhBQxeH+mSMpucsCO/gH88ootLxi6U1C9YW+h7hAUo0AyaQ/3AKu8q9kIam+60FraliCkrJOHT7c474I8BvQL8dC7btg6OBytnQyjlPSegugPECSSa1cmrvmNo872em9VBFjglDM1mrmbNT/7C9jkQU3OT6YmUZPNGUi/UmsFBM/e6be8J2K/orNQMA50Sywx9hnoz71LuNiYMI5DJAaCWt/F4F4rAfgGNuotXujALeSh3TIJ0Y+IfgGaGea5dbh+Wf+85HlucLWR6FY+c5jCtl+A4JGRepsAjUQcxnaTh9ValCKFpbIRPpzkPdoxujAVdqJQ== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , Paolo Bonzini , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Alexander Graf , Roman Bolshakov , Peter Maydell , "Michael S. Tsirkin" , Ani Sinha , Cameron Esfahani , Mohamed Mediouni Subject: [PATCH v5 13/13] target/arm: hvf: add asserts for code paths not leveraged when using the vGIC Date: Mon, 28 Jul 2025 15:41:14 +0200 Message-Id: <20250728134114.77545-14-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728134114.77545-1-mohamed@unpredictable.fr> References: <20250728134114.77545-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: nJNUOC_nKv69xIiTKz7zF6d1AL153m2b X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDEwMSBTYWx0ZWRfX4Sbx6cIziteL 41iyb0PE/An3eG9IFDfHRUMMY/PCn12hcszyfXwAkso3VoaUDj0x42a5rV1IMjtY676n2pBfvAl WRQvYRDnhXOZpZQWBQ4brlvTzN+qVieMMg/6TXf5pD6URaN9CujIhGlv+hKGkwu5pnJ5Cu9A027 3dF/F8bfGzRd0tu2Juvy1Jo+HFBygnq8Psfr+j+6YI5iY4m9SWpCVNV1Khzi71dnyPQ3+pP/oRN a0Uf33ghfCB5hIWdXmiymYHu78rpIdwz0p7rTgMQ+GrJJzv0x0uGBOAmdXESy+/w8ENZFSwrA= X-Proofpoint-ORIG-GUID: nJNUOC_nKv69xIiTKz7zF6d1AL153m2b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 bulkscore=0 mlxscore=0 mlxlogscore=588 spamscore=0 suspectscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280101 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.80; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753710540070116600 Content-Type: text/plain; charset="utf-8" When using the vGIC, timers are directly handled by the platform. No vmexits ought to happen in that case. Abort if reaching those code paths. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 1fd9517f3e..12cdcb3f2c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1476,6 +1476,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: case SYSREG_ICC_CTLR_EL1: + assert(!hvf_irqchip_in_kernel()); /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ if (hvf_sysreg_read_cp(cpu, reg, val)) { return 0; @@ -1802,6 +1803,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_ICC_SGI0R_EL1: case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: + assert(!hvf_irqchip_in_kernel()); /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ if (hvf_sysreg_write_cp(cpu, reg, val)) { return 0; @@ -2065,6 +2067,7 @@ int hvf_vcpu_exec(CPUState *cpu) /* This is the main one, handle below. */ break; case HV_EXIT_REASON_VTIMER_ACTIVATED: + assert(!hvf_irqchip_in_kernel()); qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); cpu->accel->vtimer_masked =3D true; return 0; --=20 2.39.5 (Apple Git-154)