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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 14/15] hvf: sync registers used at EL2 Date: Mon, 28 Jul 2025 07:57:00 +0200 Message-Id: <20250728055701.38975-15-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: e_tlGfHcTSHBOT9iIJ4lR05UCTVD-jhM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfXzLiQVsLh8B5i qU2DXNtD1pU7ARJpcMEsA5Prj7dkt+AUCBLmi9p0WAb+9Xc/Kjk8mXQ0RThAiM9D5t7lOOab/wz eCo4KCBmnKbk4keEOx/oYjdCt0xAmDNifUZ7THAnNu+QS4Yvqsjozs4CmIHHcPU4znfQfiG85X9 VnUTo1TD2YyXhFVecics8uDrqsjenuTKBp6rJQO2CQLmasGTkKbDtSgHxKjoHjF3GEfZmhy5RWt TL8iZw1NfDzuzUK7ETHU4acgJEgXRhCAWlK3ezG6M1wQJqMv5+4wgSjR/LODvg3nE09Cw3Tjo= X-Proofpoint-ORIG-GUID: e_tlGfHcTSHBOT9iIJ4lR05UCTVD-jhM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=887 phishscore=0 clxscore=1030 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.27; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682461250116600 Content-Type: text/plain; charset="utf-8" When starting up the VM at EL2, more sysregs are available. Sync the state = of those. In addition, sync the state of the EL1 physical timer when the vGIC is used= , even if running at EL1. However, no OS running at EL1 is expected to use those r= egisters. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 64cca9aa18..af9bbe44ed 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -407,6 +407,8 @@ static const struct hvf_reg_match hvf_fpreg_match[] =3D= { struct hvf_sreg_match { int reg; uint32_t key; + bool vgic; + bool el2; uint32_t cp_idx; }; =20 @@ -552,6 +554,41 @@ static struct hvf_sreg_match hvf_sreg_match[] =3D { { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, + /* vGIC */ + { HV_SYS_REG_CNTP_CTL_EL0, HVF_SYSREG(14, 2, 3, 3, 1), true }, + { HV_SYS_REG_CNTP_CVAL_EL0, HVF_SYSREG(14, 2, 3, 3, 2), true }, +#ifdef SYNC_NO_RAW_REGS + { HV_SYS_REG_CNTP_TVAL_EL0, HVF_SYSREG(14, 2, 3, 3, 0), true}, +#endif + /* vGIC + EL2 */ + { HV_SYS_REG_CNTHCTL_EL2, HVF_SYSREG(14, 1, 3, 4, 0), true, true }, + { HV_SYS_REG_CNTHP_CVAL_EL2, HVF_SYSREG(14, 2, 3, 4, 2), true, true }, + { HV_SYS_REG_CNTHP_CTL_EL2, HVF_SYSREG(14, 2, 3, 4, 1), true, true }, +#ifdef SYNC_NO_RAW_REGS + { HV_SYS_REG_CNTHP_TVAL_EL2, HVF_SYSREG(14, 2, 3, 4, 0), true, true }, +#endif + { HV_SYS_REG_CNTVOFF_EL2, HVF_SYSREG(14, 0, 3, 4, 3), true, true }, + /* EL2 */ + { HV_SYS_REG_CPTR_EL2, HVF_SYSREG(1, 1, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_ELR_EL2, HVF_SYSREG(4, 0, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_ESR_EL2, HVF_SYSREG(5, 2, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_FAR_EL2, HVF_SYSREG(6, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_HCR_EL2, HVF_SYSREG(1, 1, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_HPFAR_EL2, HVF_SYSREG(6, 0, 3, 4, 4), .el2 =3D true }, + { HV_SYS_REG_MAIR_EL2, HVF_SYSREG(10, 2, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_MDCR_EL2, HVF_SYSREG(1, 1, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_SCTLR_EL2, HVF_SYSREG(1, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_SPSR_EL2, HVF_SYSREG(4, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_SP_EL2, HVF_SYSREG(4, 1, 3, 6, 0), .el2 =3D true}, + { HV_SYS_REG_TCR_EL2, HVF_SYSREG(2, 0, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_TPIDR_EL2, HVF_SYSREG(13, 0, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_TTBR0_EL2, HVF_SYSREG(2, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_TTBR1_EL2, HVF_SYSREG(2, 0, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_VBAR_EL2, HVF_SYSREG(12, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_VMPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 5), .el2 =3D true }, + { HV_SYS_REG_VPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_VTCR_EL2, HVF_SYSREG(2, 1, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_VTTBR_EL2, HVF_SYSREG(2, 1, 3, 4, 0), .el2 =3D true }, }; =20 int hvf_get_registers(CPUState *cpu) @@ -595,6 +632,14 @@ int hvf_get_registers(CPUState *cpu) continue; } =20 + if (hvf_sreg_match[i].vgic && !hvf_irqchip_in_kernel()) { + continue; + } + + if (hvf_sreg_match[i].el2 && !hvf_arm_el2_enabled()) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { @@ -732,6 +777,14 @@ int hvf_put_registers(CPUState *cpu) continue; } =20 + if (hvf_sreg_match[i].vgic && !hvf_irqchip_in_kernel()) { + continue; + } + + if (hvf_sreg_match[i].el2 && !hvf_arm_el2_enabled()) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { --=20 2.39.5 (Apple Git-154)