From nobody Sun Feb 8 14:06:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682756; cv=none; d=zohomail.com; s=zohoarc; b=KgleJ0kGYRIE5n5zaaTFe1vbiKmc67Jo3JKtaijPfYFQ5C0btlaSG3mezbomJZ24uw20PoezUdWo/TN3zvPDPU7kWR2itQp9Af7lmB+QQGJDi+HKi25pEpnCVnmUmyKXJ2DSoi3uAY3qjYvFAI1+JRjMVEKGlLd3DrP2dApJ4co= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682756; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=y6mI8AmJ1dWdgen3Y4HML2fQWE3KY+VD1EyD//Qc2Zo=; b=QXF/vpk66Y3DT29j4oFDqLK/RyaClbeJwxFyY/kQlvGvOZAMjdAfyAemue9V2gBdOZKcJGzXJneaHjPRUvxAnIv7Qb+Vm5nVmkMviiAGX2A09YkzKacTOL1ojX4FpYq04sskFOzHfGLyRvI17/TMlIIx4vW19qpv0H4QsZjpPPA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753682756686491.67882265985054; Sun, 27 Jul 2025 23:05:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGtE-000133-Mg; Mon, 28 Jul 2025 01:59:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrg-0007MP-1V for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:41 -0400 Received: from p-east3-cluster3-host2-snip4-6.eps.apple.com ([57.103.86.19] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGre-0007Gy-98 for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:35 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id A66AC18000AA; Mon, 28 Jul 2025 05:57:30 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id 64038180009A; Mon, 28 Jul 2025 05:57:28 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=y6mI8AmJ1dWdgen3Y4HML2fQWE3KY+VD1EyD//Qc2Zo=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=bPar//4VQb8tPifxBJ6DFGXXmdw2AMFIC9kJAU/0JP5g8DTGTFqJHUV95D+QtqhjBISTLsuGdhXFLNgC/+rmK5lh1vCtwKnFjBcgkG+7x5uNzoecMB75hRgnbtlZzSinJE6k06OBckbgQho85XNyvUzArnK1Qti0NCURTk6prhmfxlts6mlvJke9XOmqaZRv2UKQ4LsdFC4T7aFb26HUrJtWkSN77TxeIxWrpxfzmApb6hojWSVMqMuD5cV5i8HGnUTsAzSc2vkX99u3uc7inZWUuiVn66uWdu+j4BIyxYfFtCWbL8KfmG7jNMDFxWN0uDDcwPtZpK0oLVWGSh7V/w== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 13/15] hw/intc: hvf: sync state in c->ich* registers when virt on Date: Mon, 28 Jul 2025 07:56:59 +0200 Message-Id: <20250728055701.38975-14-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 9TPXBQzbmoXtYz68X5g5VPWXWVWc7f-j X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX6qTXyYh7iTmm l2J51eimKbaGReSTF7ikrIXBTyVyO2aki5Yx2pEFrUQdSOR5UcqqZMdsyu2Fkl1dSfDm8bFouNj H4eNz230fAZGhsc8YRLCPMsHcTPhlhbmGhQ3uMOg7qCrNOZgaTMGHEgRwKtQ6H/DLBc7sB9Vvrx dpq+2GzwXfUXAAHC7ytxTaw2tVJC7t5CAwZliPmxXWIZF2zly+VOZjWTHS7PjKAv/17cBnzU1Ia UGFmvCGp6e6IG1IfZOZ8Xwnz+lvAI2Oyd+4WHJ15eVtyY2Cvo5lK4FA9oDV3dtloc7MRnRY+4= X-Proofpoint-GUID: 9TPXBQzbmoXtYz68X5g5VPWXWVWc7f-j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 mlxlogscore=884 malwarescore=0 mlxscore=0 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.19; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682757475116600 Content-Type: text/plain; charset="utf-8" Part of vGIC state to save/restore. Signed-off-by: Mohamed Mediouni --- hw/intc/arm_gicv3_hvf.c | 113 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/hw/intc/arm_gicv3_hvf.c b/hw/intc/arm_gicv3_hvf.c index a154b27318..30362540f2 100644 --- a/hw/intc/arm_gicv3_hvf.c +++ b/hw/intc/arm_gicv3_hvf.c @@ -15,6 +15,7 @@ #include "system/runstate.h" #include "system/hvf.h" #include "system/hvf_int.h" +#include "hvf_arm.h" #include "gicv3_internal.h" #include "vgic_common.h" #include "qom/object.h" @@ -315,6 +316,62 @@ static void hvf_gicv3_put(GICv3State *s) hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, reg64); } } + + /* Registers beyond this are with nested virt only */ + if (!hvf_arm_el2_enabled()) { + return; + } + + /* ICH */ + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + int num_pri_bits; + + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, + c->ich_vmcr_el2); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, + c->ich_hcr_el2); + + for (int i =3D 0; i < GICV3_LR_MAX; i++) { + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, + c->ich_lr_el2[i]); + } + + num_pri_bits =3D c->vpribits; + + switch (num_pri_bits) { + case 7: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3 + , c->ich_apr[GICV3_G0][3]); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2 + , c->ich_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1 + , c->ich_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + , c->ich_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3 + , c->ich_apr[GICV3_G1NS][3]); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2 + , c->ich_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1 + , c->ich_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + , c->ich_apr[GICV3_G1NS][0]); + } + } } =20 static void hvf_gicv3_get(GICv3State *s) @@ -452,6 +509,62 @@ static void hvf_gicv3_get(GICv3State *s) , &c->icc_apr[GICV3_G1NS][0]); } } + + /* Registers beyond this are with nested virt only */ + if (!hvf_arm_el2_enabled()) { + return; + } + + /* ICH */ + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + int num_pri_bits; + + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, + &c->ich_vmcr_el2); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, + &c->ich_hcr_el2); + + for (int i =3D 0; i < GICV3_LR_MAX; i++) { + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, + &c->ich_lr_el2[i]); + } + + num_pri_bits =3D c->vpribits; + + switch (num_pri_bits) { + case 7: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3 + , &c->ich_apr[GICV3_G0][3]); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2 + , &c->ich_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1 + , &c->ich_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + , &c->ich_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3 + , &c->ich_apr[GICV3_G1NS][3]); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2 + , &c->ich_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1 + , &c->ich_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + , &c->ich_apr[GICV3_G1NS][0]); + } + } } =20 static void hvf_gicv3_set_irq(void *opaque, int irq, int level) --=20 2.39.5 (Apple Git-154)