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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 01/15] accel, hw/arm, include/system/hvf: infrastructure changes for HVF vGIC Date: Mon, 28 Jul 2025 07:56:47 +0200 Message-Id: <20250728055701.38975-2-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 1GX8HXY5SmUydpGZwsv3PKoKBjYO-Uon X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX22OUfDfVAatF bPtDmsSr44SzIFmj3Qw1godPy959RwHcZqvlgUFF7hBbI0GzLNmVGyqnOfEwxGBDCktFHPpzUEr h1tdWSZ+JMkR1Npxv2n2+2i5iaDmcHhBvgqa9ZGhi07iZLYtseqnMpz6tYSHHqJ502wMQKS+Wtb NMBsvQTC4HZUuRWqxu05106Hx+LA2RmiHnDgIFxTASom1eEJtqAUeCjYthIOTv9DG9I88PPUhw1 7Fi8Udzbv70Auew2eArIFErvlK5qc6/PtkeG8u9SQLuPMmYDpbUTVmCe2UG0CO4xM8VUOSU+g= X-Proofpoint-GUID: 1GX8HXY5SmUydpGZwsv3PKoKBjYO-Uon X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1030 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.141; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682493023116600 Content-Type: text/plain; charset="utf-8" Misc changes needed for HVF vGIC enablement. Signed-off-by: Mohamed Mediouni --- accel/hvf/hvf-all.c | 44 ++++++++++++++++++++++++++++++++++++++ accel/stubs/hvf-stub.c | 1 + hw/arm/virt.c | 16 +++++++++----- hw/intc/arm_gicv3_common.c | 3 +++ include/system/hvf.h | 3 +++ system/vl.c | 2 ++ 6 files changed, 64 insertions(+), 5 deletions(-) diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index 0a4b498e83..5af76ba7a6 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -10,6 +10,8 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-common.h" #include "accel/accel-ops.h" #include "system/address-spaces.h" #include "system/memory.h" @@ -20,6 +22,7 @@ #include "trace.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; =20 struct mac_slot { int present; @@ -290,6 +293,41 @@ static int hvf_gdbstub_sstep_flags(AccelState *as) return SSTEP_ENABLE | SSTEP_NOIRQ; } =20 +static void hvf_set_kernel_irqchip(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ +#ifdef __aarch64__ + OnOffSplit mode; + if (!visit_type_OnOffSplit(v, name, &mode, errp)) { + return; + } + + switch (mode) { + case ON_OFF_SPLIT_ON: + hvf_kernel_irqchip =3D true; + break; + + case ON_OFF_SPLIT_OFF: + hvf_kernel_irqchip =3D false; + break; + + case ON_OFF_SPLIT_SPLIT: + error_setg(errp, "HVF: split irqchip is not supported on Arm."); + break; + + default: + /* + * The value was checked in visit_type_OnOffSplit() above. If + * we get here, then something is wrong in QEMU. + */ + abort(); + } +#else + error_setg(errp, "HVF: setting irqchip configuration not supported on = x86_64."); +#endif +} + static void hvf_accel_class_init(ObjectClass *oc, const void *data) { AccelClass *ac =3D ACCEL_CLASS(oc); @@ -297,6 +335,12 @@ static void hvf_accel_class_init(ObjectClass *oc, cons= t void *data) ac->init_machine =3D hvf_accel_init; ac->allowed =3D &hvf_allowed; ac->gdbstub_supported_sstep_flags =3D hvf_gdbstub_sstep_flags; + hvf_kernel_irqchip =3D true; + object_class_property_add(oc, "kernel-irqchip", "on|off|split", + NULL, hvf_set_kernel_irqchip, + NULL, NULL); + object_class_property_set_description(oc, "kernel-irqchip", + "Configure HVF irqchip"); } =20 static const TypeInfo hvf_accel_type =3D { diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c index 42eadc5ca9..6bd08759ba 100644 --- a/accel/stubs/hvf-stub.c +++ b/accel/stubs/hvf-stub.c @@ -10,3 +10,4 @@ #include "system/hvf.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ef6be3660f..7da1176cda 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -830,7 +830,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 @@ -853,8 +853,9 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count); =20 - if (!kvm_irqchip_in_kernel()) { - if (vms->tcg_its) { + if (!kvm_irqchip_in_kernel() && + !(hvf_enabled() && hvf_irqchip_in_kernel())) { + if (vms->its && vms->tcg_its) { object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem), &error_fatal); qdev_prop_set_bit(vms->gic, "has-lpi", true); @@ -864,7 +865,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) ARCH_GIC_MAINT_IRQ); } } else { - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->virt); } @@ -2058,7 +2059,12 @@ static void finalize_gic_version(VirtMachineState *v= ms) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; - } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { + } else if (hvf_enabled()) { + if (!hvf_irqchip_in_kernel()) { + gics_supported |=3D VIRT_GIC_VERSION_2_MASK; + } + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; + } else if (tcg_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { gics_supported |=3D VIRT_GIC_VERSION_3_MASK; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index e438d8c042..b8eee27260 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/hvf.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -662,6 +663,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (hvf_enabled() && hvf_irqchip_in_kernel()) { + return "hvf-arm-gicv3"; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/include/system/hvf.h b/include/system/hvf.h index d3dcf088b3..dc8da85979 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -26,8 +26,11 @@ #ifdef CONFIG_HVF_IS_POSSIBLE extern bool hvf_allowed; #define hvf_enabled() (hvf_allowed) +extern bool hvf_kernel_irqchip; +#define hvf_irqchip_in_kernel() (hvf_kernel_irqchip) #else /* !CONFIG_HVF_IS_POSSIBLE */ #define hvf_enabled() 0 +#define hvf_irqchip_in_kernel() 0 #endif /* !CONFIG_HVF_IS_POSSIBLE */ =20 #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf") diff --git a/system/vl.c b/system/vl.c index 3b7057e6c6..1c072d15a4 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1773,6 +1773,8 @@ static void qemu_apply_legacy_machine_options(QDict *= qdict) false); object_register_sugar_prop(ACCEL_CLASS_NAME("whpx"), "kernel-irqch= ip", value, false); + object_register_sugar_prop(ACCEL_CLASS_NAME("hvf"), "kernel-irqchi= p", value, + false); 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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 02/15] target/arm: hvf: instantiate GIC early Date: Mon, 28 Jul 2025 07:56:48 +0200 Message-Id: <20250728055701.38975-3-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: yGYHgbAxxG2EG2mKvW4VVzWD5IdaVQUs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX+8AV982c91wx sEWHeQ5RhjLOdN4m2nqmOvEg7PDk0hA5pD3kSWmqruWIMwZvMVJkQG/dVV1XrYW/y9N8mZOILrV RA7Lj2g45R8X8ZvUe0i5RWJctwkg0V16Y9Y0+Y6s+O9yvlO52meCk0bd4OqJobZeM5WNSl9C0tt qvDt+sFSmmgtesrFbNPy6DS+S//+/w6jUMGi+nH1PSq7RSBzRCkFPbRftiynTWZ5kl+IUrrWhZh XhTh7af7pQ1/7IrRU+CTiLzzO2QXjPvsCDtKfYQq1NuYojY+9ychwtzplRjzCbNPl20gbAxqI= X-Proofpoint-ORIG-GUID: yGYHgbAxxG2EG2mKvW4VVzWD5IdaVQUs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 bulkscore=0 mlxscore=0 mlxlogscore=615 spamscore=0 suspectscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.84.149; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682749251116600 Content-Type: text/plain; charset="utf-8" While figuring out a better spot for it, put it in hv_arch_vm_create(). Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 47b0cd3a35..3ba74b8daa 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1001,6 +1001,21 @@ hv_return_t hvf_arch_vm_create(MachineState *ms, uin= t32_t pa_range) chosen_ipa_bit_size =3D pa_range; =20 ret =3D hv_vm_create(config); + if (hvf_irqchip_in_kernel()) { + /* + * Instantiate GIC. + * This must be done prior to the creation of any vCPU + * but past hv_vm_create() + */ + hv_gic_config_t cfg =3D hv_gic_config_create(); + hv_gic_config_set_distributor_base(cfg, 0x08000000); + hv_gic_config_set_redistributor_base(cfg, 0x080A0000); + hv_return_t err =3D hv_gic_create(cfg); + if (err !=3D HV_SUCCESS) { + error_report("error creating platform VGIC"); + goto cleanup; + } + } =20 cleanup: os_release(config); --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682698; cv=none; d=zohomail.com; s=zohoarc; b=JGwC9omYanKyfzUTUkE/m5l0aggyOoEbTEt48Po1FJ9Dvd2uanHwMvU7WeNlogPng0GPXSL2Gm4zXi2QmWNzFTlOTeApiJLnWrmRWsGA84h8P1HfPSiD5U/sUiJaVyhmjvhmLnH8qyRLrG+tzOkitzvSe0aiXWGvQ7uk5jKr5Dg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682698; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HezpjLM2oi9haxQ0U3B8WellGbsu/AWM4D3KpVu2U/E=; b=lLXxAQiT5aIxHgGXfx3AKUojub2B75Gs3bu9f2zzGExDQz0Zgm9PUWSVrN32y/6V7DihR/jpD/rYQe6xb2tVyjB7kF6BOKEYcJI3n1hIoJ96GeiW/Y0u2GBPEOy/m5L3T91/Oy5cktz5Ki38/kQ4iNLVHyyVOTxDkw3zCfteDgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753682698836447.57091910831605; Sun, 27 Jul 2025 23:04:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGst-0000Q9-5t; Mon, 28 Jul 2025 01:58:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrN-0007C6-Gm for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:17 -0400 Received: from p-east3-cluster6-host1-snip4-4.eps.apple.com ([57.103.85.135] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrK-0007Bs-9q for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:17 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id 211EC180012F; Mon, 28 Jul 2025 05:57:12 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id 1EAB218000B0; Mon, 28 Jul 2025 05:57:10 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=HezpjLM2oi9haxQ0U3B8WellGbsu/AWM4D3KpVu2U/E=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=WuLc3+quiMv1mxDFSFw72ZhrybhaX4Z8kb42hcMHRr2Uui8lObILTBgwqjrcxJItx7UaMHlbqdHaf+OlurBq2aITmp/Gjw3guBb5M6TMPhas6ZOPxCFSCzqh2rgsCi6SHws4chdo0hq3ZRbYI78TcnRXH9sMIwDRbe43wk5wdnw/GLdlYBh6TvXlRWsELqsrct+UfH5ix9ydA8O2hIwpa/sEYnEMs4BLr1EUCy+ahpd9DGgcxldjBI0VQ2fbgTHDyUSiGcTZlnHRv4VyZT/2JgLPiuPCmdJxbbb0HTTgVbdY6m8d0Rp35RRyAEzM15WhzjL5lfvopMIF8WZfqXyOSg== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 03/15] target/arm: hvf: add asserts for code paths not leveraged when using the vGIC Date: Mon, 28 Jul 2025 07:56:49 +0200 Message-Id: <20250728055701.38975-4-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX0cIN9ajzFdPl VkA01/5hKeVtgjtyUHa5ouCWR9XHWRriNUNAHfX82gjKOujo+f30D16E1uf7Kj5ppVDCG5phXs8 l9LZQ1AyU6utUYxBKgGEtSREvzDHbJDxldSGlj3tNU5/Pod8fg6VHsvVR7nZCb2xAJJdgHKVcLs vz2HCCkmKZY/cvZ+DPnxHZd9/svq14d6+cp9oELTIT3MVHz9wR97V4Iy+qBBndVM4CXQbN4k8Hd /wJ4cPAm3Tobt2vz5qX526ZT8wXPhIfqZsEGOzp6jFjrjAe7755DZ7PVMp+nqrJdw5wXIkpKI= X-Proofpoint-ORIG-GUID: GdMFnko3xMRG9On8d_xqRPmUrFljSfjf X-Proofpoint-GUID: GdMFnko3xMRG9On8d_xqRPmUrFljSfjf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 clxscore=1030 bulkscore=0 adultscore=0 mlxlogscore=610 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.135; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682700953116600 Content-Type: text/plain; charset="utf-8" When using the vGIC, timers are directly handled by the platform. No vmexits ought to happen in that case. Abort if reaching those code paths. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 3ba74b8daa..7beb47caad 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1382,6 +1382,9 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: case SYSREG_ICC_CTLR_EL1: + if (hvf_irqchip_in_kernel()) { + abort(); + } /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ if (hvf_sysreg_read_cp(cpu, reg, val)) { return 0; @@ -1702,6 +1705,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_ICC_SGI0R_EL1: case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: + if (hvf_irqchip_in_kernel()) { + abort(); + } /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ if (hvf_sysreg_write_cp(cpu, reg, val)) { return 0; @@ -1965,6 +1971,10 @@ int hvf_vcpu_exec(CPUState *cpu) /* This is the main one, handle below. */ break; case HV_EXIT_REASON_VTIMER_ACTIVATED: + /* This is only for when a user-mode irqchip is used. */ + if (hvf_irqchip_in_kernel()) { + assert("vtimer activated vmexit when using platform GIC"); + } qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); cpu->accel->vtimer_masked =3D true; return 0; --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682428; cv=none; d=zohomail.com; s=zohoarc; b=g6drFtlCA+Harw0hoLL7oE5Z2DhhgNDON8ea+4IRyacmWOuxGhQXdQMDyPE+c8SyqQI2odEJhek+ukSF7HatC7K2njrw0ZsiYexD1ES30YgF+qLbWVQjQ9cPSPytWETjjaAD2lC/Y04mgdACTacsp0Lz6uqgb+UY/PbUtdFT0z0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682428; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1HsHYj1ziAyv4YBqhHuuhJmyb76wZ4D3LNzWMi1IZ0o=; b=hlJxu0K9ZBY9xdUVqpbIsj1Wtl2ri6WDo/7mt18g9CfYBMFvZ9rndzfeNikKyHCiPHkw+U12TglqGMyTHT6TGeoK1/dEp3xpQs7DcbmckzBohyODEkgZyp8gBB/qq7Qyf+v2g6q9cwxKbnY8d5PeJKMcpG8F1jKYPKz9ZMFS4R4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753682428434607.5710885827937; Sun, 27 Jul 2025 23:00:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGtA-0000wF-Se; Mon, 28 Jul 2025 01:59:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrS-0007FX-DY for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:27 -0400 Received: from p-east3-cluster6-host3-snip4-1.eps.apple.com ([57.103.85.152] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrL-0007CD-LE for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:19 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id E39831800140; Mon, 28 Jul 2025 05:57:13 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id ED87918000AA; Mon, 28 Jul 2025 05:57:11 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=1HsHYj1ziAyv4YBqhHuuhJmyb76wZ4D3LNzWMi1IZ0o=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=ZyTJcoiCjOiuwjxqL1HjHVUK8LEU3Wi1SR3fZ9a17G8GvqzcDsj1T2/JQfJPP7Ch6roS9lLS6D+MQM7AiZQna+5sMP0BHMVI1eSFMGtjUQ/EN5gqaItb/zrQ8JNkb7Gg/qepCIIeFZd3b64Cwgd+qMeAXulhn7kuEjlExxGociAe+zjTBETrARb5k+gGHH4ZEgXDJ0b852f45Z4XIMPttTmjw1xIqnh61KMwtgt4plQbKcW2ztZntbt3/mS7Uh+Z3qaFqR8Rj6SN6zu4WWOceZ9kfdW0eXgTgrFYkl/9ipN7s4Fq7uCNqVmZ57EmwJls+qAjvqYpsA5HS1ACPIyayQ== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 04/15] hw/intc: Add hvf vGIC interrupt controller support Date: Mon, 28 Jul 2025 07:56:50 +0200 Message-Id: <20250728055701.38975-5-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: Kn4IBIl-k4iQL_vGrv0GPLDbKYhrJAqU X-Proofpoint-ORIG-GUID: Kn4IBIl-k4iQL_vGrv0GPLDbKYhrJAqU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX7OJIlp/I2EdS lEmE9qc2QUfmYIp3E3c1+HnLsu6qUK3GwCJBSbD1fsi+l/0JyaTdF+OZOm+73Sb5s6EA8mMgjFQ sTezs/pylFHezOMXkReQRVT3KUK36RksSlEcbrg9ji/hy3N71IEinaSzXMDbJlJfVdpslQsD5mR Nmeod12E1TnsyXdttc+81s8yjNYY4hMxQjZO7FrdEFV2C531zUOWoRfqzqtV299FUxB0Vbk9Eoq wuN8uWqQYdGSYIS8dWWBVS46JgGWN2AdtuShXpfcPoaKfC24mHBstlPdQihntWpL7RIL4LYyo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 clxscore=1030 phishscore=0 suspectscore=0 mlxscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.152; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682430261116600 Content-Type: text/plain; charset="utf-8" This opens up the door to nested virtualisation support. Signed-off-by: Mohamed Mediouni --- hw/intc/arm_gicv3_hvf.c | 624 ++++++++++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + 2 files changed, 625 insertions(+) create mode 100644 hw/intc/arm_gicv3_hvf.c diff --git a/hw/intc/arm_gicv3_hvf.c b/hw/intc/arm_gicv3_hvf.c new file mode 100644 index 0000000000..a154b27318 --- /dev/null +++ b/hw/intc/arm_gicv3_hvf.c @@ -0,0 +1,624 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller using HVF platform support + * + * Copyright (c) 2025 Mohamed Mediouni + * Based on vGICv3 KVM code by Pavel Fedin + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "system/runstate.h" +#include "system/hvf.h" +#include "system/hvf_int.h" +#include "gicv3_internal.h" +#include "vgic_common.h" +#include "qom/object.h" +#include "target/arm/cpregs.h" +#include + +struct HVFARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#define TYPE_HVF_GICV3 "hvf-arm-gicv3" +typedef struct HVFARMGICv3Class HVFARMGICv3Class; + +/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ +DECLARE_OBJ_CHECKERS(GICv3State, HVFARMGICv3Class, + HVF_GICV3, TYPE_HVF_GICV3); + +/* + * Loop through each distributor IRQ related register; since bits + * corresponding to SPIs and PPIs are RAZ/WI when affinity routing + * is enabled, we skip those. + */ +#define for_each_dist_irq_reg(_irq, _max, _field_width) \ + for (_irq =3D GIC_INTERNAL; _irq < _max; _irq +=3D (32 / _field_width)) + +static void hvf_dist_get_priority(GICv3State *s, hv_gic_distributor_reg_t = offset + , uint8_t *bmp) +{ + uint64_t reg; + uint32_t *field; + int irq; + field =3D (uint32_t *)(bmp); + + for_each_dist_irq_reg(irq, s->num_irq, 8) { + hv_gic_get_distributor_reg(offset, ®); + *field =3D reg; + offset +=3D 4; + field++; + } +} + +static void hvf_dist_put_priority(GICv3State *s, hv_gic_distributor_reg_t = offset + , uint8_t *bmp) +{ + uint32_t reg, *field; + int irq; + field =3D (uint32_t *)(bmp); + + for_each_dist_irq_reg(irq, s->num_irq, 8) { + reg =3D *field; + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + field++; + } +} + +static void hvf_dist_get_edge_trigger(GICv3State *s, hv_gic_distributor_re= g_t offset, + uint32_t *bmp) +{ + uint64_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 2) { + hv_gic_get_distributor_reg(offset, ®); + reg =3D half_unshuffle32(reg >> 1); + if (irq % 32 !=3D 0) { + reg =3D (reg << 16); + } + *gic_bmp_ptr32(bmp, irq) |=3D reg; + offset +=3D 4; + } +} + +static void hvf_dist_put_edge_trigger(GICv3State *s, hv_gic_distributor_re= g_t offset, + uint32_t *bmp) +{ + uint32_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 2) { + reg =3D *gic_bmp_ptr32(bmp, irq); + if (irq % 32 !=3D 0) { + reg =3D (reg & 0xffff0000) >> 16; + } else { + reg =3D reg & 0xffff; + } + reg =3D half_shuffle32(reg) << 1; + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + } +} + +/* Read a bitmap register group from the kernel VGIC. */ +static void hvf_dist_getbmp(GICv3State *s, hv_gic_distributor_reg_t offset= , uint32_t *bmp) +{ + uint64_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 1) { + + hv_gic_get_distributor_reg(offset, ®); + *gic_bmp_ptr32(bmp, irq) =3D reg; + offset +=3D 4; + } +} + +static void hvf_dist_putbmp(GICv3State *s, hv_gic_distributor_reg_t offset, + hv_gic_distributor_reg_t clroffset, uint32_t *= bmp) +{ + uint32_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 1) { + /* + * If this bitmap is a set/clear register pair, first write to the + * clear-reg to clear all bits before using the set-reg to write + * the 1 bits. + */ + if (clroffset !=3D 0) { + reg =3D 0; + hv_gic_set_distributor_reg(clroffset, reg); + clroffset +=3D 4; + } + reg =3D *gic_bmp_ptr32(bmp, irq); + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + } +} + +static void hvf_gicv3_check(GICv3State *s) +{ + uint64_t reg; + uint32_t num_irq; + + /* Sanity checking s->num_irq */ + hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_TYPER, ®); + num_irq =3D ((reg & 0x1f) + 1) * 32; + + if (num_irq < s->num_irq) { + error_report("Model requests %u IRQs, but HVF supports max %u", + s->num_irq, num_irq); + abort(); + } +} + +static void hvf_gicv3_put(GICv3State *s) +{ + uint32_t reg; + uint64_t reg64, redist_typer; + int ncpu, i; + + hvf_gicv3_check(s); + + hv_vcpu_t vcpu0 =3D s->cpu[0].cpu->accel->fd; + hv_gic_get_redistributor_reg(vcpu0, HV_GIC_REDISTRIBUTOR_REG_GICR_TYPER + , &redist_typer); + + reg =3D s->gicd_ctlr; + hv_gic_set_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, reg); + + if (redist_typer & GICR_TYPER_PLPIS) { + error_report("ITS is not supported on HVF."); + abort(); + } + + /* Redistributor state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + + reg =3D c->gicr_waker; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= GROUPR0, reg); + + reg =3D c->gicr_igroupr0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= GROUPR0, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CENABLER0, reg); + reg =3D c->gicr_ienabler0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= SENABLER0, reg); + + /* Restore config before pending so we treat level/edge correctly = */ + reg =3D half_shuffle32(c->edge_trigger >> 16) << 1; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CFGR1, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CPENDR0, reg); + reg =3D c->gicr_ipendr0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= SPENDR0, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CACTIVER0, reg); + reg =3D c->gicr_iactiver0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= SACTIVER0, reg); + + for (i =3D 0; i < GIC_INTERNAL; i +=3D 4) { + reg =3D c->gicr_ipriorityr[i] | + (c->gicr_ipriorityr[i + 1] << 8) | + (c->gicr_ipriorityr[i + 2] << 16) | + (c->gicr_ipriorityr[i + 3] << 24); + hv_gic_set_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, reg); + } + } + + /* s->enable bitmap -> GICD_ISENABLERn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0 + , HV_GIC_DISTRIBUTOR_REG_GICD_ICENABLER0, s->enabled); + + /* s->group bitmap -> GICD_IGROUPRn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0 + , 0, s->group); + + /* Restore targets before pending to ensure the pending state is set on + * the appropriate CPU interfaces in the kernel + */ + + /* s->gicd_irouter[irq] -> GICD_IROUTERn */ + for (i =3D GIC_INTERNAL; i < s->num_irq; i++) { + uint32_t offset =3D HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32 + (8 * i) + - (8 * GIC_INTERNAL); + hv_gic_set_distributor_reg(offset, s->gicd_irouter[i]); + } + + + /* + * s->trigger bitmap -> GICD_ICFGRn + * (restore configuration registers before pending IRQs so we treat + * level/edge correctly) + */ + hvf_dist_put_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0, s->ed= ge_trigger); + + /* s->pending bitmap -> GICD_ISPENDRn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0, + HV_GIC_DISTRIBUTOR_REG_GICD_ICPENDR0, s->pending); + + /* s->active bitmap -> GICD_ISACTIVERn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0, + HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0, s->active); + + /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ + hvf_dist_put_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0, s->g= icd_ipriority); + + /* CPU interface state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + int num_pri_bits; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, c->icc_sre_el1); + + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1, + c->icc_ctlr_el1[GICV3_NS]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1, + c->icc_igrpen[GICV3_G0]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1, + c->icc_igrpen[GICV3_G1NS]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1, c->icc_pmr_el1); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1, c->icc_bpr[GICV3= _G0]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1, c->icc_bpr[GICV3= _G1NS]); + + num_pri_bits =3D ((c->icc_ctlr_el1[GICV3_NS] & + ICC_CTLR_EL1_PRIBITS_MASK) >> + ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; + + switch (num_pri_bits) { + case 7: + reg64 =3D c->icc_apr[GICV3_G0][3]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3, reg64); + reg64 =3D c->icc_apr[GICV3_G0][2]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2, reg64); + /* fall through */ + case 6: + reg64 =3D c->icc_apr[GICV3_G0][1]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1, reg64); + /* fall through */ + default: + reg64 =3D c->icc_apr[GICV3_G0][0]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1, reg64); + } + + switch (num_pri_bits) { + case 7: + reg64 =3D c->icc_apr[GICV3_G1NS][3]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3, reg64); + reg64 =3D c->icc_apr[GICV3_G1NS][2]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2, reg64); + /* fall through */ + case 6: + reg64 =3D c->icc_apr[GICV3_G1NS][1]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1, reg64); + /* fall through */ + default: + reg64 =3D c->icc_apr[GICV3_G1NS][0]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, reg64); + } + } +} + +static void hvf_gicv3_get(GICv3State *s) +{ + uint64_t reg, redist_typer; + int ncpu, i; + + hvf_gicv3_check(s); + + hv_vcpu_t vcpu0 =3D s->cpu[0].cpu->accel->fd; + hv_gic_get_redistributor_reg(vcpu0, + HV_GIC_REDISTRIBUTOR_REG_GICR_TYPER, &redist_typer); + + hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, ®); + s->gicd_ctlr =3D reg; + + /* Redistributor state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_IGROUPR0, ®); + c->gicr_igroupr0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ISENABLER0, ®); + c->gicr_ienabler0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ICFGR1, ®); + c->edge_trigger =3D half_unshuffle32(reg >> 1) << 16; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ISPENDR0, ®); + c->gicr_ipendr0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ISACTIVER0, ®); + c->gicr_iactiver0 =3D reg; + + for (i =3D 0; i < GIC_INTERNAL; i +=3D 4) { + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, ®); + c->gicr_ipriorityr[i] =3D extract32(reg, 0, 8); + c->gicr_ipriorityr[i + 1] =3D extract32(reg, 8, 8); + c->gicr_ipriorityr[i + 2] =3D extract32(reg, 16, 8); + c->gicr_ipriorityr[i + 3] =3D extract32(reg, 24, 8); + } + } + + if (redist_typer & GICR_TYPER_PLPIS) { + error_report("ITS is not supported on HVF."); + abort(); + } + + /* GICD_IGROUPRn -> s->group bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0, s->group); + + /* GICD_ISENABLERn -> s->enabled bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0, s->enabled); + + /* GICD_ISPENDRn -> s->pending bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0, s->pending); + + /* GICD_ISACTIVERn -> s->active bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0, s->active); + + /* GICD_ICFGRn -> s->trigger bitmap */ + hvf_dist_get_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0 + , s->edge_trigger); + + /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ + hvf_dist_get_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0 + , s->gicd_ipriority); + + /* GICD_IROUTERn -> s->gicd_irouter[irq] */ + for (i =3D GIC_INTERNAL; i < s->num_irq; i++) { + uint32_t offset =3D HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32 + + (8 * i) - (8 * GIC_INTERNAL); + hv_gic_get_distributor_reg(offset, &s->gicd_irouter[i]); + } + + /* CPU interface state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + int num_pri_bits; + + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, &c->icc_sre_el1); + + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1, + &c->icc_ctlr_el1[GICV3_NS]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1, + &c->icc_igrpen[GICV3_G0]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1, + &c->icc_igrpen[GICV3_G1NS]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1 + , &c->icc_pmr_el1); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1 + , &c->icc_bpr[GICV3_G0]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1 + , &c->icc_bpr[GICV3_G1NS]); + num_pri_bits =3D ((c->icc_ctlr_el1[GICV3_NS] & + ICC_CTLR_EL1_PRIBITS_MASK) >> + ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; + + switch (num_pri_bits) { + case 7: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3 + , &c->icc_apr[GICV3_G0][3]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2 + , &c->icc_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1 + , &c->icc_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + , &c->icc_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3 + , &c->icc_apr[GICV3_G1NS][3]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2 + , &c->icc_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1 + , &c->icc_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + , &c->icc_apr[GICV3_G1NS][0]); + } + } +} + +static void hvf_gicv3_set_irq(void *opaque, int irq, int level) +{ + GICv3State *s =3D (GICv3State *)opaque; + if (irq > s->num_irq) { + return; + } + hv_gic_set_spi(GIC_INTERNAL + irq, !!level); +} + +static void hvf_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3State *s; + GICv3CPUState *c; + + c =3D (GICv3CPUState *)env->gicv3state; + s =3D c->gic; + + c->icc_pmr_el1 =3D 0; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; + + c->icc_sre_el1 =3D 0x7; + memset(c->icc_apr, 0, sizeof(c->icc_apr)); + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); + + if (s->migration_blocker) { + return; + } + + /* Initialize to actual HW supported configuration */ + hv_gic_get_icc_reg(c->cpu->accel->fd, + HV_GIC_ICC_REG_CTLR_EL1, &c->icc_ctlr_el1[GICV3_NS]); + + c->icc_ctlr_el1[GICV3_S] =3D c->icc_ctlr_el1[GICV3_NS]; +} + +static void hvf_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + HVFARMGICv3Class *kgc =3D HVF_GICV3_GET_CLASS(s); + + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj, type); + } + + hvf_gicv3_put(s); +} + + +/* + * CPU interface registers of GIC needs to be reset on CPU reset. + * For the calling arm_gicv3_icc_reset() on CPU reset, we register + * below ARMCPRegInfo. As we reset the whole cpu interface under single + * register reset, we define only one register of CPU interface instead + * of defining all the registers. + */ +static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { + { .name =3D "ICC_CTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 4, + /* + * If ARM_CP_NOP is used, resetfn is not called, + * So ARM_CP_NO_RAW is appropriate type. + */ + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, + .readfn =3D arm_cp_read_zero, + .writefn =3D arm_cp_write_ignore, + /* + * We hang the whole cpu interface reset routine off here + * rather than parcelling it out into one little function + * per register + */ + .resetfn =3D hvf_gicv3_icc_reset, + }, +}; + +static void hvf_gicv3_realize(DeviceState *dev, Error **errp) +{ + GICv3State *s =3D HVF_GICV3(dev); + HVFARMGICv3Class *kgc =3D HVF_GICV3_GET_CLASS(s); + Error *local_err =3D NULL; + int i; + + kgc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by HVF"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, hvf_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); + + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + } + + if (s->maint_irq && s->maint_irq !=3D HV_GIC_INT_MAINTENANCE) { + error_setg(errp, "vGIC maintenance IRQ mismatch with the hardcoded= one in HVF."); + return; + } +} + +static void hvf_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + HVFARMGICv3Class *kgc =3D HVF_GICV3_CLASS(klass); + + agcc->pre_save =3D hvf_gicv3_get; + agcc->post_load =3D hvf_gicv3_put; + + device_class_set_parent_realize(dc, hvf_gicv3_realize, + &kgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, hvf_gicv3_reset_hold, NUL= L, + &kgc->parent_phases); +} + +static const TypeInfo hvf_arm_gicv3_info =3D { + .name =3D TYPE_HVF_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D hvf_gicv3_class_init, + .class_size =3D sizeof(HVFARMGICv3Class), +}; + +static void hvf_gicv3_register_types(void) +{ + type_register_static(&hvf_arm_gicv3_info); +} + +type_init(hvf_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3137521a4a..f446e966e3 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -42,6 +42,7 @@ specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('a= rm_gicv3_cpuif_common.c specific_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.= c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_true: files('= arm_gicv3_hvf.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 05/15] hvf: save/restore Apple GIC state Date: Mon, 28 Jul 2025 07:56:51 +0200 Message-Id: <20250728055701.38975-6-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX4/8orIypeOx4 EiIR4IYF5mGWHJn6R7Dup+zo3WDLzHv+FES0kBE9ZJ7KcsLAGC8rrm0af+BMsBoZZeEWIQ0mfKP HkCeIWHYAyc4v/lZNzUk2XgaXpRHRdKMliEzOD7Jbd22eYYmY+iPIkCycx5HDz8ni97h3CVwQmH jOiCIFka4Gl1cDZJPGfJgXzmHAYTvMqZPkLYwZq7DQCGSQtzfykDohhFK4olAfRBUap3a0MGDgq dE5wWmIcMbup1Yv91PtM6QNOrdmYDmsn6tTOoiHpLriuPvWdkAM1UHsTtOzF99v8ciFTdVXBQ= X-Proofpoint-GUID: CVCjsihdzAaxyLqjKEbH8s1Hc_mg_OfT X-Proofpoint-ORIG-GUID: CVCjsihdzAaxyLqjKEbH8s1Hc_mg_OfT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 clxscore=1030 mlxscore=0 bulkscore=0 phishscore=0 malwarescore=0 spamscore=0 mlxlogscore=820 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.138; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682432473116600 Content-Type: text/plain; charset="utf-8" On HVF, some of the GIC state is in an opaque Apple-provided structure. Save/restore that state to be able to save/restore VMs. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 73 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 7beb47caad..766b35f937 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -22,6 +22,7 @@ #include "cpu-sysregs.h" =20 #include +#include =20 #include "system/address-spaces.h" #include "system/memory.h" @@ -2169,15 +2170,83 @@ static const VMStateDescription vmstate_hvf_vtimer = =3D { }, }; =20 +/* Apple specific opaque state for the vGIC */ + +typedef struct HVGICState { + void *state; + uint32_t size; +} HVGICState; + +static HVGICState gic; + +static int hvf_gic_opaque_state_get(void) +{ + hv_gic_state_t gic_state; + hv_return_t err; + size_t size; + + gic_state =3D hv_gic_state_create(); + if (gic_state =3D=3D NULL) { + error_report("hvf: vgic: failed to create hv_gic_state_create."); + return 1; + } + err =3D hv_gic_state_get_size(gic_state, &size); + gic.size =3D size; + if (err !=3D HV_SUCCESS) { + error_report("hvf: vgic: failed to get GIC state size."); + return 1; + } + gic.state =3D malloc(gic.size); + err =3D hv_gic_state_get_data(gic_state, gic.state); + if (err !=3D HV_SUCCESS) { + error_report("hvf: vgic: failed to get GIC state."); + return 1; + } + return 0; +} + +static int hvf_gic_opaque_state_set(void) +{ + hv_return_t err; + if (!gic.size) { + return 0; + } + err =3D hv_gic_set_state(gic.state, gic.size); + if (err !=3D HV_SUCCESS) { + error_report("hvf: vgic: failed to restore GIC state."); + return 1; + } + return 0; +} + +static const VMStateDescription vmstate_hvf_gic =3D { + .name =3D "hvf-gic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(size, HVGICState), + VMSTATE_VBUFFER_UINT32(state, + HVGICState, 0, 0, + size), + VMSTATE_END_OF_LIST() + }, +}; + static void hvf_vm_state_change(void *opaque, bool running, RunState state) { HVFVTimer *s =3D opaque; =20 if (running) { + if (hvf_irqchip_in_kernel()) { + hvf_gic_opaque_state_set(); + } /* Update vtimer offset on all CPUs */ hvf_state->vtimer_offset =3D mach_absolute_time() - s->vtimer_val; cpu_synchronize_all_states(); } else { + if (hvf_irqchip_in_kernel()) { + hvf_gic_opaque_state_get(); + } /* Remember vtimer value on every pause */ s->vtimer_val =3D hvf_vtimer_val_raw(); } @@ -2187,6 +2256,10 @@ int hvf_arch_init(void) { hvf_state->vtimer_offset =3D mach_absolute_time(); vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); + if (hvf_irqchip_in_kernel()) { + gic.size =3D 0; + vmstate_register(NULL, 0, &vmstate_hvf_gic, &gic); + } qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); =20 hvf_arm_init_debug(); --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 06/15] hw/arm, target/arm: nested virtualisation on HVF Date: Mon, 28 Jul 2025 07:56:52 +0200 Message-Id: <20250728055701.38975-7-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfXw6HqDUGTxeGg Fp3cdVchNRHhhRUpqVhXPGQn82Tv6ZbnndEI/ng1IcDGpuO/gS32iaJoS+DI1GVmMJSGeaybnil EOTRwMI1p8Ui6viosO8JjIMsYbhCchPwoRAo8zQ5ozxpQzCpFdilQkkKoCoKo2GPyUo5y7IpKU/ ScPf6G9nqF3+arEmMSxjYPmCAU4Nge+n8HLfaPspIkIqn3DZzxfMt2GMO04U93noYmv83Wgu4iw K31ysfmCPAoSDqOk0uMtHZ2L013U2ZDNYnTCvZuSAwAzUbOMP2kXsCamGCkZo4GC83DCaWlcw= X-Proofpoint-ORIG-GUID: dCgXuImNEvU1nvDgGDUTkJGZZAVClWeo X-Proofpoint-GUID: dCgXuImNEvU1nvDgGDUTkJGZZAVClWeo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 clxscore=1030 spamscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.152; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682701107116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni --- hw/arm/virt.c | 9 ++++++--- target/arm/hvf-stub.c | 15 +++++++++++++++ target/arm/hvf/hvf.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/hvf_arm.h | 3 +++ 4 files changed, 59 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7da1176cda..7348d55104 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -817,8 +817,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) g_assert_not_reached(); } =20 - if (kvm_enabled() && vms->virt && - (revision !=3D 3 || !kvm_irqchip_in_kernel())) { + if (kvm_enabled() && vms->virt && (revision !=3D 3 || !kvm_irqchip_in_= kernel())) { error_report("KVM EL2 is only supported with in-kernel GICv3"); exit(1); } @@ -2279,7 +2278,8 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled())= { + if (vms->virt && !kvm_enabled() && !tcg_enabled() + && !hvf_enabled() && !qtest_enabled()) { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", current_accel_name()); @@ -2549,6 +2549,9 @@ static void virt_set_virt(Object *obj, bool value, Er= ror **errp) VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 vms->virt =3D value; +#if defined(CONFIG_HVF) && defined(__aarch64__) + hvf_arm_el2_enable(value); +#endif } =20 static bool virt_get_highmem(Object *obj, Error **errp) diff --git a/target/arm/hvf-stub.c b/target/arm/hvf-stub.c index ff137267a0..95ec4ea62f 100644 --- a/target/arm/hvf-stub.c +++ b/target/arm/hvf-stub.c @@ -18,3 +18,18 @@ uint32_t hvf_arm_get_max_ipa_bit_size(void) { g_assert_not_reached(); } + +bool hvf_arm_el2_supported(void) +{ + g_assert_not_reached(); +} + +bool hvf_arm_el2_enabled(void) +{ + g_assert_not_reached(); +} + +void hvf_arm_el2_enable(bool) +{ + g_assert_not_reached(); +} diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 766b35f937..5b9865b569 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -27,6 +27,7 @@ #include "system/address-spaces.h" #include "system/memory.h" #include "hw/boards.h" +#include "hw/arm/virt.h" #include "hw/irq.h" #include "qemu/main-loop.h" #include "system/cpus.h" @@ -892,6 +893,10 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) (1ULL << ARM_FEATURE_PMU) | (1ULL << ARM_FEATURE_GENERIC_TIMER); =20 + if (hvf_arm_el2_enabled()) { + ahcf->features |=3D 1ULL << ARM_FEATURE_EL2; + } + /* We set up a small vcpu to extract host registers */ =20 if (hv_vcpu_create(&fd, &exit, NULL) !=3D HV_SUCCESS) { @@ -965,6 +970,25 @@ uint32_t hvf_arm_get_max_ipa_bit_size(void) return round_down_to_parange_bit_size(max_ipa_size); } =20 +bool hvf_arm_el2_supported(void) +{ + bool is_nested_virt_supported; + hv_return_t ret =3D hv_vm_config_get_el2_supported(&is_nested_virt_sup= ported); + assert_hvf_ok(ret); + return is_nested_virt_supported; +} + +static bool is_nested_virt_enabled =3D false; +bool hvf_arm_el2_enabled(void) +{ + return is_nested_virt_enabled; +} + +void hvf_arm_el2_enable(bool enable) +{ + is_nested_virt_enabled =3D enable; +} + void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) { if (!arm_host_cpu_features.dtb_compatible) { @@ -1001,6 +1025,13 @@ hv_return_t hvf_arch_vm_create(MachineState *ms, uin= t32_t pa_range) } chosen_ipa_bit_size =3D pa_range; =20 + if (hvf_arm_el2_enabled()) { + ret =3D hv_vm_config_set_el2_enabled(config, true); + if (ret !=3D HV_SUCCESS) { + goto cleanup; + } + } + ret =3D hv_vm_create(config); if (hvf_irqchip_in_kernel()) { /* @@ -1147,6 +1178,10 @@ static bool hvf_handle_psci_call(CPUState *cpu) int target_el =3D 1; int32_t ret =3D 0; =20 + if (hvf_arm_el2_enabled()) { + target_el =3D 2; + } + trace_hvf_psci_call(param[0], param[1], param[2], param[3], arm_cpu_mp_affinity(arm_cpu)); =20 diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea82f2691d..bf55e7ae28 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -24,5 +24,8 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 uint32_t hvf_arm_get_default_ipa_bit_size(void); uint32_t hvf_arm_get_max_ipa_bit_size(void); +bool hvf_arm_el2_supported(void); +bool hvf_arm_el2_enabled(void); +void hvf_arm_el2_enable(bool); =20 #endif --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682752; cv=none; d=zohomail.com; s=zohoarc; b=cj1o5urNcMqbJo5VEJPdPCHfSSesTAHpWlZWk03DNwVCOTkh7ACvHfUx224yeveETy72EfI8BkU+UoTF+X8mw/L2hoIl0JglNd3nkFBTZ3hsy3Bug9yy2y1u1wkQ/oyoxezjnMvZCBDWa5m8rsb6PVQAuLs8m/ckCmScjkhEaTQ= ARC-Message-Signature: i=1; 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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 07/15] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Date: Mon, 28 Jul 2025 07:56:53 +0200 Message-Id: <20250728055701.38975-8-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfXwfFC5Uxw4ZIG jts1X3AyoTCSUEs2t7wYEvXbBGfXE6aNKCpJxad1uKjzBZHbqZ/KUwIcf/WcxuVoMkftG2rYCGe PEIfBkZ+8/ArhoWvn53GGorHcNTrjOK3frDd5tsAbkKgEeNQuWlkho0BWeVrP2Wwdg22AcYeBJX FGbaWdyiGdjBo96V92K2N64+bA4Iv+xaB4HyY8clOQsqJ0YSlSUx60FLcSwoFHw9ZuBbWz2173+ XdDUHdlhpMgHnL+BmXM1Lt9yegqIwsQa/fHdnHaL8c6QvG3luPPdID+8E4709sDWw3OR11Xfw= X-Proofpoint-ORIG-GUID: iuyx2U-TI4x5mjG90OO6J3ir_dC07rDQ X-Proofpoint-GUID: iuyx2U-TI4x5mjG90OO6J3ir_dC07rDQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 clxscore=1030 bulkscore=0 adultscore=0 mlxlogscore=676 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.142; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682753267116600 Content-Type: text/plain; charset="utf-8" HVF traps accesses to CNTHCTL_EL2. For nested guests, HVF traps accesses to= MDCCINT_EL1. Pass through those accesses to the Hypervisor.framework library. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 5b9865b569..63b7967053 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -297,6 +297,10 @@ void hvf_arm_init_debug(void) #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) =20 +/* EL2 registers */ +#define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0) +#define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0) + #define WFX_IS_WFE (1 << 0) =20 #define TMR_CTL_ENABLE (1 << 0) @@ -1392,6 +1396,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t r= eg, uint64_t *val) case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; + case SYSREG_CNTHCTL_EL2: + assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); + return 0; + case SYSREG_MDCCINT_EL1: + assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1712,6 +1722,12 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t = reg, uint64_t val) case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; + case SYSREG_CNTHCTL_EL2: + assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); + return 0; + case SYSREG_MDCCINT_EL1: + assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); + return 0; case SYSREG_LORC_EL1: /* Dummy register */ return 0; --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682432; cv=none; d=zohomail.com; s=zohoarc; b=mFofC+v18AxlhhSNe0VySkJQt+YEkSJ07ptz/8vMQPbQUStDerxu0/sNmCSYvaELnTnF38KXFQ32xsPnvozpJHCnvP0mxUy+ADqvxQD1SkUxuDVVrgWt0bHOlxn0oMyz/GyE8Z+pYz8Ll2ST01sxfoo+KxHQabqzoZ9epYB70Zo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682432; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q7xD0GY8k1Hk4vFR23J6NN3+mR0YZXy/rA40WkfECXE=; b=ixdk1jlIDbDvq3xRA7x6hoWzClg/6V5/cj2Z/at53rtTXA8VcpQCk9EY8i9UdGPjqzbJ1OBQZ79a+1w92Nrh6iA66THNfJACU53CuZA4w1wRJotqUFr4L7qDAR0AfqwsBU7OJbhInSzOtW5Vp2bfNS4IzSFmMmWHiMHI8E00I2s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175368243232578.57351423839657; Sun, 27 Jul 2025 23:00:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGsk-00005Q-GK; Mon, 28 Jul 2025 01:58:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrV-0007Gp-Ih for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:28 -0400 Received: from p-east3-cluster5-host2-snip4-1.eps.apple.com ([57.103.86.142] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrS-0007E0-VS for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:24 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id 36BDE180014C; Mon, 28 Jul 2025 05:57:21 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id 4AA4B1800107; Mon, 28 Jul 2025 05:57:19 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=q7xD0GY8k1Hk4vFR23J6NN3+mR0YZXy/rA40WkfECXE=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=J0O0aj9WRyuZ1wty2i0pJi8av1bdM10jCnhEMUBR0qeRQm5kTKoclDZj75PTK0W1F1HK+/wqzl4J21dNNF1O7ifvmJfsdrZPpd/PVulP2FCBGEsBDCTZ+b5HEJ9bJkc9/4l3ZKW4LCCynSkxYq0+hX4XEK01YWqFpexORJsHCAU3YPFozC1iShP2dZ7i4oDQOhfNiXwalzJg7AUrEfyoZ+kp0dlJkaJeUq7GkNlKCzWUIu9i4IjpTlbNOxTRgQp/MXFHGcktokzj1sTC8WnIKcG3hMsZdf5sJUivZFWQlmCPRLXSQvO5SBPqL70VTVLxPCVJhb9sASFgtIuLXvHTEg== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 08/15] hw/arm: virt: add GICv2m for the case when ITS is not available Date: Mon, 28 Jul 2025 07:56:54 +0200 Message-Id: <20250728055701.38975-9-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: WmP-4RsTOlDqrSZzI1WqltD8Sb_6DMh0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX4eGybyWPzh4n aOW505ZrogNq49/hLxrF0/eYvMZ+NIp04YJvFtWN6U5MchnwfqDuETF++BfEviiknt47eiHqRBG t39cUhU5ULnJiemTAmXtaRBS8zVC4pvTwBghBMr7/tMlw/lxJTw36DT3jW0/2GtEuEhHecoM+R0 Sy8XcI2praX1cOq/fJ/1nm1uS242gscK2bj6IT4VdlRwkly4HCErylAKnsZL628guCx5MmEHnyA XMTd/2vpCYaCgvqAQ6Tkhhjb7B9li0kw2PxG+1korkrC2Dmkk6Jo61t7g0EBuD3KwG+a5/xmc= X-Proofpoint-GUID: WmP-4RsTOlDqrSZzI1WqltD8Sb_6DMh0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 mlxlogscore=999 malwarescore=0 mlxscore=0 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.142; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682433916116600 Content-Type: text/plain; charset="utf-8" On Hypervisor.framework for macOS and WHPX for Windows, the provided enviro= nment is a GICv3 without ITS. As such, support a GICv3 w/ GICv2m for that scenario. Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 4 +++- hw/arm/virt.c | 8 ++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b01fc4f8ef..969fa3f686 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -848,7 +848,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } - } else { + } + + if (!vms->its && !vms->no_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7348d55104..91d8cd9363 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -953,6 +953,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { create_its(vms); + } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { + create_v2m(vms); } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { create_v2m(vms); } @@ -2408,6 +2410,8 @@ static void machvirt_init(MachineState *machine) vms->ns_el2_virt_timer_irq =3D ns_el2_virt_timer_present() && !vmc->no_ns_el2_virt_timer_irq; =20 + vms->no_gicv3_with_gicv2m =3D vmc->no_gicv3_with_gicv2m; + fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); =20 @@ -3419,6 +3423,7 @@ static void virt_instance_init(Object *obj) vms->its =3D true; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; + vms->no_gicv3_with_gicv2m =3D false; =20 /* Default disallows iommu instantiation */ vms->iommu =3D VIRT_IOMMU_NONE; @@ -3471,8 +3476,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(10, 1) =20 static void virt_machine_10_0_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_10_1_options(mc); compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len); 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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 09/15] target/arm: hvf: use LOG_UNIMP for CNTP_CVAL_EL0/SYSREG_CNTP_CTL_EL0 Date: Mon, 28 Jul 2025 07:56:55 +0200 Message-Id: <20250728055701.38975-10-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 7AWGEd_kSgvYu7mHfxrrph9dNdbn2vvq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX07q5cpUqu9bp 3uvHUx+ZJf976VXZ9oZVB/bc2RtQFWsUlP6xD9ZuecwaWEbDJgYb8thaIaHwRyBFDr08RNB9sbK vMtJeBtPtzX6MROshVuaP7AZoP4Lnqn9ZI0SRVWgiW+jUhOAc/32yIFfl22N1CtaB/FvBL4pIoM dCSm3zvJgHz1H9pRiJu8ELKPpInXFqVCvWaGpg0L2DTwqCDmk4JNnEnsbC0zRdNrJi77WjUhb6k pDIHVEak3yfyMvFtAs0j1xlKuGDQgBfe4nr4pzmDdvAzDoPr46GOTQYOKbPoiCkZ/CharEvMg= X-Proofpoint-GUID: 7AWGEd_kSgvYu7mHfxrrph9dNdbn2vvq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 mlxlogscore=617 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1030 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.144; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682959234116600 Content-Type: text/plain; charset="utf-8" Instead of considering reads there to be fatal, mark it as unimplemented. This is to allow experimentation on using configurations other than the App= le vGIC. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 63b7967053..f17fb0695a 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -300,6 +300,7 @@ void hvf_arm_init_debug(void) /* EL2 registers */ #define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0) #define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0) +#define SYSREG_CNTP_CVAL_EL0 SYSREG(3, 3, 14, 2, 2) =20 #define WFX_IS_WFE (1 << 0) =20 @@ -1399,6 +1400,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t r= eg, uint64_t *val) case SYSREG_CNTHCTL_EL2: assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); return 0; + case SYSREG_CNTP_CTL_EL0: + qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CTL_EL0\n"); + return 0; + case SYSREG_CNTP_CVAL_EL0: + qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CVAL_EL0\n"); + return 0; case SYSREG_MDCCINT_EL1: assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); return 0; @@ -1719,6 +1726,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) */ qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CTL_EL0\n"); return 0; + case SYSREG_CNTP_CVAL_EL0: + qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CVAL_EL0\n"); + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682420; cv=none; d=zohomail.com; s=zohoarc; b=ER/zaayLICfmPhYxlmC79ug3e75gNOal1HpSlINeDOidZY/iMfAPT2AsyZJwXF7gsRKnHI1eOqY/YPC7kH1uOI3OXBORfRlOsvdTClTU7D/Gdj0afONC+c+uxo4KHZ7y95tOnV9BXBxllgMvebpokKZVFBqxFKBJLqgWgKywtHM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682420; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=S3ZBNHI1pU1dOel9dX+AYwGkdx57h3gION5nK4yFHyQ=; b=jIn/luZOvrlWqjxaYxdtWRlS4dahARihVvxtj387fnhkQdQq53xo/zQ9aChn5c4Q5hdYAFJv/sgfbw67S7F4RjLiXpQWR+6YbwFfp7c6Y5ygeSvHnnhJ/NyRZCdZkjx8XacXu9bm1VW+TTiDch140z4rgklLinjxYR/Zf1zG6FM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753682419761348.8221683768643; Sun, 27 Jul 2025 23:00:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGtC-0000yo-O2; Mon, 28 Jul 2025 01:59:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrZ-0007J1-Cp for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:30 -0400 Received: from p-east3-cluster6-host11-snip4-10.eps.apple.com ([57.103.85.241] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrX-0007FD-4C for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:29 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id DBBC71800107; Mon, 28 Jul 2025 05:57:24 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id DAD361800139; Mon, 28 Jul 2025 05:57:22 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=S3ZBNHI1pU1dOel9dX+AYwGkdx57h3gION5nK4yFHyQ=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=XfespWzdNxMbHSC06EWwbwLonyZAkdZWTxAEaDWD672+aY7Maw8LOqyc/pyzLqEOQMecdmYdim60tbA2OFuaclVok0xCPEZciJ5BhWys0iuOiforjsTJEWdCrGnvdVPwiRbExOhuJG7MPtzM/f4pTkB2c+MUNSi0T+pMZeXXWXLXwUApbuisDTI57wEYVG8IXZxmvIltvjZEdqcT2TcP+ml1toDni0GhB44zgumc0o2YZcqV3d1dHRRo0mfpVCQDSBE/VuJ9nK2SOyVYkLvvOtaRwfui3nfUS/RWlvRQF567yIy2jgv2S+hX+r0fR7+dOruURE/Xgvo//oUPliky/w== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 10/15] hw/arm: virt: cleanly fail on attempt to use the platform vGIC together with ITS Date: Mon, 28 Jul 2025 07:56:56 +0200 Message-Id: <20250728055701.38975-11-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: rFjSwuNaRyaY7ZzVL56WM8XNBBq-EynG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfXx6JuD9XF/zEu LgyFWgKV6ia0No0E5lkbm4Ltw4bvP3zZkfhFQKhAwAX2cGD2aH1efV48bppFrL+adMK0mOr0wZz okCF6K1G5YPIxz78v95m60z8mt3aPviXeYxoKtOppMQIGSO+OVxlzH5fqBTGnDP1vy4/nmvhPBn Te0FPkyAeHCh+BhLPdrwd2pZw6g8D/kWXSg6y2tPoSm1YvmHpbhdGrTRP/EBW5Zk4mIOyZDC+8O DZEJijq9YR2Rifj5ETZDHyzh7a970CXQoCtGTmtkw/G3XzM+BAzGyhsTW8T9AVfJ8xCWDFYKQ= X-Proofpoint-ORIG-GUID: rFjSwuNaRyaY7ZzVL56WM8XNBBq-EynG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=881 malwarescore=0 clxscore=1030 mlxscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.85.241; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682422411116600 Content-Type: text/plain; charset="utf-8" Apple's platform vGIC doesn't support ITS. Deal with this by reporting to t= he user and not creating the ITS device. Signed-off-by: Mohamed Mediouni --- hw/arm/virt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 91d8cd9363..005e923a22 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -740,6 +740,16 @@ static void create_its(VirtMachineState *vms) return; } =20 + if (hvf_enabled() && hvf_irqchip_in_kernel() && vms->tcg_its) { + /* + * In the HVF case, inform the user that they can use the + * user-mode GIC if they want to have an ITS. + */ + info_report("ITS not supported without kernel-irqchip=3Doff on HVF= "); + info_report("Disabling ITS"); + return; + } + dev =3D qdev_new(its_class_name()); =20 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682748; cv=none; d=zohomail.com; s=zohoarc; b=LEZCn6eT3o5fhAouEOj35UDIztw0Zdr+4OjGG7JfQ9bhvq5vlXyucVOxd5dVe8k33MNDGkjc9DeAbWFYf9k7MhvbiqP08RWDA4S/2Acx2QkZbZEMWfFOBfBaHEjiLDd6vWnU4z3IpEaRwbPhgWq79WIy9vduUN5g3+IBFNpD1ks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682748; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+I0eS72KXDJ7+FwHhj/Ya3f5pWsr6GfQlGxIXf2fQwQ=; b=I8AQCJyIoYDXpPIrpTSnXoB7CsOYncu/M0pyBAfgVMFRSXRwhu4p61ANVGaq8V6w4zhFRWzFqDAr42cCMqJCCDoXZwxS21ExnXCC4V7mYI/l4bRPQr3Pxof5O3iKGwygjNd9/VGVFSZrirFJj1iO8nAjXakTlOocu59h3CsA09Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753682748564708.3935774128879; Sun, 27 Jul 2025 23:05:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGtM-0001Eg-0h; Mon, 28 Jul 2025 01:59:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGre-0007LZ-HB for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:39 -0400 Received: from p-east3-cluster2-host12-snip4-10.eps.apple.com ([57.103.87.251] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrb-0007GL-Kn for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:34 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id 415D71800155; Mon, 28 Jul 2025 05:57:27 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id ACAB418000AA; Mon, 28 Jul 2025 05:57:24 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=+I0eS72KXDJ7+FwHhj/Ya3f5pWsr6GfQlGxIXf2fQwQ=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=BWWcUbf+sGAbVsTGuGEP0nIOMjKtHT1UpS4AgCaY0wvR0c4RTk/nTDhEaM552zzYeKYaOVSWiMv3/M+J7XH+hhlBqG1gTpSBZcsBDpSdBCTxMHClK+nHflAXHWme4BAuaLLEf80yZc6hb7+VyKPByHAirPLww4idFGhfAeV7lsBIrzL85juYmvHHzV9VYaclB+OL2DPAMzerGm0u3DgOkN39wQMVO0OItqZHwWxD723eAGVokI+xoJMbnOvokD2Eh05Z/bOKFllvcZf5uUpZ330JHeN+qmWdMRXYZ0UjZjWs7vHkH68ynqNYYKwhbrQHwQ95R0ZYrlNaFqjU/AJrGg== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 11/15] hvf: only call hvf_sync_vtimer() when running without the platform vGIC Date: Mon, 28 Jul 2025 07:56:57 +0200 Message-Id: <20250728055701.38975-12-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX24jx4lGQZ/t5 Q8HxcvCZ392hwf6nnHnsAb+0Ut1RhO1eQ7dJJtINyW+5Rp7EvXdwLnU5o3BdWZu53DlQlnLWUvD cEQ9+oukqArPJuNDstk35SCY1baAH8UJ82eQ2REepJcdytve8myq0DEMajihPrIxie71ufDmAFB U6q1GMUWg7RSFknS8Z6z/QgKhjy9JhiUQer4S5rTa+SW4h7VjtSmgPfhZT84ktQx20pb4FKwp7F xTsHIg91aLSjtohTe+dW8omhTGDNG563UmLH9sXA5sTu4125KbNCC3tPFQ9QlOvfRECXBQ92Y= X-Proofpoint-GUID: F-ojjvsQmN_XwIwEbHaK64NV6kKvFFkz X-Proofpoint-ORIG-GUID: F-ojjvsQmN_XwIwEbHaK64NV6kKvFFkz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxscore=0 spamscore=0 phishscore=0 adultscore=0 clxscore=1030 mlxlogscore=890 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.251; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682749234116600 Content-Type: text/plain; charset="utf-8" When running with the Apple vGIC, the EL1 vtimer is handled by the platform. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f17fb0695a..afe09a216e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2047,7 +2047,8 @@ int hvf_vcpu_exec(CPUState *cpu) g_assert_not_reached(); } =20 - hvf_sync_vtimer(cpu); + if (!hvf_irqchip_in_kernel()) + hvf_sync_vtimer(cpu); =20 switch (ec) { case EC_SOFTWARESTEP: { --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682781; cv=none; d=zohomail.com; s=zohoarc; b=MLU+2neS7T0rLu1yVWrLhE6YlT6hYDZuVwAaVqdpiqMMiKHjPU0HG47+oT+ZtnVH2Y+R9foU+tyAYJPfi4yK6k31WQ66cyQGq8lCG6zmgkiI47vFWcKxTeH9H/WvN3JtDpwhfUcYgxGUQ5gN+D6XUMp2UWpxgoaRLZXlwIDvuVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682781; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m5yjYmCYNH90EJVxeL8leflY4NUxU/PF6QRQfToy6ZU=; b=Zmce2AWvgTezhvFt5IM+u0ddImeC/UZlP5bmZD9pVrhOh3SAzAdyomQYsI+pYrIGCt3+tUXKWga/opu+VFFIB/s3YkpEfU5PN99XYDawvrhcYpbW6mUPcTuUyltLibSCNzrP4UwqfXr8C4h+qMyddKvGMehIFShnKDi10Ss+LOM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753682781613240.7916912340046; Sun, 27 Jul 2025 23:06:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGtD-00012P-Ud; Mon, 28 Jul 2025 01:59:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrd-0007Kf-49 for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:40 -0400 Received: from p-east3-cluster2-host5-snip4-10.eps.apple.com ([57.103.87.181] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGra-0007G9-C6 for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:32 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id 9AFED180010B; Mon, 28 Jul 2025 05:57:28 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id 84A16180014D; Mon, 28 Jul 2025 05:57:26 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=m5yjYmCYNH90EJVxeL8leflY4NUxU/PF6QRQfToy6ZU=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=GtVP/Hn4a3gb6NrP0/AUyXlE2uHvlMBVSVcOCkMTO2B1SX7Lp956zswwrlIKukImYASULWU5Tz7EwE3E9OH5TEVTFOV3JTjWIjzuoqmcj3I2V/5zY2VOq3+7NZ9rtvUJM541tPAQ8Axqx9hJFT1e38pfop3b6aqo6KJgHddbwzVeKkOPLev6N+GmvEZKM5imBHYuMGvUjBHFX6qFZGVKKyt2DtnCD658y+6vQT/mgGFsXoHwH91uR3mZr5u8M7r6agFJ9y7KyaYJtevqtzxecOtcg9Njco3MaBVrBMFO+uaECn3fOwfAp9QUpbLd852uyn0fYGGiBTAKM0UIWmSw8Q== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 12/15] target/arm: hvf: when the platform irqchip is used, abort on writes to the ptimer Date: Mon, 28 Jul 2025 07:56:58 +0200 Message-Id: <20250728055701.38975-13-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: G-F_arxhLC5Km0J3S-uywZB-6_5rMWji X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX6ZeKXeNqQPUP s0yUTurt/QKIuH+ZZPAio1Pxp5yyqsZMTm6Eh9npUAAZQV2KnKgwdVq5M+7i04/ri0sLgIUUElu srGygeK0XJO/3MpCbm8M7qpV2S43dWTd7hzafXe2HaztV4PBxd742hc2TN9WW5ib9Pw2PpCJmmx ddTNivNjTc+kVC8qPKFwjc7sIdSOKX6vjlcEAIewd/VM8wxeVd3ZO/wyThjm/+pqrhfCWnZvK2R S0I4/NbLkFGlnAuR+iSppBAKe230qgABkwA5sSa0MlkB29VTZnBxQze746fRDu2QqvTuCLgRU= X-Proofpoint-ORIG-GUID: G-F_arxhLC5Km0J3S-uywZB-6_5rMWji X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 bulkscore=0 mlxscore=0 mlxlogscore=584 spamscore=0 suspectscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.181; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -37 X-Spam_score: -3.8 X-Spam_bar: --- X-Spam_report: (-3.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682783759116600 Content-Type: text/plain; charset="utf-8" In that case, this code path should never be triggerable as timer emulation= is handled by the platform. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index afe09a216e..64cca9aa18 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1401,9 +1401,15 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t r= eg, uint64_t *val) assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); return 0; case SYSREG_CNTP_CTL_EL0: + if (hvf_irqchip_in_kernel()) { + abort(); + } qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CTL_EL0\n"); return 0; case SYSREG_CNTP_CVAL_EL0: + if (hvf_irqchip_in_kernel()) { + abort(); + } qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CVAL_EL0\n"); return 0; case SYSREG_MDCCINT_EL1: @@ -1720,6 +1726,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) env->cp15.oslsr_el1 =3D val & 1; return 0; case SYSREG_CNTP_CTL_EL0: + if (hvf_irqchip_in_kernel()) { + abort(); + } /* * Guests should not rely on the physical counter, but macOS emits * disable writes to it. Let it do so, but ignore the requests. @@ -1727,6 +1736,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CTL_EL0\n"); return 0; case SYSREG_CNTP_CVAL_EL0: + if (hvf_irqchip_in_kernel()) { + abort(); + } qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CVAL_EL0\n"); return 0; case SYSREG_OSDLR_EL1: --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753682756; cv=none; d=zohomail.com; s=zohoarc; b=KgleJ0kGYRIE5n5zaaTFe1vbiKmc67Jo3JKtaijPfYFQ5C0btlaSG3mezbomJZ24uw20PoezUdWo/TN3zvPDPU7kWR2itQp9Af7lmB+QQGJDi+HKi25pEpnCVnmUmyKXJ2DSoi3uAY3qjYvFAI1+JRjMVEKGlLd3DrP2dApJ4co= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753682756; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=y6mI8AmJ1dWdgen3Y4HML2fQWE3KY+VD1EyD//Qc2Zo=; b=QXF/vpk66Y3DT29j4oFDqLK/RyaClbeJwxFyY/kQlvGvOZAMjdAfyAemue9V2gBdOZKcJGzXJneaHjPRUvxAnIv7Qb+Vm5nVmkMviiAGX2A09YkzKacTOL1ojX4FpYq04sskFOzHfGLyRvI17/TMlIIx4vW19qpv0H4QsZjpPPA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753682756686491.67882265985054; Sun, 27 Jul 2025 23:05:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ugGtE-000133-Mg; Mon, 28 Jul 2025 01:59:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGrg-0007MP-1V for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:41 -0400 Received: from p-east3-cluster3-host2-snip4-6.eps.apple.com ([57.103.86.19] helo=outbound.qs.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ugGre-0007Gy-98 for qemu-devel@nongnu.org; Mon, 28 Jul 2025 01:57:35 -0400 Received: from outbound.qs.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPS id A66AC18000AA; Mon, 28 Jul 2025 05:57:30 +0000 (UTC) Received: from localhost.localdomain (qs-asmtp-me-k8s.p00.prod.me.com [17.57.155.37]) by p00-icloudmta-asmtp-us-east-2d-100-percent-7 (Postfix) with ESMTPSA id 64038180009A; Mon, 28 Jul 2025 05:57:28 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=y6mI8AmJ1dWdgen3Y4HML2fQWE3KY+VD1EyD//Qc2Zo=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=bPar//4VQb8tPifxBJ6DFGXXmdw2AMFIC9kJAU/0JP5g8DTGTFqJHUV95D+QtqhjBISTLsuGdhXFLNgC/+rmK5lh1vCtwKnFjBcgkG+7x5uNzoecMB75hRgnbtlZzSinJE6k06OBckbgQho85XNyvUzArnK1Qti0NCURTk6prhmfxlts6mlvJke9XOmqaZRv2UKQ4LsdFC4T7aFb26HUrJtWkSN77TxeIxWrpxfzmApb6hojWSVMqMuD5cV5i8HGnUTsAzSc2vkX99u3uc7inZWUuiVn66uWdu+j4BIyxYfFtCWbL8KfmG7jNMDFxWN0uDDcwPtZpK0oLVWGSh7V/w== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , Mads Ynddal , "Michael S. Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 13/15] hw/intc: hvf: sync state in c->ich* registers when virt on Date: Mon, 28 Jul 2025 07:56:59 +0200 Message-Id: <20250728055701.38975-14-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 9TPXBQzbmoXtYz68X5g5VPWXWVWc7f-j X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfX6qTXyYh7iTmm l2J51eimKbaGReSTF7ikrIXBTyVyO2aki5Yx2pEFrUQdSOR5UcqqZMdsyu2Fkl1dSfDm8bFouNj H4eNz230fAZGhsc8YRLCPMsHcTPhlhbmGhQ3uMOg7qCrNOZgaTMGHEgRwKtQ6H/DLBc7sB9Vvrx dpq+2GzwXfUXAAHC7ytxTaw2tVJC7t5CAwZliPmxXWIZF2zly+VOZjWTHS7PjKAv/17cBnzU1Ia UGFmvCGp6e6IG1IfZOZ8Xwnz+lvAI2Oyd+4WHJ15eVtyY2Cvo5lK4FA9oDV3dtloc7MRnRY+4= X-Proofpoint-GUID: 9TPXBQzbmoXtYz68X5g5VPWXWVWc7f-j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 mlxlogscore=884 malwarescore=0 mlxscore=0 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.19; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682757475116600 Content-Type: text/plain; charset="utf-8" Part of vGIC state to save/restore. Signed-off-by: Mohamed Mediouni --- hw/intc/arm_gicv3_hvf.c | 113 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/hw/intc/arm_gicv3_hvf.c b/hw/intc/arm_gicv3_hvf.c index a154b27318..30362540f2 100644 --- a/hw/intc/arm_gicv3_hvf.c +++ b/hw/intc/arm_gicv3_hvf.c @@ -15,6 +15,7 @@ #include "system/runstate.h" #include "system/hvf.h" #include "system/hvf_int.h" +#include "hvf_arm.h" #include "gicv3_internal.h" #include "vgic_common.h" #include "qom/object.h" @@ -315,6 +316,62 @@ static void hvf_gicv3_put(GICv3State *s) hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, reg64); } } + + /* Registers beyond this are with nested virt only */ + if (!hvf_arm_el2_enabled()) { + return; + } + + /* ICH */ + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + int num_pri_bits; + + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, + c->ich_vmcr_el2); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, + c->ich_hcr_el2); + + for (int i =3D 0; i < GICV3_LR_MAX; i++) { + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, + c->ich_lr_el2[i]); + } + + num_pri_bits =3D c->vpribits; + + switch (num_pri_bits) { + case 7: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3 + , c->ich_apr[GICV3_G0][3]); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2 + , c->ich_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1 + , c->ich_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + , c->ich_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3 + , c->ich_apr[GICV3_G1NS][3]); + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2 + , c->ich_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1 + , c->ich_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + , c->ich_apr[GICV3_G1NS][0]); + } + } } =20 static void hvf_gicv3_get(GICv3State *s) @@ -452,6 +509,62 @@ static void hvf_gicv3_get(GICv3State *s) , &c->icc_apr[GICV3_G1NS][0]); } } + + /* Registers beyond this are with nested virt only */ + if (!hvf_arm_el2_enabled()) { + return; + } + + /* ICH */ + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + int num_pri_bits; + + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, + &c->ich_vmcr_el2); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, + &c->ich_hcr_el2); + + for (int i =3D 0; i < GICV3_LR_MAX; i++) { + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, + &c->ich_lr_el2[i]); + } + + num_pri_bits =3D c->vpribits; + + switch (num_pri_bits) { + case 7: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3 + , &c->ich_apr[GICV3_G0][3]); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2 + , &c->ich_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1 + , &c->ich_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + , &c->ich_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3 + , &c->ich_apr[GICV3_G1NS][3]); + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2 + , &c->ich_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1 + , &c->ich_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_get_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + , &c->ich_apr[GICV3_G1NS][0]); + } + } } =20 static void hvf_gicv3_set_irq(void *opaque, int irq, int level) --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; 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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 14/15] hvf: sync registers used at EL2 Date: Mon, 28 Jul 2025 07:57:00 +0200 Message-Id: <20250728055701.38975-15-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: e_tlGfHcTSHBOT9iIJ4lR05UCTVD-jhM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfXzLiQVsLh8B5i qU2DXNtD1pU7ARJpcMEsA5Prj7dkt+AUCBLmi9p0WAb+9Xc/Kjk8mXQ0RThAiM9D5t7lOOab/wz eCo4KCBmnKbk4keEOx/oYjdCt0xAmDNifUZ7THAnNu+QS4Yvqsjozs4CmIHHcPU4znfQfiG85X9 VnUTo1TD2YyXhFVecics8uDrqsjenuTKBp6rJQO2CQLmasGTkKbDtSgHxKjoHjF3GEfZmhy5RWt TL8iZw1NfDzuzUK7ETHU4acgJEgXRhCAWlK3ezG6M1wQJqMv5+4wgSjR/LODvg3nE09Cw3Tjo= X-Proofpoint-ORIG-GUID: e_tlGfHcTSHBOT9iIJ4lR05UCTVD-jhM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=887 phishscore=0 clxscore=1030 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.27; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682461250116600 Content-Type: text/plain; charset="utf-8" When starting up the VM at EL2, more sysregs are available. Sync the state = of those. In addition, sync the state of the EL1 physical timer when the vGIC is used= , even if running at EL1. However, no OS running at EL1 is expected to use those r= egisters. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 64cca9aa18..af9bbe44ed 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -407,6 +407,8 @@ static const struct hvf_reg_match hvf_fpreg_match[] =3D= { struct hvf_sreg_match { int reg; uint32_t key; + bool vgic; + bool el2; uint32_t cp_idx; }; =20 @@ -552,6 +554,41 @@ static struct hvf_sreg_match hvf_sreg_match[] =3D { { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, + /* vGIC */ + { HV_SYS_REG_CNTP_CTL_EL0, HVF_SYSREG(14, 2, 3, 3, 1), true }, + { HV_SYS_REG_CNTP_CVAL_EL0, HVF_SYSREG(14, 2, 3, 3, 2), true }, +#ifdef SYNC_NO_RAW_REGS + { HV_SYS_REG_CNTP_TVAL_EL0, HVF_SYSREG(14, 2, 3, 3, 0), true}, +#endif + /* vGIC + EL2 */ + { HV_SYS_REG_CNTHCTL_EL2, HVF_SYSREG(14, 1, 3, 4, 0), true, true }, + { HV_SYS_REG_CNTHP_CVAL_EL2, HVF_SYSREG(14, 2, 3, 4, 2), true, true }, + { HV_SYS_REG_CNTHP_CTL_EL2, HVF_SYSREG(14, 2, 3, 4, 1), true, true }, +#ifdef SYNC_NO_RAW_REGS + { HV_SYS_REG_CNTHP_TVAL_EL2, HVF_SYSREG(14, 2, 3, 4, 0), true, true }, +#endif + { HV_SYS_REG_CNTVOFF_EL2, HVF_SYSREG(14, 0, 3, 4, 3), true, true }, + /* EL2 */ + { HV_SYS_REG_CPTR_EL2, HVF_SYSREG(1, 1, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_ELR_EL2, HVF_SYSREG(4, 0, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_ESR_EL2, HVF_SYSREG(5, 2, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_FAR_EL2, HVF_SYSREG(6, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_HCR_EL2, HVF_SYSREG(1, 1, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_HPFAR_EL2, HVF_SYSREG(6, 0, 3, 4, 4), .el2 =3D true }, + { HV_SYS_REG_MAIR_EL2, HVF_SYSREG(10, 2, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_MDCR_EL2, HVF_SYSREG(1, 1, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_SCTLR_EL2, HVF_SYSREG(1, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_SPSR_EL2, HVF_SYSREG(4, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_SP_EL2, HVF_SYSREG(4, 1, 3, 6, 0), .el2 =3D true}, + { HV_SYS_REG_TCR_EL2, HVF_SYSREG(2, 0, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_TPIDR_EL2, HVF_SYSREG(13, 0, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_TTBR0_EL2, HVF_SYSREG(2, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_TTBR1_EL2, HVF_SYSREG(2, 0, 3, 4, 1), .el2 =3D true }, + { HV_SYS_REG_VBAR_EL2, HVF_SYSREG(12, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_VMPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 5), .el2 =3D true }, + { HV_SYS_REG_VPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 0), .el2 =3D true }, + { HV_SYS_REG_VTCR_EL2, HVF_SYSREG(2, 1, 3, 4, 2), .el2 =3D true }, + { HV_SYS_REG_VTTBR_EL2, HVF_SYSREG(2, 1, 3, 4, 0), .el2 =3D true }, }; =20 int hvf_get_registers(CPUState *cpu) @@ -595,6 +632,14 @@ int hvf_get_registers(CPUState *cpu) continue; } =20 + if (hvf_sreg_match[i].vgic && !hvf_irqchip_in_kernel()) { + continue; + } + + if (hvf_sreg_match[i].el2 && !hvf_arm_el2_enabled()) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { @@ -732,6 +777,14 @@ int hvf_put_registers(CPUState *cpu) continue; } =20 + if (hvf_sreg_match[i].vgic && !hvf_irqchip_in_kernel()) { + continue; + } + + if (hvf_sreg_match[i].el2 && !hvf_arm_el2_enabled()) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 07:42:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Cameron Esfahani , Ani Sinha , Paolo Bonzini , Roman Bolshakov , Shannon Zhao , Phil Dennis-Jordan , Igor Mammedov , qemu-arm@nongnu.org, Mohamed Mediouni Subject: [PATCH v4 15/15] hw/intc: hvf: add migration blocker when using multiple vCPUs with the Apple GIC Date: Mon, 28 Jul 2025 07:57:01 +0200 Message-Id: <20250728055701.38975-16-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250728055701.38975-1-mohamed@unpredictable.fr> References: <20250728055701.38975-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA0MyBTYWx0ZWRfXza1e44twkMYv 0FkTlbOr46B6dC+zyRCroqHHkJA3kCPmFa6lowguCYpS+MD8dYQSA+jCVJwwPkHYgdCXLP7HTj9 rl4xBRYOoOWA42PHdCrI05t4qQ4n7WkQrLZyOD26RZTV2D38QLfxAu/fPo42AC8Bizm+v2atiaE N/lLLk2UbDQ9m5KSqjl6klbj8Etpmu2M0c0XxkUFUoKlMiyF+3FOWG5LRR0cI14UzGb2Sk6CSIZ dwwe2hSkoLmWu1FmeZB17HKUF7YQVtJ4inOlQQ4kJISn5qcqGb9AP5Ih28z0/B+oGNIz7/Tdo= X-Proofpoint-GUID: hPGQXMacA3npR4211D55ZO7dYyxNLADF X-Proofpoint-ORIG-GUID: hPGQXMacA3npR4211D55ZO7dYyxNLADF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 suspectscore=0 phishscore=0 clxscore=1030 malwarescore=0 spamscore=0 adultscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507280043 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.63; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -37 X-Spam_score: -3.8 X-Spam_bar: --- X-Spam_report: (-3.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753682409845116600 Content-Type: text/plain; charset="utf-8" Current state known to be broken, still figuring things out... Signed-off-by: Mohamed Mediouni --- hw/intc/arm_gicv3_hvf.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/intc/arm_gicv3_hvf.c b/hw/intc/arm_gicv3_hvf.c index 30362540f2..151020edd6 100644 --- a/hw/intc/arm_gicv3_hvf.c +++ b/hw/intc/arm_gicv3_hvf.c @@ -18,6 +18,7 @@ #include "hvf_arm.h" #include "gicv3_internal.h" #include "vgic_common.h" +#include "migration/blocker.h" #include "qom/object.h" #include "target/arm/cpregs.h" #include @@ -703,6 +704,17 @@ static void hvf_gicv3_realize(DeviceState *dev, Error = **errp) error_setg(errp, "vGIC maintenance IRQ mismatch with the hardcoded= one in HVF."); return; } + + /* Temporary: current state known to be incomplete. */ + if (s->num_cpu > 1) { + Error *hvf_mcpu_migration_blocker =3D NULL; + error_setg(&hvf_mcpu_migration_blocker, + "Live migration disabled because multiple CPUs are exposed."); + if (migrate_add_blocker(&hvf_mcpu_migration_blocker, errp)) { + error_free(hvf_mcpu_migration_blocker); + return; + } + } } =20 static void hvf_gicv3_class_init(ObjectClass *klass, const void *data) --=20 2.39.5 (Apple Git-154)