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Most changes are straightforward, adjusting printf formats, changing local variable types. More complex is migration, where to maintain backward compatibility a new pstate64 record is introduced, and only when one of the extensions that sets bits 32-35 are active. The fate of gdbstub is left undecided for the moment. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 8 +++--- target/arm/tcg/translate.h | 20 ++++++------- target/arm/cpu.c | 6 ++-- target/arm/gdbstub64.c | 1 + target/arm/helper.c | 11 ++++---- target/arm/machine.c | 56 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper-a64.c | 2 +- 7 files changed, 81 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98360b70b8..7769c4ae3c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -268,7 +268,7 @@ typedef struct CPUArchState { uint64_t xregs[32]; uint64_t pc; /* PSTATE isn't an architectural register for ARMv8. However, it is - * convenient for us to assemble the underlying state into a 32 bit fo= rmat + * convenient for us to assemble the underlying state into a 64 bit fo= rmat * identical to the architectural format used for the SPSR. (This is a= lso * what the Linux kernel's 'pstate' field in signal handlers and KVM's * 'pstate' register are.) Of the PSTATE bits: @@ -280,7 +280,7 @@ typedef struct CPUArchState { * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate */ - uint32_t pstate; + uint64_t pstate; bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nR= W */ bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ =20 @@ -1556,7 +1556,7 @@ static inline unsigned int aarch64_pstate_mode(unsign= ed int el, bool handler) * interprocessing, so we don't attempt to sync with the cpsr state used by * the 32 bit decoder. */ -static inline uint32_t pstate_read(CPUARMState *env) +static inline uint64_t pstate_read(CPUARMState *env) { int ZF; =20 @@ -1566,7 +1566,7 @@ static inline uint32_t pstate_read(CPUARMState *env) | env->pstate | env->daif | (env->btype << 10); } =20 -static inline void pstate_write(CPUARMState *env, uint32_t val) +static inline void pstate_write(CPUARMState *env, uint64_t val) { env->ZF =3D (~val) & PSTATE_Z; env->NF =3D val; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3e63dad2b6..1479f5bf74 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -378,27 +378,27 @@ static inline TCGv_i32 get_ahp_flag(void) } =20 /* Set bits within PSTATE. */ -static inline void set_pstate_bits(uint32_t bits) +static inline void set_pstate_bits(uint64_t bits) { - TCGv_i32 p =3D tcg_temp_new_i32(); + TCGv_i64 p =3D tcg_temp_new_i64(); =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); - tcg_gen_ori_i32(p, p, bits); - tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i64(p, p, bits); + tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* Clear bits within PSTATE. */ -static inline void clear_pstate_bits(uint32_t bits) +static inline void clear_pstate_bits(uint64_t bits) { - TCGv_i32 p =3D tcg_temp_new_i32(); + TCGv_i64 p =3D tcg_temp_new_i64(); =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); - tcg_gen_andi_i32(p, p, ~bits); - tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i64(p, p, ~bits); + tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* If the singlestep state is Active-not-pending, advance to Active-pendin= g. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d9318c5325..ec63297165 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1208,7 +1208,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - uint32_t psr =3D pstate_read(env); + uint64_t psr =3D pstate_read(env); int i, j; int el =3D arm_current_el(env); uint64_t hcr =3D arm_hcr_el2_eff(env); @@ -1230,7 +1230,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) } else { ns_status =3D ""; } - qemu_fprintf(f, "PSTATE=3D%08x %c%c%c%c %sEL%d%c", + qemu_fprintf(f, "PSTATE=3D%016" PRIx64 " %c%c%c%c %sEL%d%c", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', @@ -1247,7 +1247,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); } if (cpu_isar_feature(aa64_bti, cpu)) { - qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); + qemu_fprintf(f, " BTYPE=3D%d", (int)(psr & PSTATE_BTYPE) >> 10); } qemu_fprintf(f, "%s%s%s", (hcr & HCR_NV) ? " NV" : "", diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 64ee9b3b56..3cef47281a 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -47,6 +47,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) case 32: return gdb_get_reg64(mem_buf, env->pc); case 33: + /* pstate is now a 64-bit value; can we simply adjust the xml? */ return gdb_get_reg32(mem_buf, pstate_read(env)); } /* Unknown register. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index f006ecabf3..e404ba0f71 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9185,8 +9185,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) CPUARMState *env =3D &cpu->env; unsigned int new_el =3D env->exception.target_el; vaddr addr =3D env->cp15.vbar_el[new_el]; - unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); - unsigned int old_mode; + uint64_t new_mode =3D aarch64_pstate_mode(new_el, true); + uint64_t old_mode; unsigned int cur_el =3D arm_current_el(env); int rt; =20 @@ -9334,7 +9334,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) * If NV2 is disabled, change SPSR when NV,NV1 =3D=3D 1,0 = (I_ZJRNN) * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM) */ - old_mode =3D deposit32(old_mode, 2, 2, 2); + old_mode =3D deposit64(old_mode, 2, 2, 2); } } } else { @@ -9347,7 +9347,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; =20 - qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%x\n", old_mode); + qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%" PRIx64 "\n", old_mode); qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); =20 @@ -9401,7 +9401,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) =20 env->pc =3D addr; =20 - qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", + qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 + " PSTATE 0x%" PRIx64 "\n", new_el, env->pc, pstate_read(env)); } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 8dbeca2867..9b00c14b4a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -836,6 +836,61 @@ static const VMStateInfo vmstate_cpsr =3D { .put =3D put_cpsr, }; =20 +static int get_pstate64_1(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + uint64_t val =3D qemu_get_be64(f); + + env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); + pstate_write(env, val); + return 0; +} + +static int put_pstate64_1(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + uint64_t val =3D pstate_read(env); + + qemu_put_be64(f, val); + return 0; +} + +static const VMStateInfo vmstate_pstate64_1 =3D { + .name =3D "pstate64", + .get =3D get_pstate64_1, + .put =3D put_pstate64_1, +}; + +static bool pstate64_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return is_a64(env) && pstate_read(env) > UINT32_MAX; +} + +static const VMStateDescription vmstate_pstate64 =3D { + .name =3D "cpu/pstate64", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pstate64_needed, + .fields =3D (const VMStateField[]) { + { + .name =3D "pstate64", + .version_id =3D 0, + .size =3D sizeof(uint64_t), + .info =3D &vmstate_pstate64_1, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, + VMSTATE_END_OF_LIST() + }, +}; + static int get_power(QEMUFile *f, void *opaque, size_t size, const VMStateField *field) { @@ -1119,6 +1174,7 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_serror, &vmstate_irq_line_state, &vmstate_wfxt_timer, + &vmstate_pstate64, NULL } }; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 71c6c44ee8..f61adf1f80 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -639,7 +639,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); unsigned int spsr_idx =3D aarch64_banked_spsr_index(cur_el); - uint32_t spsr =3D env->banked_spsr[spsr_idx]; + uint64_t spsr =3D env->banked_spsr[spsr_idx]; int new_el; bool return_to_aa64 =3D (spsr & PSTATE_nRW) =3D=3D 0; =20 --=20 2.43.0