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[98.150.199.49]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fbe333efesm30016415ad.65.2025.07.27.01.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jul 2025 01:03:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753603410; x=1754208210; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TMPqhlIvVePcBqPr/zfm9nD1xzcakWTsu9w+PFYmzes=; b=gm4/dkNneI8Kprt38MaFBzB0bzpa0i5B366pQqhav+FMI7T1eT1R0hxyhpXe9xQGdW sEx/wYM8YKnMdu/JAEE3B39JhSwkHKY4BuTli9Ujca2W++EQmq41vaTR8yv/4DE/U01U Xr4TMEYPGLwmueNoTYS2FjeT2iiAbbsKV+HLtwktNAZ5vP3j6eTeOKVx8axQXbBvYzcM 4ATUff53WDyTM+Hx1JNP3Y89Wjh++G4HVTaJuYOtzuJsSTpRV6Hz134Smsmfdk+XrOsJ G0+ZRLDoMXPKCSSyopeyWlM/nPPQ0c4pDbm4Pk3zcSDHbv9+WNeYzDr8Aox3P58duzil a+KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753603410; x=1754208210; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TMPqhlIvVePcBqPr/zfm9nD1xzcakWTsu9w+PFYmzes=; b=HTbPKIuVpvbpdiUzc3gFhRzgKf4bh/JqJZslCx0gY8bX+LyEQAe9plZcodSZu/9Duv AR1w5Bqxcj4JFZqMx+GCVbb/1/qg2VL40Ur81ByFCogOMSsu8JG01V7C1R8HI2GXcTga My5xlOuhlC/CAWYcIOqUnS6maMz1mRrCcv5qlj+0B75GF5i4SI2wypEl8z7QisgodGR6 JZ+SQcG57LTknQ/QIucBji5F4EuOXS+7bZjIwNBazVtytFdh4ibK8cblxMNORC2UJyUI Afb1EulkiEVFz0rradRRolXFfgdNw6r9+Ie/voLBZyhxlbLmQd3x9VzWxsJcP+1oUvkN vpGA== X-Gm-Message-State: AOJu0Yxp+OP66JO/K1XDR0UEUgBLWTWUHir+T1jN677lRor2eb7zX9o0 tVfrPJlkCKidd8/ZlzvIHmDo7YgNxv7p+MPRGSB04vtx/W7GKgXP1CryUgSGHnIMruVQhfUruVp mGHHw X-Gm-Gg: ASbGncvC0lpgvJqIHJlexnRP0yUuJjISB8GtdPcp49FRMVxIZ38UqxdINgcSw0KKmFD 4Bcn0/RCLC6h2vJK8IUA6JXm9Me8pAqupUv6CJtpl9q2sHI0KKSVWGT1LuWPE16FgDIox2v5gR5 3FU4pZH5le6tuxicUgDuo2XvuZhQXdoM8US/K4mvOdebIRnIQ6SuDyyC83NOsqWGn3bdwf8BLRw O5XRwRQHY2sQfybPqoXdLLY8czM42AQZHVcbDwITuQ2dYMG3v6DGWZLXRAgCqjkQqW/l6AQ7/eV 2y0wetfgvlSPtaT+cV/DgWad4teO9r/ESAPEMMfgTvGq0LlTg7Kjit3d4TlS/u5GFpgH4aUyBYA y1BXNyvqerZRXd6ChBhR8MMaOld0LDbqzPrnPh4oYpNgGsIKvakblPTzfHVmO57J/qjsegNdPVs coTudYMTBEtw== X-Google-Smtp-Source: AGHT+IEj3kNZcHnsQJUHZjOnzE4zvkn1AY6MPkHP+bxMldIPOTC9x6UwjNYtBvSg/cfDcMNZndzfow== X-Received: by 2002:a17:902:ce0c:b0:234:a779:47cd with SMTP id d9443c01a7336-23fb2fffa92mr116055315ad.15.1753603410479; Sun, 27 Jul 2025 01:03:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 28/82] include/hw/core/cpu: Widen MMUIdxMap Date: Sat, 26 Jul 2025 22:02:00 -1000 Message-ID: <20250727080254.83840-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250727080254.83840-1-richard.henderson@linaro.org> References: <20250727080254.83840-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753603937702116600 Content-Type: text/plain; charset="utf-8" Widen MMUIdxMap to 32 bits. Do not yet expand NB_MMU_MODES, but widen the map type in preparation. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/hw/core/cpu.h | 2 +- accel/tcg/cputlb.c | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 85b1ab4022..a95559c538 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -201,7 +201,7 @@ struct CPUClass { * Fix the number of mmu modes to 16. */ #define NB_MMU_MODES 16 -typedef uint16_t MMUIdxMap; +typedef uint32_t MMUIdxMap; =20 /* Use a fully associative victim tlb of 8 entries. */ #define CPU_VTLB_SIZE 8 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2a6aa01c57..416aaa1040 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -89,9 +89,6 @@ */ QEMU_BUILD_BUG_ON(sizeof(vaddr) > sizeof(run_on_cpu_data)); =20 -/* We currently can't handle more than 16 bits in the MMUIDX bitmask. - */ -QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) =20 static inline size_t tlb_n_entries(CPUTLBDescFast *fast) --=20 2.43.0