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[98.150.199.49]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fbe327443sm29824635ad.44.2025.07.27.00.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jul 2025 00:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753601853; x=1754206653; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YoDX6hlPhJpbPYJEoHdtEuOKXRrXAq3oOs7MkhVvpa0=; b=Gae6/77axf6tNMsVZqrB2uC6X9OK0V7s8G03K3muaTgNMgvKBVpZ8ARoP4W7pwL020 yzZDWtyEdgw8DqjxgD7KGR1oqYzE4Xww6XjE9mRAftlF95j6IvUhtP3HeWQnfkc4JhgL aTCqa1aK6KQ+7xRz2wSwiXeYuLYLBL/Cw3LiPyCdDtExxeH7zvZFih7Nw+LfSddSZfBQ 1vSuSQL3MXzQ+tzsFhplIc0WDoshxvqaVmZppZBLTOUFPSU/NTSlt6k2Uq1HdCZqw0xJ gUEH7ycNVfHuFeRrsFWsfYTVVuyo5sIv8OTUmm4B6l51GHPPLp4zaVcIilFf4lEMVqNq OG1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753601853; x=1754206653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YoDX6hlPhJpbPYJEoHdtEuOKXRrXAq3oOs7MkhVvpa0=; b=LXHiD6x0gfF9u7bwV1J/aGPB9hiT1Rqm/c69rtPoP9eVBEhS3OFGe+o5tcqLFjfMVa GnLDIHP0hjSzeQxBCL23KAnaokA7PDH6u6F8B32jKBi/D0IPm6oTmp/IDRSbhaUHA1H4 o2VEfyHx/Xxap+hCft6do1dCcq5succP2KwBAOU4PjOkfBDFGMdZdP3C0mNNDlNGW/1t eMbIpcs5tEw52YEq1ynhswBvDx6bbhlmr2iupz+d3bUTdzAaAu42pdDzkSqtFW6GcJAB QvkJtzFI3tTWYMfsN8cKUMcbf3mR1Ls86l4b9S90BnMmMTzdtPa5D7DmyuDC1FIc2fql Sq2A== X-Gm-Message-State: AOJu0YzOzGGYY6SXabTexFEi9oXdhhm8aBMXX0PLWDPT7rlebNY8KLYe H18YmmXDXj1jXsxq9rG7b5SjVWxQh9IqlyxDH6ClqyefMgDEfvpS/ZfwuXdK6GvPjy8CazMqXPK 4cRfz X-Gm-Gg: ASbGncuQBHKDOMS5sJZtFZSyb3jLDET7gEV6IZ01JnsPbFEw09whSpyy5VKVQQoHzYy a3pWOVKi2+mvzscGMInOL+dJVEg10GoTCzPEByajCG9eFrjP4crgRW282JUyPGZhqOzxe/hCELe SkGxTYL6o9ip3Q4Aou5etArhEVKZvrg7ZWfGg34ZadjRUjzDUC5l/c8D/wHlsX9UhFKbmTUnrLu LpFBYDMmAWEAhITVKqhlyfpHS4xqHgDZ6dJVyQfv9e/drP6iBMF7Czp65RpEQmp71zx0S5cKuZ+ 0KLH7Efams19fOGCgUPuMb7ve61wAnSasrkMljoVck9+jTWe77La0Lq1bzqx+9KNCfm4HVL21+z Fem5BCfmJxMfWynih83gseqOKPITBEujhS4TPJfCs9ghQ4t1sGpqU6LbP/iuuPU/q5MUj5dVNwj ozj2Kk6UbMjQ== X-Google-Smtp-Source: AGHT+IGhQ+pFBTnFj5Z14tGkXVeVv25JYpbQh5wIQukFgRFVOAmfEencbQbpKcm66S3yWz2VIuVpqQ== X-Received: by 2002:a17:902:c94f:b0:23f:f6e0:b3c7 with SMTP id d9443c01a7336-23ff6e0b6a4mr39168825ad.45.1753601852675; Sun, 27 Jul 2025 00:37:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-stable@nongnu.org, Pierrick Bouvier Subject: [PULL 1/3] linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals Date: Sat, 26 Jul 2025 21:37:26 -1000 Message-ID: <20250727073728.82913-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250727073728.82913-1-richard.henderson@linaro.org> References: <20250727073728.82913-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753601933874116600 Content-Type: text/plain; charset="utf-8" From: Peter Maydell A recent change to the kernel (Linux commit b376108e1f88 "arm64/fpsimd: signal: Clear TPIDR2 when delivering signals") updated the signal-handler entry code to always clear TPIDR2_EL0. This is necessary for the userspace ZA lazy saving scheme to work correctly when unwinding exceptions across a signal boundary. (For the essay-length description of the incorrect behaviour and why this is the correct fix, see the commit message for the kernel commit.) Make QEMU also clear TPIDR2_EL0 on signal entry, applying the equivalent bugfix to our implementation. Note that getting this unwinding to work correctly also requires changes to the userspace code, e.g. as implemented in gcc in https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3Db5ffc8e75a8 This change is technically an ABI change; from the kernel's point of view SME was never enabled (it was hidden behind CONFIG_BROKEN) before the change. From QEMU's point of view our SME-related signal handling was broken anyway as we weren't saving and restoring TPIDR2_EL0. Cc: qemu-stable@nongnu.org Fixes: 78011586b90d1 ("target/arm: Enable SME for user-only") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250725175510.3864231-2-peter.maydell@linaro.org> --- linux-user/aarch64/signal.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index d50cab78d8..6514b73ad9 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -666,8 +666,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, env->btype =3D 2; } =20 - /* Invoke the signal handler with both SM and ZA disabled. */ + /* + * Invoke the signal handler with a clean SME state: both SM and ZA + * disabled and TPIDR2_EL0 cleared. + */ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + env->cp15.tpidr2_el0 =3D 0; =20 if (info) { frame->info =3D *info; --=20 2.43.0 From nobody Sat Nov 15 07:40:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753601937; cv=none; d=zohomail.com; s=zohoarc; b=WdJUUDQ96LUl9m2oq7xHQJIr5AKpB3FwQEyHAa+Vs8H/yTp8yMnYyFmUTw6x3dTWB+xiRi2cFUXfQy99dvH6sLYsqhIeKc6EXv8CuwChE89lg+QPKZ7jOtBXc+OYYJrRux2L90vhDwiG9/dCHQZXGMizhaj26Lxv3VkELxdXlUw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753601937; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1DLT5kPT2st9uLIffRQa9ZE7Wu7o06Vv+AiBdjjBCGA=; b=O0szzCzVpmDIviOEQrRC026UI4FWX8lT0EQiUhlfvv8XYRrAfkZeSeNTOArmtoHhIlXRPimWerIzmFRpbyMCYxtb5bch4pZ94ResS+T+9/Qjm7gXgCKFM+urXkG8CTB4ujQu3XbBArcGfdplbxdPVr6PL7iQfs4tYZ5pF8cF0Oc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753601937320156.81686034307438; Sun, 27 Jul 2025 00:38:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufvx2-0001s3-F3; Sun, 27 Jul 2025 03:37:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufvwz-0001bb-UW for qemu-devel@nongnu.org; Sun, 27 Jul 2025 03:37:41 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ufvwu-0000Qt-1H for qemu-devel@nongnu.org; Sun, 27 Jul 2025 03:37:41 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-879d2e419b9so2399752a12.2 for ; Sun, 27 Jul 2025 00:37:35 -0700 (PDT) Received: from localhost.localdomain (syn-098-150-199-049.res.spectrum.com. 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The result is that code which tries to unwind an exception out of a signal handler will not work correctly. Add support for the missing record. Cc: qemu-stable@nongnu.org Fixes: 78011586b90d1 ("target/arm: Enable SME for user-only") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250725175510.3864231-3-peter.maydell@linaro.org> --- linux-user/aarch64/signal.c | 42 +++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 6514b73ad9..f28ba80754 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -121,6 +121,13 @@ struct target_za_context { #define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) =20 +#define TARGET_TPIDR2_MAGIC 0x54504902 + +struct target_tpidr2_context { + struct target_aarch64_ctx head; + uint64_t tpidr2; +}; + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -253,6 +260,14 @@ static void target_setup_za_record(struct target_za_co= ntext *za, } } =20 +static void target_setup_tpidr2_record(struct target_tpidr2_context *tpidr= 2, + CPUARMState *env) +{ + __put_user(TARGET_TPIDR2_MAGIC, &tpidr2->head.magic); + __put_user(sizeof(struct target_tpidr2_context), &tpidr2->head.size); + __put_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -403,6 +418,12 @@ static bool target_restore_za_record(CPUARMState *env, return true; } =20 +static void target_restore_tpidr2_record(CPUARMState *env, + struct target_tpidr2_context *tpi= dr2) +{ + __get_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -410,6 +431,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_fpsimd_context *fpsimd =3D NULL; struct target_sve_context *sve =3D NULL; struct target_za_context *za =3D NULL; + struct target_tpidr2_context *tpidr2 =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; @@ -460,6 +482,14 @@ static int target_restore_sigframe(CPUARMState *env, za_size =3D size; break; =20 + case TARGET_TPIDR2_MAGIC: + if (tpidr2 || size !=3D sizeof(struct target_tpidr2_context) || + !cpu_isar_feature(aa64_sme, env_archcpu(env))) { + goto err; + } + tpidr2 =3D (struct target_tpidr2_context *)ctx; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -497,6 +527,9 @@ static int target_restore_sigframe(CPUARMState *env, if (za && !target_restore_za_record(env, za, za_size, &svcr)) { goto err; } + if (tpidr2) { + target_restore_tpidr2_record(env, tpidr2); + } if (env->svcr !=3D svcr) { env->svcr =3D svcr; arm_rebuild_hflags(env); @@ -568,8 +601,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, .total_size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0; - int sve_size =3D 0, za_size =3D 0; + int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -585,6 +618,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, sve_ofs =3D alloc_sigframe_space(sve_size, &layout); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + tpidr2_size =3D sizeof(struct target_tpidr2_context); + tpidr2_ofs =3D alloc_sigframe_space(tpidr2_size, &layout); /* ZA state needs saving only if it is enabled. */ if (FIELD_EX64(env->svcr, SVCR, ZA)) { za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env)); @@ -644,6 +679,9 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, if (za_ofs) { target_setup_za_record((void *)frame + za_ofs, env, za_size); } + if (tpidr2_ofs) { + target_setup_tpidr2_record((void *)frame + tpidr2_ofs, env); + } =20 /* Set up the stack frame for unwinding. */ fr =3D (void *)frame + fr_ofs; --=20 2.43.0 From nobody Sat Nov 15 07:40:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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This is done with a new ZT_MAGIC record. We forgot to implement support for this in our linux-user code before enabling the SME2p1 emulation, which meant that a signal handler using SME would corrupt the ZT0 register value, and code that attempted to unwind an exception from inside a signal handler would not work. Add the missing record handling. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250725175510.3864231-4-peter.maydell@linaro.org> --- linux-user/aarch64/signal.c | 93 ++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f28ba80754..668353bbda 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -128,6 +128,23 @@ struct target_tpidr2_context { uint64_t tpidr2; }; =20 +#define TARGET_ZT_MAGIC 0x5a544e01 + +struct target_zt_context { + struct target_aarch64_ctx head; + uint16_t nregs; + uint16_t reserved[3]; + /* ZTn register data immediately follows */ +}; + +#define TARGET_ZT_SIG_REG_BYTES (512 / 8) +#define TARGET_ZT_SIG_REGS_SIZE(n) (TARGET_ZT_SIG_REG_BYTES * (n)) +#define TARGET_ZT_SIG_CONTEXT_SIZE(n) (sizeof(struct target_zt_context) + \ + TARGET_ZT_SIG_REGS_SIZE(n)) +#define TARGET_ZT_SIG_REGS_OFFSET sizeof(struct target_zt_context) +QEMU_BUILD_BUG_ON(TARGET_ZT_SIG_REG_BYTES !=3D \ + sizeof_field(CPUARMState, za_state.zt0)); + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -268,6 +285,28 @@ static void target_setup_tpidr2_record(struct target_t= pidr2_context *tpidr2, __put_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); } =20 +static void target_setup_zt_record(struct target_zt_context *zt, + CPUARMState *env, int size) +{ + uint64_t *z; + + memset(zt, 0, sizeof(*zt)); + __put_user(TARGET_ZT_MAGIC, &zt->head.magic); + __put_user(size, &zt->head.size); + /* + * The record format allows for multiple ZT regs, but + * currently there is only one, ZT0. + */ + __put_user(1, &zt->nregs); + assert(size =3D=3D TARGET_ZT_SIG_CONTEXT_SIZE(1)); + + /* ZT0 is the same byte-stream format as SVE regs and ZA */ + z =3D (void *)zt + TARGET_ZT_SIG_REGS_OFFSET; + for (int i =3D 0; i < ARRAY_SIZE(env->za_state.zt0); i++) { + __put_user_e(env->za_state.zt0[i], z + i, le); + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -424,6 +463,30 @@ static void target_restore_tpidr2_record(CPUARMState *= env, __get_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); } =20 +static bool target_restore_zt_record(CPUARMState *env, + struct target_zt_context *zt, int siz= e, + int svcr) +{ + uint16_t nregs; + uint64_t *z; + + if (!(FIELD_EX64(svcr, SVCR, ZA))) { + return false; + } + + __get_user(nregs, &zt->nregs); + + if (nregs !=3D 1) { + return false; + } + + z =3D (void *)zt + TARGET_ZT_SIG_REGS_OFFSET; + for (int i =3D 0; i < ARRAY_SIZE(env->za_state.zt0); i++) { + __get_user_e(env->za_state.zt0[i], z + i, le); + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -432,10 +495,12 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; struct target_za_context *za =3D NULL; struct target_tpidr2_context *tpidr2 =3D NULL; + struct target_zt_context *zt =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; int za_size =3D 0; + int zt_size =3D 0; int svcr =3D 0; =20 target_restore_general_frame(env, sf); @@ -490,6 +555,15 @@ static int target_restore_sigframe(CPUARMState *env, tpidr2 =3D (struct target_tpidr2_context *)ctx; break; =20 + case TARGET_ZT_MAGIC: + if (zt || size !=3D TARGET_ZT_SIG_CONTEXT_SIZE(1) || + !cpu_isar_feature(aa64_sme2, env_archcpu(env))) { + goto err; + } + zt =3D (struct target_zt_context *)ctx; + zt_size =3D size; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -530,6 +604,13 @@ static int target_restore_sigframe(CPUARMState *env, if (tpidr2) { target_restore_tpidr2_record(env, tpidr2); } + /* + * NB that we must restore ZT after ZA so the check that there's + * no ZT record if SVCR.ZA is 0 gets the right value of SVCR. + */ + if (zt && !target_restore_zt_record(env, zt, zt_size, svcr)) { + goto err; + } if (env->svcr !=3D svcr) { env->svcr =3D svcr; arm_rebuild_hflags(env); @@ -602,7 +683,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, uc.tuc_mcontext.__reserved), }; int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; - int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0; + int zt_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0, zt_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -628,6 +710,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, } za_ofs =3D alloc_sigframe_space(za_size, &layout); } + if (cpu_isar_feature(aa64_sme2, env_archcpu(env)) && + FIELD_EX64(env->svcr, SVCR, ZA)) { + /* If SME ZA storage is enabled, we must also save SME2 ZT0 */ + zt_size =3D TARGET_ZT_SIG_CONTEXT_SIZE(1); + zt_ofs =3D alloc_sigframe_space(zt_size, &layout); + } =20 if (layout.extra_ofs) { /* Reserve space for the extra end marker. The standard end marker @@ -682,6 +770,9 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, if (tpidr2_ofs) { target_setup_tpidr2_record((void *)frame + tpidr2_ofs, env); } + if (zt_ofs) { + target_setup_zt_record((void *)frame + zt_ofs, env, zt_size); + } =20 /* Set up the stack frame for unwinding. */ fr =3D (void *)frame + fr_ofs; --=20 2.43.0