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Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/{intc =3D> arm}/arm_gicv3_cpuif_common.c | 2 +- hw/arm/meson.build | 1 + hw/intc/meson.build | 1 - 3 files changed, 2 insertions(+), 2 deletions(-) rename hw/{intc =3D> arm}/arm_gicv3_cpuif_common.c (92%) diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/arm/arm_gicv3_cpuif_comm= on.c similarity index 92% rename from hw/intc/arm_gicv3_cpuif_common.c rename to hw/arm/arm_gicv3_cpuif_common.c index ff1239f65db..8435ef8cf0d 100644 --- a/hw/intc/arm_gicv3_cpuif_common.c +++ b/hw/arm/arm_gicv3_cpuif_common.c @@ -10,7 +10,7 @@ */ =20 #include "qemu/osdep.h" -#include "gicv3_internal.h" +#include "hw/intc/gicv3_internal.h" #include "cpu.h" =20 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index dc68391305f..9f2eea474b4 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -82,6 +82,7 @@ arm_common_ss.add(when: 'CONFIG_VERSATILE', if_true: file= s('versatilepb.c')) arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) =20 arm_common_ss.add(files('boot.c')) +arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_= common.c')) =20 hw_arch +=3D {'arm': arm_ss} hw_common_arch +=3D {'arm': arm_common_ss} diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3137521a4ad..4578c70dc45 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -38,7 +38,6 @@ if config_all_devices.has_key('CONFIG_APIC') or \ endif =20 specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common= .c')) -specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_co= mmon.c')) specific_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.= c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) --=20 2.47.2 From nobody Thu Oct 16 01:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753475130; cv=none; d=zohomail.com; s=zohoarc; b=Tc3HgD2X7hF2IY0fRDaZ5j5eCfNjXW2/BPHxZ+b5cFPM3v7/Gamd9cvDzQo97C4u3bcgu/eujv9XbBO5Kht0sWdvEGyIEIFaCSTmf4DToXDEnfQe+WRz+dqg3+fNziEkO8o0BAMfmNUnR2ObN4mZndaqCL3Taei7/gys0XNIP2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753475130; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TAokCfQUIO9o7V4gC6O0FLK0Lo5OjtX4UkdOojm8EZ0=; b=mL/BNp16YqUrtQIkRWKFjAs1yj7K134o/t7z8IeRfAqm7aa8E9DEgen+5O8gclVx7vfM/ICeQBozR9mPPbIUzd1yUUX0UsE+/FPGNlemcIO5uoojJmeXFSMv9A5TWyGGlphHG1W1GIPsd32iuaDPXpTIzTi5xia/9T9urOM1C+M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753475130360645.9034740320103; Fri, 25 Jul 2025 13:25:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufOyU-0004W3-KS; Fri, 25 Jul 2025 16:25:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufOsx-0006jY-18 for qemu-devel@nongnu.org; Fri, 25 Jul 2025 16:19:19 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ufOst-0000vt-Tl for qemu-devel@nongnu.org; Fri, 25 Jul 2025 16:19:18 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-315cd33fa79so1729152a91.3 for ; Fri, 25 Jul 2025 13:19:15 -0700 (PDT) Received: from pc.. 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Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/{intc =3D> arm}/arm_gicv3_cpuif.c | 2 +- hw/arm/meson.build | 1 + hw/arm/trace-events | 62 ++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 - hw/intc/trace-events | 62 ------------------------------ 5 files changed, 64 insertions(+), 64 deletions(-) rename hw/{intc =3D> arm}/arm_gicv3_cpuif.c (99%) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/arm/arm_gicv3_cpuif.c similarity index 99% rename from hw/intc/arm_gicv3_cpuif.c rename to hw/arm/arm_gicv3_cpuif.c index 4b4cf091570..a3564f2c53d 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/arm/arm_gicv3_cpuif.c @@ -17,7 +17,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "trace.h" -#include "gicv3_internal.h" +#include "hw/intc/gicv3_internal.h" #include "hw/irq.h" #include "cpu.h" #include "target/arm/cpregs.h" diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 9f2eea474b4..25b6bb438a2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -83,6 +83,7 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files= ('vexpress.c')) =20 arm_common_ss.add(files('boot.c')) arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_= common.c')) +arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpui= f.c')) =20 hw_arch +=3D {'arm': arm_ss} hw_common_arch +=3D {'arm': arm_common_ss} diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f3386bd7ae1..250ad116186 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -1,5 +1,67 @@ # See docs/devel/tracing.rst for syntax documentation. =20 +# arm_gicv3_cpuif.c +gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu 0x%= x value 0x%" PRIx64 +gicv3_icc_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR write cpu 0= x%x value 0x%" PRIx64 +gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d r= ead cpu 0x%x value 0x%" PRIx64 +gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d = write cpu 0x%x value 0x%" PRIx64 +gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 I= CC_AP%dR%d read cpu 0x%x value 0x%" PRIx64 +gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 = ICC_AP%dR%d write cpu 0x%x value 0x%" PRIx64 +gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRP= EN%d read cpu 0x%x value 0x%" PRIx64 +gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGR= PEN%d write cpu 0x%x value 0x%" PRIx64 +gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_= EL3 read cpu 0x%x value 0x%" PRIx64 +gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1= _EL3 write cpu 0x%x value 0x%" PRIx64 +gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR read cpu 0= x%x value 0x%" PRIx64 +gicv3_icc_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR write cpu= 0x%x value 0x%" PRIx64 +gicv3_icc_ctlr_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 re= ad cpu 0x%x value 0x%" PRIx64 +gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 w= rite cpu 0x%x value 0x%" PRIx64 +gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio) "GICv3 CPU = i/f 0x%x HPPI update: irq %d group %d prio %d" +gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CP= U i/f 0x%x HPPI update: setting FIQ %d IRQ %d" +gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uin= t32_t targetlist) "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affin= ity 0x%xxx targetlist 0x%x" +gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu 0= x%x value 0x%" PRIx64 +gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu 0= x%x value 0x%" PRIx64 +gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_NMIAR1 read c= pu 0x%x value 0x%" PRIx64 +gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR%= d write cpu 0x%x value 0x%" PRIx64 +gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read c= pu 0x%x value 0x%" PRIx64 +gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read c= pu 0x%x value 0x%" PRIx64 +gicv3_icc_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICC_DIR write cpu 0= x%x value 0x%" PRIx64 +gicv3_icc_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_RPR read cpu 0x%= x value 0x%" PRIx64 +gicv3_ich_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 I= CH_AP%dR%d read cpu 0x%x value 0x%" PRIx64 +gicv3_ich_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 = ICH_AP%dR%d write cpu 0x%x value 0x%" PRIx64 +gicv3_ich_hcr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_HCR_EL2 read cpu= 0x%x value 0x%" PRIx64 +gicv3_ich_hcr_write(uint32_t cpu, uint64_t val) "GICv3 ICH_HCR_EL2 write c= pu 0x%x value 0x%" PRIx64 +gicv3_ich_vmcr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_VMCR_EL2 read c= pu 0x%x value 0x%" PRIx64 +gicv3_ich_vmcr_write(uint32_t cpu, uint64_t val) "GICv3 ICH_VMCR_EL2 write= cpu 0x%x value 0x%" PRIx64 +gicv3_ich_lr_read(int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_LR%d_E= L2 read cpu 0x%x value 0x%" PRIx64 +gicv3_ich_lr32_read(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LR%d= read cpu 0x%x value 0x%" PRIx32 +gicv3_ich_lrc_read(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LRC%d= read cpu 0x%x value 0x%" PRIx32 +gicv3_ich_lr_write(int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_LR%d_= EL2 write cpu 0x%x value 0x%" PRIx64 +gicv3_ich_lr32_write(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LR%= d write cpu 0x%x value 0x%" PRIx32 +gicv3_ich_lrc_write(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LRC%= d write cpu 0x%x value 0x%" PRIx32 +gicv3_ich_vtr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_VTR read cpu 0x%= x value 0x%" PRIx64 +gicv3_ich_misr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_MISR read cpu 0= x%x value 0x%" PRIx64 +gicv3_ich_eisr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_EISR read cpu 0= x%x value 0x%" PRIx64 +gicv3_ich_elrsr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_ELRSR read cpu= 0x%x value 0x%" PRIx64 +gicv3_icv_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 I= CV_AP%dR%d read cpu 0x%x value 0x%" PRIx64 +gicv3_icv_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 = ICV_AP%dR%d write cpu 0x%x value 0x%" PRIx64 +gicv3_icv_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d r= ead cpu 0x%x value 0x%" PRIx64 +gicv3_icv_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d = write cpu 0x%x value 0x%" PRIx64 +gicv3_icv_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR read cpu 0x%= x value 0x%" PRIx64 +gicv3_icv_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR write cpu 0= x%x value 0x%" PRIx64 +gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRP= EN%d read cpu 0x%x value 0x%" PRIx64 +gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGR= PEN%d write cpu 0x%x value 0x%" PRIx64 +gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR read cpu 0= x%x value 0x%" PRIx64 +gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR write cpu= 0x%x value 0x%" PRIx64 +gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu 0x%= x value 0x%" PRIx64 +gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR= %d read cpu 0x%x value 0x%" PRIx64 +gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0= x%x value 0x%" PRIx64 +gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d r= ead cpu 0x%x value 0x%" PRIx64 +gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICV_NMIAR1 read c= pu 0x%x value 0x%" PRIx64 +gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%= d write cpu 0x%x value 0x%" PRIx64 +gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int= prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d p= rio %d" +gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GIC= v3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" +gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) "GICv3 CPU = i/f 0x%x virt HPPI update: setting maintenance-irq %d" + # omap1.c omap1_pwl_clocking_scheme(const char *scheme) "omap1 CLKM: clocking scheme= set to %s" omap1_pwl_backlight(int output) "omap1 PWL: backlight now at %d/256" diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 4578c70dc45..22814893cbe 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -38,7 +38,6 @@ if config_all_devices.has_key('CONFIG_APIC') or \ endif =20 specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common= .c')) -specific_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.= c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 018c609ca5e..4d6c886b794 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -110,68 +110,6 @@ gic_dist_write(int addr, unsigned int size, uint32_t v= al) "dist write at 0x%08x gic_lr_entry(int cpu, int entry, uint32_t val) "cpu %d: new lr entry %d: 0= x%08" PRIx32 gic_update_maintenance_irq(int cpu, int val) "cpu %d: maintenance =3D %d" =20 -# arm_gicv3_cpuif.c -gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu 0x%= x value 0x%" PRIx64 -gicv3_icc_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR write cpu 0= x%x value 0x%" PRIx64 -gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d r= ead cpu 0x%x value 0x%" PRIx64 -gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d = write cpu 0x%x value 0x%" PRIx64 -gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 I= CC_AP%dR%d read cpu 0x%x value 0x%" PRIx64 -gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 = ICC_AP%dR%d write cpu 0x%x value 0x%" PRIx64 -gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRP= EN%d read cpu 0x%x value 0x%" PRIx64 -gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGR= PEN%d write cpu 0x%x value 0x%" PRIx64 -gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_= EL3 read cpu 0x%x value 0x%" PRIx64 -gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1= _EL3 write cpu 0x%x value 0x%" PRIx64 -gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR read cpu 0= x%x value 0x%" PRIx64 -gicv3_icc_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR write cpu= 0x%x value 0x%" PRIx64 -gicv3_icc_ctlr_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 re= ad cpu 0x%x value 0x%" PRIx64 -gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_CTLR_EL3 w= rite cpu 0x%x value 0x%" PRIx64 -gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio) "GICv3 CPU = i/f 0x%x HPPI update: irq %d group %d prio %d" -gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CP= U i/f 0x%x HPPI update: setting FIQ %d IRQ %d" -gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uin= t32_t targetlist) "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affin= ity 0x%xxx targetlist 0x%x" -gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu 0= x%x value 0x%" PRIx64 -gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu 0= x%x value 0x%" PRIx64 -gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_NMIAR1 read c= pu 0x%x value 0x%" PRIx64 -gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR%= d write cpu 0x%x value 0x%" PRIx64 -gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read c= pu 0x%x value 0x%" PRIx64 -gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read c= pu 0x%x value 0x%" PRIx64 -gicv3_icc_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICC_DIR write cpu 0= x%x value 0x%" PRIx64 -gicv3_icc_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_RPR read cpu 0x%= x value 0x%" PRIx64 -gicv3_ich_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 I= CH_AP%dR%d read cpu 0x%x value 0x%" PRIx64 -gicv3_ich_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 = ICH_AP%dR%d write cpu 0x%x value 0x%" PRIx64 -gicv3_ich_hcr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_HCR_EL2 read cpu= 0x%x value 0x%" PRIx64 -gicv3_ich_hcr_write(uint32_t cpu, uint64_t val) "GICv3 ICH_HCR_EL2 write c= pu 0x%x value 0x%" PRIx64 -gicv3_ich_vmcr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_VMCR_EL2 read c= pu 0x%x value 0x%" PRIx64 -gicv3_ich_vmcr_write(uint32_t cpu, uint64_t val) "GICv3 ICH_VMCR_EL2 write= cpu 0x%x value 0x%" PRIx64 -gicv3_ich_lr_read(int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_LR%d_E= L2 read cpu 0x%x value 0x%" PRIx64 -gicv3_ich_lr32_read(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LR%d= read cpu 0x%x value 0x%" PRIx32 -gicv3_ich_lrc_read(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LRC%d= read cpu 0x%x value 0x%" PRIx32 -gicv3_ich_lr_write(int regno, uint32_t cpu, uint64_t val) "GICv3 ICH_LR%d_= EL2 write cpu 0x%x value 0x%" PRIx64 -gicv3_ich_lr32_write(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LR%= d write cpu 0x%x value 0x%" PRIx32 -gicv3_ich_lrc_write(int regno, uint32_t cpu, uint32_t val) "GICv3 ICH_LRC%= d write cpu 0x%x value 0x%" PRIx32 -gicv3_ich_vtr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_VTR read cpu 0x%= x value 0x%" PRIx64 -gicv3_ich_misr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_MISR read cpu 0= x%x value 0x%" PRIx64 -gicv3_ich_eisr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_EISR read cpu 0= x%x value 0x%" PRIx64 -gicv3_ich_elrsr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_ELRSR read cpu= 0x%x value 0x%" PRIx64 -gicv3_icv_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 I= CV_AP%dR%d read cpu 0x%x value 0x%" PRIx64 -gicv3_icv_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 = ICV_AP%dR%d write cpu 0x%x value 0x%" PRIx64 -gicv3_icv_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d r= ead cpu 0x%x value 0x%" PRIx64 -gicv3_icv_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d = write cpu 0x%x value 0x%" PRIx64 -gicv3_icv_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR read cpu 0x%= x value 0x%" PRIx64 -gicv3_icv_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR write cpu 0= x%x value 0x%" PRIx64 -gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRP= EN%d read cpu 0x%x value 0x%" PRIx64 -gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGR= PEN%d write cpu 0x%x value 0x%" PRIx64 -gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR read cpu 0= x%x value 0x%" PRIx64 -gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR write cpu= 0x%x value 0x%" PRIx64 -gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu 0x%= x value 0x%" PRIx64 -gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR= %d read cpu 0x%x value 0x%" PRIx64 -gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0= x%x value 0x%" PRIx64 -gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d r= ead cpu 0x%x value 0x%" PRIx64 -gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICV_NMIAR1 read c= pu 0x%x value 0x%" PRIx64 -gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%= d write cpu 0x%x value 0x%" PRIx64 -gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int= prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d p= rio %d" -gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GIC= v3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" -gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) "GICv3 CPU = i/f 0x%x virt HPPI update: setting maintenance-irq %d" - # arm_gicv3_dist.c gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure= ) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u = secure %d" gicv3_dist_badread(uint64_t offset, unsigned size, bool secure) "GICv3 dis= tributor read: offset 0x%" PRIx64 " size %u secure %d: error" --=20 2.47.2 From nobody Thu Oct 16 01:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753475194; cv=none; d=zohomail.com; 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Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/{intc =3D> arm}/armv7m_nvic.c | 0 hw/arm/meson.build | 1 + hw/arm/trace-events | 17 +++++++++++++++++ hw/intc/meson.build | 1 - hw/intc/trace-events | 17 ----------------- 5 files changed, 18 insertions(+), 18 deletions(-) rename hw/{intc =3D> arm}/armv7m_nvic.c (100%) diff --git a/hw/intc/armv7m_nvic.c b/hw/arm/armv7m_nvic.c similarity index 100% rename from hw/intc/armv7m_nvic.c rename to hw/arm/armv7m_nvic.c diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 25b6bb438a2..68dbdd3e913 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -84,6 +84,7 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files= ('vexpress.c')) arm_common_ss.add(files('boot.c')) arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_= common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpui= f.c')) +arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) =20 hw_arch +=3D {'arm': arm_ss} hw_common_arch +=3D {'arm': arm_common_ss} diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 250ad116186..e25fa32668c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -62,6 +62,23 @@ gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hpp= vlpi, int grp, int prio) gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GIC= v3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) "GICv3 CPU = i/f 0x%x virt HPPI update: setting maintenance-irq %d" =20 +# armv7m_nvic.c +nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" +nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" +nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-= bank %d priority %d" +nvic_irq_update(int vectpending, int pendprio, int exception_prio, int lev= el) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq lin= e to %d" +nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq= %d to HardFault: insufficient priority %d >=3D %d" +nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disa= bled" +nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, = int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d= derived %d (enabled: %d priority %d)" +nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pen= ding irq %d secure-bank %d (enabled: %d priority %d)" +nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now acti= ve (prio %d)" +nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets= _secure: %d" +nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)" +nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to = %d" +nvic_set_nmi_level(int level) "NVIC external NMI level set to %d" +nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysre= g read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysr= eg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + # omap1.c omap1_pwl_clocking_scheme(const char *scheme) "omap1 CLKM: clocking scheme= set to %s" omap1_pwl_backlight(int output) "omap1 PWL: backlight now at %d/256" diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 22814893cbe..dc857833dcb 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -40,7 +40,6 @@ endif specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common= .c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) -specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_= liointc.c')) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 4d6c886b794..aa9d65fdc25 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -165,23 +165,6 @@ gicv3_its_vte_read(uint32_t vpeid, int valid, uint32_t= vptsize, uint64_t vptaddr gicv3_its_vte_read_fault(uint32_t vpeid) "GICv3 ITS: vPE Table read for vP= EID 0x%x: faulted" gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t = vptaddr, uint32_t rdbase) "GICv3 ITS: vPE Table write for vPEID 0x%x: valid= %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" =20 -# armv7m_nvic.c -nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" -nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" -nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-= bank %d priority %d" -nvic_irq_update(int vectpending, int pendprio, int exception_prio, int lev= el) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq lin= e to %d" -nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq= %d to HardFault: insufficient priority %d >=3D %d" -nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disa= bled" -nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, = int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d= derived %d (enabled: %d priority %d)" -nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pen= ding irq %d secure-bank %d (enabled: %d priority %d)" -nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now acti= ve (prio %d)" -nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets= _secure: %d" -nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)" -nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to = %d" -nvic_set_nmi_level(int level) "NVIC external NMI level set to %d" -nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysre= g read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" -nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysr= eg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" - # heathrow_pic.c heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64"= %u: 0x%"PRIx64 heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" = %u: 0x%"PRIx64 --=20 2.47.2