From nobody Sat Nov 15 07:42:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753466159; cv=none; d=zohomail.com; s=zohoarc; b=mk0IMAf3FhLltjnuqPI8aqK4q7siUPUWQZ366duaU4ZnHWW+MyoYiwC3Y8MO8SejhX+/LUEj+c6w28R1D46I1hZ45X5bdIYtdY0KNGVbYSWk/Tb/DnMW8q1nrAz3ty5DyMnHAMjNtocFXQ564H4FwwOKuYmUa51YgsemzBuJ3zA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753466159; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GNWd437IneI7rQZbiaYAiFHnUytRK1qpbnn38Zb1wZA=; b=j7dH+MQt7pH7R25QgSNRsXrYKkVLi+AVSp1KjggrhbGbKt4Xs8fpvD5DJILbjyD5OmE8Wq/y6CKnHWL+6qnhc0U+67T9MW58P9iV13cX1nx+swR6hkZwJlkezcNCCmLdlaDiIX6DyiNqSG23ShRDGqbN81dYRCtggKT4Lw7IO5s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175346615963876.856735033179; Fri, 25 Jul 2025 10:55:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufMdj-000807-Kv; Fri, 25 Jul 2025 13:55:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufMdb-0007kg-FN for qemu-devel@nongnu.org; Fri, 25 Jul 2025 13:55:19 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ufMdX-0001kx-Dx for qemu-devel@nongnu.org; Fri, 25 Jul 2025 13:55:17 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3a6e2d85705so1238837f8f.0 for ; Fri, 25 Jul 2025 10:55:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b778f16819sm499036f8f.67.2025.07.25.10.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 10:55:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753466114; x=1754070914; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GNWd437IneI7rQZbiaYAiFHnUytRK1qpbnn38Zb1wZA=; b=FndEFV9f/a01nyspN9eYGHVaNs0VH2mGgE1OElA1qJyGHLJknGQVAf8A8hnTzjgNDy wredVDgJTO4ekTfa9IBl01gq62BUsYcKymmD/WfY6oUf7JoYyVVsJkjCNrvr3Ub+x/Fp IlXGBVezS01+P3GQvIwXytIfNtb9huLi3aFbuXEZRx8o02C+IArPWY+Tfw1vHdSpyA3t GS8H13IR3KWJqvt+n/uzhiTH4pHPOu/yR7FdYIjOtrDx9YXVk46ck7MLPFz+5HnARYVq likdq47SPyv6FovvI14Lpvi0Q2Z/hUSP2XxYg7HJdmseknP3RZKpXjN4ZpTQOd8L1bjm mepA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753466114; x=1754070914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GNWd437IneI7rQZbiaYAiFHnUytRK1qpbnn38Zb1wZA=; b=knkmhj3He+bSOgY6jmNp7g85hETTEcuOK8uJPwenqpDBs3QIocBCO9i2Ftv4vRcLOI /0nxaWEdmp0b9v9n8j6oBU1AwX1i2iBaxHZOEy/eZzpXhccAkByl25CI69pFo7jMEjXw aZWUxi0BqLj5sEs0xfQKRaOlyh0Us8P5c7McZ2+QUfpotZtccipFPktRRPpltR1TFKUp dOqTu28tEekLPZG7XBKq5ynZ0uHB8/S1vMmSXcypqb23QS5nnPQes3KhOz7w3R9V+wWY /X6oafA8Qlvd/oBwrQ5zWSLxMBuB1cxr3GBUQ7bXe9NvbQ1tDqa4+w3gde+zFAGvm+TP rlOQ== X-Forwarded-Encrypted: i=1; AJvYcCWh3IfUR7faq1k3qSF0CGSy1x2n8MBME1N4wJLETAJCxxNLu5qGOr2Mnx1eb4lu5FehoftD9IvYcG4L@nongnu.org X-Gm-Message-State: AOJu0YzLeXEqysovGyho6fasgnDhB2VRq2FamYsG9DJx4OTxa7zK68xU UgLLNJm8LxxLz8Z+ZXMs9euLKwaui7e37UyqcsABDt6X2A6D3EFOegec/LfJppnZEdo= X-Gm-Gg: ASbGnct2STHmk82u/Z+ngJSTwhhVcESjlhz3S9Rw0RHQwBMH1wKW4qKnXY0jBvzYpr5 /6YEw1+J1pbKmSL2GdCBKA80cTCuOLY2sZXaWM1lPm+7RIVvcVc4+6myp0HKmvKPyTGf3YgSPAI 02HXqaaBt3GhXJpltrJWbXtjq25nvKMl6EIKz7AEqLJNqeJ5yEzxZJBhiBuXtjYGTkzr4SXd6yO UOIbZ0ldOAbsEpn/G2Kvm2RKBSZhEYEQ3/K86Aoutt+cRRAKr9duVdDAK20xWkZ/0PFzwifQC3i mIfiyZgvcQO+KIDLU3QVaWTOXOl15QV21YDty7Z9pCxX1pNbsur+YyFYI5FUpJhuU0a2uI30LLN 5lxF9BnOZTGmAOz0hkOE8Fkq6TzfS X-Google-Smtp-Source: AGHT+IF+U1f6wmbiKlV0Fz9wOf+lF3q8IEne9h8zxkeXmFO4McUPkhkeZR3lu5O0rf32JiAwCHUhIA== X-Received: by 2002:a05:6000:2484:b0:3a4:cbc6:9db0 with SMTP id ffacd0b85a97d-3b77677defbmr2740567f8f.51.1753466113781; Fri, 25 Jul 2025 10:55:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 for-10.1 1/3] linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals Date: Fri, 25 Jul 2025 18:55:08 +0100 Message-ID: <20250725175510.3864231-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250725175510.3864231-1-peter.maydell@linaro.org> References: <20250725175510.3864231-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753466161570116600 Content-Type: text/plain; charset="utf-8" A recent change to the kernel (Linux commit b376108e1f88 "arm64/fpsimd: signal: Clear TPIDR2 when delivering signals") updated the signal-handler entry code to always clear TPIDR2_EL0. This is necessary for the userspace ZA lazy saving scheme to work correctly when unwinding exceptions across a signal boundary. (For the essay-length description of the incorrect behaviour and why this is the correct fix, see the commit message for the kernel commit.) Make QEMU also clear TPIDR2_EL0 on signal entry, applying the equivalent bugfix to our implementation. Note that getting this unwinding to work correctly also requires changes to the userspace code, e.g. as implemented in gcc in https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3Db5ffc8e75a8 This change is technically an ABI change; from the kernel's point of view SME was never enabled (it was hidden behind CONFIG_BROKEN) before the change. From QEMU's point of view our SME-related signal handling was broken anyway as we weren't saving and restoring TPIDR2_EL0. Cc: qemu-stable@nongnu.org Fixes: 78011586b90d1 ("target/arm: Enable SME for user-only") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- linux-user/aarch64/signal.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index d50cab78d83..6514b73ad98 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -666,8 +666,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, env->btype =3D 2; } =20 - /* Invoke the signal handler with both SM and ZA disabled. */ + /* + * Invoke the signal handler with a clean SME state: both SM and ZA + * disabled and TPIDR2_EL0 cleared. + */ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + env->cp15.tpidr2_el0 =3D 0; =20 if (info) { frame->info =3D *info; --=20 2.43.0 From nobody Sat Nov 15 07:42:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1753466193; cv=none; d=zohomail.com; s=zohoarc; b=UAM4pNZcqmFuwJ0jAFyC8GA4XSbMixT3/Vpgpc3o7kRG+la7f5HpKL1RDLGazXVcGG3gaIqWopj7IoUONAQQpa+SfErajj62zjlgUdPE+bxnVPSHMbWH5aNG4BgwYqBvW58qbc5g2bOCUrWrZBrG59Qwb5f63aWmLBLN2gAJCz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753466193; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cx/FbVm1MdKSCrBP/0m/5JMlptiQo4e2+krFmi0/nrw=; b=Q7lzDvUSCoCFAGLJ3NjLD7cC8/WVJiv6TDROBeHDD50CVuIEuAVaO4EYkHEsGgRoDZurDu/tWXp4ntK+Rg7RgrdQlM03cVPRscHmEetHEQ76+jHo5DJBE/eG/vAVQEK7X43RtIXwBL36lKS+VFL6OYDd1DUvw5/XC9DWJHikmPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753466193722894.7593484453861; Fri, 25 Jul 2025 10:56:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufMdh-0007zI-Dn; Fri, 25 Jul 2025 13:55:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufMdb-0007l0-Ga for qemu-devel@nongnu.org; Fri, 25 Jul 2025 13:55:19 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ufMdY-0001lF-F9 for qemu-devel@nongnu.org; Fri, 25 Jul 2025 13:55:18 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3a4f72cba73so2140204f8f.1 for ; Fri, 25 Jul 2025 10:55:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b778f16819sm499036f8f.67.2025.07.25.10.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 10:55:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1753466115; x=1754070915; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cx/FbVm1MdKSCrBP/0m/5JMlptiQo4e2+krFmi0/nrw=; b=AbLkFLQKuRr4KntIwtOb/w/ltIe+kj4H76aMEXbr6ZZWHe6Mh6lnat/Ks2Ty3xOuRq fgWaKltTMMLHDsnuOfHIY4vDpkOGnSbSkeagUYLduFiTRQgxYKzbDWvMkTDYEoF/S08j gBiWtDz2zuT6vN2CfNI/Tp0XqEEElNGM/w7sCHporwKOKEJSaurQIKbxOG3lM9r6ACHU M8pCAxdopdYCCD8wdUgU/NLLBb63iQWQm/nyM8Yw4zlWAsuiO2rRqW+yH3xWRR7e9/xN xUxszHR+2eQHWEQ+jVm2I7vvW5gqU9nflKcSUke2GIOdOyqt0szhD3d70PWcoMqpAN6P QFAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753466115; x=1754070915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cx/FbVm1MdKSCrBP/0m/5JMlptiQo4e2+krFmi0/nrw=; b=aNBp476LxV8qqjxU4Flx2kl5cpuuVGpsz+lWGVvvWYe0m9C7/NZsNF+X5RqrJ1jrNN JxOtiyg/rEBkPActBCqOPj5SXCVmlAyLgkt4BVf375mq0YpK7HCxJO8+Q1BIVbgh5NOc McGLqYKJ4H9D5Py6+lUx4T0ONO5p6tmudYUgctMc6lqMFQAYmp65Nbs8JYVZ7QCC+hbk P0QBCj1cim44f7+r2k5Yvpro2vjh6tB+iP/zQ55+77KoN/F0aneuMQClaKUgIOjcmo33 HP6Z+TldWIff2GIrrX8i/Y9Bxsqmaj3q6kDwGgwzqkKvnQ0WkhJL9K4COlbCwLiUoDxe dD6g== X-Forwarded-Encrypted: i=1; AJvYcCVI4HD83CAS/Y25UkaHA4IlpUtNJWu/Icq9TT2xQSzsTFeO4aEIVYHz4TkTS5Ud8oPPSV9OXPfToCLC@nongnu.org X-Gm-Message-State: AOJu0YwK6Rfx3tRQvQWja/G65QxU0eMMAx72WlqPZBprpKzB4mADQpg3 4KsvvcfX/Kdd2FJV978gxOKU6NEMOHbjDsaKzxX58KLulXekxVnnTNUvRYcQ5CTmLcg= X-Gm-Gg: ASbGncuoqDFH5ZTeS+FFJ3PZBsaoTDbf6ZAWcd7j+V8Z1J+qXcmV+0pBuPtN0SBQUdW UAzZEtQTuFjdh9YEzcCeKZgkrrAwOdsohGPIuVxrTH5fBNsG57ASe+OluY8TmSDzV+bAKf1QDqK VdR/cQjaPA44IOF4QbTjsKtdo3sj1/0GUhpyHPpPyVvxiNbkQANQgIF1kWEZko/PYi3VQMBfE// dJY56CCaTtow3iSjqRMxklKJha4ap8tY4GsIoqruPYYdjtK9xMttCw4F9y9d/4Vj2ha00KM0kyh DFIjiHxgtX7rSpg9uPl1Yb0HQ/QOXCUqzDyzCp3sxQcnbA0gC6cfu+ntWp2Mvhwxko/FGycZV6Y 8JOUTs6ofkGjRF6FHmALGvA7jiqtVCBG2yHhBmVw= X-Google-Smtp-Source: AGHT+IEiK5CMo80OC7n6T0I4IvROf2tZ6KsnL7fllzzYaEqX9+HqypsPftb3El2Xt8A5TFkOx5HsdQ== X-Received: by 2002:a05:6000:401e:b0:3a5:6860:f47f with SMTP id ffacd0b85a97d-3b7765e6070mr2960761f8f.6.1753466114792; Fri, 25 Jul 2025 10:55:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 for-10.1 2/3] linux-user/aarch64: Support TPIDR2_MAGIC signal frame record Date: Fri, 25 Jul 2025 18:55:09 +0100 Message-ID: <20250725175510.3864231-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250725175510.3864231-1-peter.maydell@linaro.org> References: <20250725175510.3864231-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1753466196354116600 Content-Type: text/plain; charset="utf-8" FEAT_SME adds the TPIDR2 userspace-accessible system register, which is used as part of the procedure calling standard's lazy saving scheme for the ZA registers: https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#66the= -za-lazy-saving-scheme The Linux kernel has a signal frame record for saving and restoring this value when calling signal handlers, but we forgot to implement this. The result is that code which tries to unwind an exception out of a signal handler will not work correctly. Add support for the missing record. Cc: qemu-stable@nongnu.org Fixes: 78011586b90d1 ("target/arm: Enable SME for user-only") Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- linux-user/aarch64/signal.c | 42 +++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 6514b73ad98..f28ba807549 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -121,6 +121,13 @@ struct target_za_context { #define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) =20 +#define TARGET_TPIDR2_MAGIC 0x54504902 + +struct target_tpidr2_context { + struct target_aarch64_ctx head; + uint64_t tpidr2; +}; + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -253,6 +260,14 @@ static void target_setup_za_record(struct target_za_co= ntext *za, } } =20 +static void target_setup_tpidr2_record(struct target_tpidr2_context *tpidr= 2, + CPUARMState *env) +{ + __put_user(TARGET_TPIDR2_MAGIC, &tpidr2->head.magic); + __put_user(sizeof(struct target_tpidr2_context), &tpidr2->head.size); + __put_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -403,6 +418,12 @@ static bool target_restore_za_record(CPUARMState *env, return true; } =20 +static void target_restore_tpidr2_record(CPUARMState *env, + struct target_tpidr2_context *tpi= dr2) +{ + __get_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -410,6 +431,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_fpsimd_context *fpsimd =3D NULL; struct target_sve_context *sve =3D NULL; struct target_za_context *za =3D NULL; + struct target_tpidr2_context *tpidr2 =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; @@ -460,6 +482,14 @@ static int target_restore_sigframe(CPUARMState *env, za_size =3D size; break; =20 + case TARGET_TPIDR2_MAGIC: + if (tpidr2 || size !=3D sizeof(struct target_tpidr2_context) || + !cpu_isar_feature(aa64_sme, env_archcpu(env))) { + goto err; + } + tpidr2 =3D (struct target_tpidr2_context *)ctx; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -497,6 +527,9 @@ static int target_restore_sigframe(CPUARMState *env, if (za && !target_restore_za_record(env, za, za_size, &svcr)) { goto err; } + if (tpidr2) { + target_restore_tpidr2_record(env, tpidr2); + } if (env->svcr !=3D svcr) { env->svcr =3D svcr; arm_rebuild_hflags(env); @@ -568,8 +601,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, .total_size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0; - int sve_size =3D 0, za_size =3D 0; + int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -585,6 +618,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, sve_ofs =3D alloc_sigframe_space(sve_size, &layout); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + tpidr2_size =3D sizeof(struct target_tpidr2_context); + tpidr2_ofs =3D alloc_sigframe_space(tpidr2_size, &layout); /* ZA state needs saving only if it is enabled. */ if (FIELD_EX64(env->svcr, SVCR, ZA)) { za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env)); @@ -644,6 +679,9 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, if (za_ofs) { target_setup_za_record((void *)frame + za_ofs, env, za_size); } + if (tpidr2_ofs) { + target_setup_tpidr2_record((void *)frame + tpidr2_ofs, env); + } =20 /* Set up the stack frame for unwinding. */ fr =3D (void *)frame + fr_ofs; --=20 2.43.0 From nobody Sat Nov 15 07:42:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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This is done with a new ZT_MAGIC record. We forgot to implement support for this in our linux-user code before enabling the SME2p1 emulation, which meant that a signal handler using SME would corrupt the ZT0 register value, and code that attempted to unwind an exception from inside a signal handler would not work. Add the missing record handling. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- linux-user/aarch64/signal.c | 93 ++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f28ba807549..668353bbda4 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -128,6 +128,23 @@ struct target_tpidr2_context { uint64_t tpidr2; }; =20 +#define TARGET_ZT_MAGIC 0x5a544e01 + +struct target_zt_context { + struct target_aarch64_ctx head; + uint16_t nregs; + uint16_t reserved[3]; + /* ZTn register data immediately follows */ +}; + +#define TARGET_ZT_SIG_REG_BYTES (512 / 8) +#define TARGET_ZT_SIG_REGS_SIZE(n) (TARGET_ZT_SIG_REG_BYTES * (n)) +#define TARGET_ZT_SIG_CONTEXT_SIZE(n) (sizeof(struct target_zt_context) + \ + TARGET_ZT_SIG_REGS_SIZE(n)) +#define TARGET_ZT_SIG_REGS_OFFSET sizeof(struct target_zt_context) +QEMU_BUILD_BUG_ON(TARGET_ZT_SIG_REG_BYTES !=3D \ + sizeof_field(CPUARMState, za_state.zt0)); + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -268,6 +285,28 @@ static void target_setup_tpidr2_record(struct target_t= pidr2_context *tpidr2, __put_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); } =20 +static void target_setup_zt_record(struct target_zt_context *zt, + CPUARMState *env, int size) +{ + uint64_t *z; + + memset(zt, 0, sizeof(*zt)); + __put_user(TARGET_ZT_MAGIC, &zt->head.magic); + __put_user(size, &zt->head.size); + /* + * The record format allows for multiple ZT regs, but + * currently there is only one, ZT0. + */ + __put_user(1, &zt->nregs); + assert(size =3D=3D TARGET_ZT_SIG_CONTEXT_SIZE(1)); + + /* ZT0 is the same byte-stream format as SVE regs and ZA */ + z =3D (void *)zt + TARGET_ZT_SIG_REGS_OFFSET; + for (int i =3D 0; i < ARRAY_SIZE(env->za_state.zt0); i++) { + __put_user_e(env->za_state.zt0[i], z + i, le); + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -424,6 +463,30 @@ static void target_restore_tpidr2_record(CPUARMState *= env, __get_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2); } =20 +static bool target_restore_zt_record(CPUARMState *env, + struct target_zt_context *zt, int siz= e, + int svcr) +{ + uint16_t nregs; + uint64_t *z; + + if (!(FIELD_EX64(svcr, SVCR, ZA))) { + return false; + } + + __get_user(nregs, &zt->nregs); + + if (nregs !=3D 1) { + return false; + } + + z =3D (void *)zt + TARGET_ZT_SIG_REGS_OFFSET; + for (int i =3D 0; i < ARRAY_SIZE(env->za_state.zt0); i++) { + __get_user_e(env->za_state.zt0[i], z + i, le); + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -432,10 +495,12 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; struct target_za_context *za =3D NULL; struct target_tpidr2_context *tpidr2 =3D NULL; + struct target_zt_context *zt =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; int za_size =3D 0; + int zt_size =3D 0; int svcr =3D 0; =20 target_restore_general_frame(env, sf); @@ -490,6 +555,15 @@ static int target_restore_sigframe(CPUARMState *env, tpidr2 =3D (struct target_tpidr2_context *)ctx; break; =20 + case TARGET_ZT_MAGIC: + if (zt || size !=3D TARGET_ZT_SIG_CONTEXT_SIZE(1) || + !cpu_isar_feature(aa64_sme2, env_archcpu(env))) { + goto err; + } + zt =3D (struct target_zt_context *)ctx; + zt_size =3D size; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -530,6 +604,13 @@ static int target_restore_sigframe(CPUARMState *env, if (tpidr2) { target_restore_tpidr2_record(env, tpidr2); } + /* + * NB that we must restore ZT after ZA so the check that there's + * no ZT record if SVCR.ZA is 0 gets the right value of SVCR. + */ + if (zt && !target_restore_zt_record(env, zt, zt_size, svcr)) { + goto err; + } if (env->svcr !=3D svcr) { env->svcr =3D svcr; arm_rebuild_hflags(env); @@ -602,7 +683,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, uc.tuc_mcontext.__reserved), }; int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; - int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0; + int zt_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0, zt_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -628,6 +710,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, } za_ofs =3D alloc_sigframe_space(za_size, &layout); } + if (cpu_isar_feature(aa64_sme2, env_archcpu(env)) && + FIELD_EX64(env->svcr, SVCR, ZA)) { + /* If SME ZA storage is enabled, we must also save SME2 ZT0 */ + zt_size =3D TARGET_ZT_SIG_CONTEXT_SIZE(1); + zt_ofs =3D alloc_sigframe_space(zt_size, &layout); + } =20 if (layout.extra_ofs) { /* Reserve space for the extra end marker. The standard end marker @@ -682,6 +770,9 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, if (tpidr2_ofs) { target_setup_tpidr2_record((void *)frame + tpidr2_ofs, env); } + if (zt_ofs) { + target_setup_zt_record((void *)frame + zt_ofs, env, zt_size); + } =20 /* Set up the stack frame for unwinding. */ fr =3D (void *)frame + fr_ofs; --=20 2.43.0