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Fri, 25 Jul 2025 10:01:47 -0700 (PDT) Date: Fri, 25 Jul 2025 10:01:36 -0700 Mime-Version: 1.0 X-Mailer: git-send-email 2.50.1.470.g6ba607880d-goog Message-ID: <20250725170136.145116-1-alexrichardson@google.com> Subject: [PATCH v3] target/arm: add support for 64-bit PMCCNTR in AArch32 mode From: Alex Richardson To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alex Richardson Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::44a; envelope-from=3e7iDaA4KCkYitm5zqkpizl0wvowwotm.kwuymu2-lm3mtvwvov2.wzo@flex--alexrichardson.bounces.google.com; helo=mail-pf1-x44a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1753463035458116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the PMUv3, a new AArch32 64-bit (MCRR/MRRC) accessor for the PMCCNTR was added. In QEMU we forgot to implement this, so only provide the 32-bit accessor. Since we have a 64-bit PMCCNTR sysreg for AArch64, adding the 64-bit AArch32 version is easy. We add the PMCCNTR to the v8_cp_reginfo because PMUv3 was added in the ARMv8 architecture. This is consistent with how we handle the existing PMCCNTR support, where we always implement it for all v7 CPUs. This is arguably something we should clean up so it is gated on ARM_FEATURE_PMU and/or an ID register check for the relevant PMU version, but we should do that as its own tidyup rather than being inconsistent between this PMCCNTR accessor and the others. Since the register name is the same as the 32-bit PMCCNTR, we set ARM_CP_NO_GDB on the 32-bit one to avoid generating an invalid GDB XML. See https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registe= rs/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=3Den Change v2->v3: - Moved ARM_CP_NO_GDB to the 32-bit register if Armv8 is supported Changes v1->v2: - Moved to new file - Updated commit message - Added ARM_CP_NO_GDB Signed-off-by: Alex Richardson --- target/arm/cpregs-pmu.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c index 0f295b1376..144e339c76 100644 --- a/target/arm/cpregs-pmu.c +++ b/target/arm/cpregs-pmu.c @@ -1067,11 +1067,6 @@ static const ARMCPRegInfo v7_pm_reginfo[] =3D { .fgt =3D FGT_PMSELR_EL0, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, - { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, - .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, - .fgt =3D FGT_PMCCNTR_EL0, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, - .accessfn =3D pmreg_access_ccntr }, { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, @@ -1211,6 +1206,19 @@ void define_pm_cpregs(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr64); define_arm_cp_regs(cpu, v7_pm_reginfo); + /* When Armv8 is supported, PMCCNTR aliases the new 64-bit version= */ + ARMCPRegInfo pmccntr =3D { + .name =3D "PMCCNTR", + .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, + .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fgt =3D FGT_PMCCNTR_EL0, + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, + }; + if (arm_feature(env, ARM_FEATURE_V8)) { + pmccntr.type |=3D ARM_CP_NO_GDB; + } + define_one_arm_cp_reg(cpu, &pmccntr); =20 for (unsigned i =3D 0, pmcrn =3D pmu_num_counters(env); i < pmcrn;= i++) { g_autofree char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d= ", i); @@ -1276,6 +1284,12 @@ void define_pm_cpregs(ARMCPU *cpu) .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, .fgt =3D FGT_PMCEIDN_EL0, .resetvalue =3D cpu->pmceid1 }, + { .name =3D "PMCCNTR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .crm =3D 9, .opc1 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .reset= value =3D 0, + .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT, + .fgt =3D FGT_PMCCNTR_EL0, .readfn =3D pmccntr_read, + .writefn =3D pmccntr_write, }, }; define_arm_cp_regs(cpu, v8_pm_reginfo); } --=20 2.50.1.470.g6ba607880d-goog