From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433895; cv=none; d=zohomail.com; s=zohoarc; b=gKTVzsnTM3Br075X7L6wjFuwv5XPMAc3LfagwlD38v6MnMkkLaZU67R88JrfmJ3XhMpUVNQbJiBbaHDD+QZw84hvCfVI/094hj/WHVZLk/DNLfMkTBjBybwpa6Ppam5whL6pA1s7o65Hw1Veo5Wz0EmSBZEMg2L0C6FDcJEdKGE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433895; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VT+vLkQ2OgLpMtVF9hAuKVaGzZdWuCg5ciEij+c5zzI=; b=i9vqJ6tQkterWlBqR1KLHZR0tjsMlgFu64LL4B8g3D9eT9fGn3jpb/Pu2CCKbfAS9a1fYP9HTBiO64RRyldDIbLx/qyvp51PKmArh32mLW213y3lQd7AcOsfno+QjScJW7lrQ3R00MyccK9MK/4N0c3hh/rOAN7Yo6Qid/lxaac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753433895939309.3236288635194; Fri, 25 Jul 2025 01:58:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEDq-0007Y1-6E; Fri, 25 Jul 2025 04:56:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDj-0007Ob-SD for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:04 -0400 Received: from p-west3-cluster2-host6-snip4-1.eps.apple.com ([57.103.74.54] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDg-0001rb-Tj for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:02 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id E315018000AA; Fri, 25 Jul 2025 08:55:54 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 2B5F41800209; Fri, 25 Jul 2025 08:55:50 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=VT+vLkQ2OgLpMtVF9hAuKVaGzZdWuCg5ciEij+c5zzI=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=f2ijtylkjuIVBTZJz8boFStCQDRG3MnmwM94cxDVsfdRdlIQ9QVbhWXryE66Fx4OuT+rbGIONgm9049yYgyC23r6/rBXXPPEw05lauLzGnscoVnlAUeXrO/ueTdxL1B24nBziYSR+nlGJmQhtd8fYHiLfi9oxutGvLgSe5Pcy2/wCuCQ3aBpxxsM4Fv4nvvWz5cPWPse+Mr85QqBD3vcxJ3yKBN3DHMc2nNzJh0JVZU9jkc/mxEiEl4gu+KCGP7umqbGiEaCfXSxIzjROozC9hoDQSo1WTRi4aLaC/AzS0O64KiEvooBnsV0XZ6f10rLutaHVFET0lBz/RhLmzscMQ== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 1/9] target/arm: hvf: stubbing writes to LORC_EL1 Date: Fri, 25 Jul 2025 10:55:37 +0200 Message-Id: <20250725085545.93619-2-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: bi8nbXj5c4zJsPIftg5GQsrkiBqckjcD X-Proofpoint-ORIG-GUID: bi8nbXj5c4zJsPIftg5GQsrkiBqckjcD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfX9yLiFrBknFJZ 1HsusMa2ogBx4zx+I8y5OC86LbQ4OyadXU1cJLXnsfrb8lfx7VnKWHV/lIkOMv3BAHmcdSRCCzd zi1XgWnfNDsKKB7iziaS5W386goq0IuQCJyHOy3oTkbOdsJIHSKyamy5GLOG90Oi+Lokwai17XG 9+o65UsP6NNM+SErswQ6vsmL7UiKImdzTgE3P1twaGGZYpMVfLfQ/BKMNMIzjpAMR+uJhmnGBDs ZZ6dwvej+HO5Gd/gft2ifm88I3kADBLnIyW8/KDlntUQjSJqx6FGLsWYJn4Fs+MRFd/aQ37ho= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 mlxlogscore=797 phishscore=0 spamscore=0 mlxscore=0 malwarescore=0 clxscore=1030 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.54; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433899059116600 Content-Type: text/plain; charset="utf-8" Linux zeroes LORC_EL1 on boot at EL2, without further interaction with FEAT= _LOR afterwards. Stub out LORC_EL1 accesses as FEAT_LOR is a mandatory extension on Armv8.1+. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index c9cfcdc08b..edfd29de75 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -186,6 +186,7 @@ void hvf_arm_init_debug(void) #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) +#define SYSREG_LORC_EL1 SYSREG(3, 0, 10, 4, 3) #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) #define SYSREG_CNTP_CTL_EL0 SYSREG(3, 3, 14, 2, 1) #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) @@ -1650,6 +1651,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; + case SYSREG_LORC_EL1: + /* Dummy register */ + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433909; cv=none; d=zohomail.com; s=zohoarc; b=ChILGPZMyy52bi7vXJPAiKn9ujTozCLtoIuH6xYozrkN8sS6UuBGCJLYIlrm6i8fq6hrlBlgkqDIxUMZq4Ixb04TmrP8kBO/lkbbRBKy+FM76Avr23b95xVoQ3yBgzB/7jpIjbpudO+EjRG9u40Fyk8mYwJ/URa64aijyeCRgzY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433909; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jJOGyIhLIcX1vAvbV7H3PNba35G2QEX+o9kg0SfkkBA=; b=jDFecdGLr5eR0ypXjn3WDzCTLAN6sh18ifU3cGTENEx29UzTexH3rqfOh03TQ+ZD1M4gvzJ61plevOmZo7qjGzwugtygawlsSsNJhF2dLs7WX/1UhbAXRVCq4q0ypwHsNc9ksJ+XF9cJAEkv91qZFjTBkV0yN2ZgT+vOqpGDHjw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175343390911214.259725247234087; Fri, 25 Jul 2025 01:58:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEDr-0007by-Gb; Fri, 25 Jul 2025 04:56:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDh-0007O7-U6 for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:03 -0400 Received: from p-west3-cluster2-host12-snip4-8.eps.apple.com ([57.103.74.101] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDf-0001r8-Uw for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:01 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id 59C9A1800099; Fri, 25 Jul 2025 08:55:57 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 8208518000B9; Fri, 25 Jul 2025 08:55:54 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=jJOGyIhLIcX1vAvbV7H3PNba35G2QEX+o9kg0SfkkBA=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=IHN7IxneU/oUnG516IuPadMAFDWS4LOqGOrOLAev8lknNnTuFqnwGhfXvizrS+QExZllGRz3kIMpE6R/GmVuxaj9wU/J5s+kn32kaKL90zJS06CIx+FEbqKowEdGZUq0h6P06KnpIUjOuUFQKf6LYuw+lN8UaNMSyeUDmb00o0hniDtDZv+2FS2xS5HN0Gkz5eqOEVzUz2D4C3fPApAEFFvCKn1REqoPb/AGVt16cYdajGTYHyvgmLE8IhiO4DyNJqEqSYudfRp91qMJuHhEmdKSWgm3JJRNGhob1xoXHOJXJIMaP0rrcj+0f1/cdcBgzTku6L/zay6sBs2M3Xrs2g== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 2/9] accel, hw/arm, include/system/hvf: plumbing changes for HVF vGIC Date: Fri, 25 Jul 2025 10:55:38 +0200 Message-Id: <20250725085545.93619-3-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfX4tEzheQQIQrJ Kv+Db5fvqDBwekEAY43nup/T7B3upozvKjL3PI80X7VOMQCESXiiw5tOL1wll6QSnQ3roPcneVO +4G/xsAjJeg7Uv7oOeL9TSXl2otl3dFMg0IOdT6OleIb+QPL3763XrT3975vJEOz1h3tFEa86Fb /Tr2k4owNqQJS0bsfJ1z4b46sy0ItMPhrCJfwxPEC8aUiPMd55fdhxXoczVNSpFt8hUzJQLJ7B7 IrZzKWbhBBmY4Ju+ywz2EqCDBWpcPzNoqzOu+H4sdAOCXBKoeNfpNK8TRADV58GtXoJP7UHWE= X-Proofpoint-GUID: 5VYpoCsbgTCW18uBm0bIHD1_cGAvpEgy X-Proofpoint-ORIG-GUID: 5VYpoCsbgTCW18uBm0bIHD1_cGAvpEgy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 mlxscore=0 spamscore=0 phishscore=0 clxscore=1030 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.101; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433910708116600 Content-Type: text/plain; charset="utf-8" Misc changes for HVF vGIC enablement. Signed-off-by: Mohamed Mediouni --- accel/hvf/hvf-all.c | 44 ++++++++++++++++++++++++++++++++++++++ accel/stubs/hvf-stub.c | 1 + hw/arm/virt.c | 17 +++++++++------ hw/intc/arm_gicv3_common.c | 3 +++ include/system/hvf.h | 3 +++ system/vl.c | 2 ++ 6 files changed, 64 insertions(+), 6 deletions(-) diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index e67a8105a6..d9408e259f 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -10,6 +10,8 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-common.h" #include "accel/accel-ops.h" #include "system/address-spaces.h" #include "system/memory.h" @@ -20,6 +22,7 @@ #include "trace.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; =20 struct mac_slot { int present; @@ -290,6 +293,41 @@ static int hvf_gdbstub_sstep_flags(AccelState *as) return SSTEP_ENABLE | SSTEP_NOIRQ; } =20 +static void hvf_set_kernel_irqchip(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ +#ifdef __aarch64__ + OnOffSplit mode; + if (!visit_type_OnOffSplit(v, name, &mode, errp)) { + return; + } + + switch (mode) { + case ON_OFF_SPLIT_ON: + hvf_kernel_irqchip =3D true; + break; + + case ON_OFF_SPLIT_OFF: + hvf_kernel_irqchip =3D false; + break; + + case ON_OFF_SPLIT_SPLIT: + error_setg(errp, "HVF: split irqchip is not supported on Arm."); + break; + + default: + /* + * The value was checked in visit_type_OnOffSplit() above. If + * we get here, then something is wrong in QEMU. + */ + abort(); + } +#else + error_setg(errp, "HVF: setting irqchip configuration not supported on = x86_64."); +#endif +} + static void hvf_accel_class_init(ObjectClass *oc, const void *data) { AccelClass *ac =3D ACCEL_CLASS(oc); @@ -297,6 +335,12 @@ static void hvf_accel_class_init(ObjectClass *oc, cons= t void *data) ac->init_machine =3D hvf_accel_init; ac->allowed =3D &hvf_allowed; ac->gdbstub_supported_sstep_flags =3D hvf_gdbstub_sstep_flags; + hvf_kernel_irqchip =3D true; + object_class_property_add(oc, "kernel-irqchip", "on|off|split", + NULL, hvf_set_kernel_irqchip, + NULL, NULL); + object_class_property_set_description(oc, "kernel-irqchip", + "Configure HVF irqchip"); } =20 static const TypeInfo hvf_accel_type =3D { diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c index 42eadc5ca9..6bd08759ba 100644 --- a/accel/stubs/hvf-stub.c +++ b/accel/stubs/hvf-stub.c @@ -10,3 +10,4 @@ #include "system/hvf.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ef6be3660f..a26bde4c75 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -830,7 +830,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 @@ -853,8 +853,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count); =20 - if (!kvm_irqchip_in_kernel()) { - if (vms->tcg_its) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { + if (vms->its && vms->tcg_its) { object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem), &error_fatal); qdev_prop_set_bit(vms->gic, "has-lpi", true); @@ -864,7 +864,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) ARCH_GIC_MAINT_IRQ); } } else { - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->virt); } @@ -2058,11 +2058,16 @@ static void finalize_gic_version(VirtMachineState *= vms) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; - } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { + } else if (hvf_enabled()) { + if (!hvf_irqchip_in_kernel()) { + gics_supported |=3D VIRT_GIC_VERSION_2_MASK; + } + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; + } else if (tcg_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { gics_supported |=3D VIRT_GIC_VERSION_3_MASK; - if (vms->virt) { + if (vms->virt && !hvf_enabled()) { /* GICv4 only makes sense if CPU has EL2 */ gics_supported |=3D VIRT_GIC_VERSION_4_MASK; } diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index e438d8c042..7c0eb5eb1e 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/hvf.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -662,6 +663,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (hvf_irqchip_in_kernel()) { + return "hvf-arm-gicv3"; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/include/system/hvf.h b/include/system/hvf.h index d3dcf088b3..dc8da85979 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -26,8 +26,11 @@ #ifdef CONFIG_HVF_IS_POSSIBLE extern bool hvf_allowed; #define hvf_enabled() (hvf_allowed) +extern bool hvf_kernel_irqchip; +#define hvf_irqchip_in_kernel() (hvf_kernel_irqchip) #else /* !CONFIG_HVF_IS_POSSIBLE */ #define hvf_enabled() 0 +#define hvf_irqchip_in_kernel() 0 #endif /* !CONFIG_HVF_IS_POSSIBLE */ =20 #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf") diff --git a/system/vl.c b/system/vl.c index 3b7057e6c6..1c072d15a4 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1773,6 +1773,8 @@ static void qemu_apply_legacy_machine_options(QDict *= qdict) false); object_register_sugar_prop(ACCEL_CLASS_NAME("whpx"), "kernel-irqch= ip", value, false); + object_register_sugar_prop(ACCEL_CLASS_NAME("hvf"), "kernel-irqchi= p", value, + false); qdict_del(qdict, "kernel-irqchip"); } =20 --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433818; cv=none; d=zohomail.com; s=zohoarc; b=IIBwl4yGqzAY5/gepCn/4UCopYB0F4BSNphMnZ4aG3vXif/n6Yik7ogqceT+zt1xAfgc8J0onZNaDPbiXbQzHy1GUkE/YChBP9lE0x/5+1nIVoud7siC8Soir5ZcAiNcBZ9bgc7fvxuU7X1SJOe26Z/RtmTCLWe/BcChQFVM3RY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433818; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DekRPyqD95GZgQR0lU+JTQs/LwEyYeukO06spM11U3Q=; b=RTFVeuKifWek4CxHOeDMaQzGtqVe4bsYvSUWGgB5PWV1r78JC2f8vizButtEXAe+N1hlTdCW/Q6kBSzNbitWoWnHi5YZ5/OjTCpYKre3DTyjItesJldCxzdb6CnnFVljTNPwnJEwuXI0GHdMYYVWSVo48GylM2mBbVo9X2Xvmck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753433818242937.3746386894608; Fri, 25 Jul 2025 01:56:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEDr-0007d4-U4; Fri, 25 Jul 2025 04:56:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDp-0007Yf-LK for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:09 -0400 Received: from p-west3-cluster2-host4-snip4-10.eps.apple.com ([57.103.74.83] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDn-0001u8-OL for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:09 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id A5C11180021B; Fri, 25 Jul 2025 08:56:00 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 7B9311800094; Fri, 25 Jul 2025 08:55:57 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=DekRPyqD95GZgQR0lU+JTQs/LwEyYeukO06spM11U3Q=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=Thln2EomONlKzHqNB+G2GRJQPfuddeDNrcgE4LcU1mKm0X6sek9P+IkaaMoO9fabpggM+kYTwvUg76XtXnhrfaC5+GXIfOE9jZv46QpSEO2GOMp4VRBa8clTOmcWrIxwhILB8cMqgmNEzr36thnyMPpbtdwhIBV1GZUSCzHYTV7A3bDUg2Q8WBWcVFzocCJlmOPWQ15Z5apvlW87d5nwWyMQ2T8gdNof0qcBWa/0GAVwxyoC34zF9e9KzM3DZr8lnFYT+pXrHKQrFLZABS0gCZAC61jSHGqcaUY+gtUxhHsbksRTLbPu4pLwKkxMAK21JKdfrc7E+bx1zvfPdMA+9A== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 3/9] target/arm: hvf: instantiate GIC early Date: Fri, 25 Jul 2025 10:55:39 +0200 Message-Id: <20250725085545.93619-4-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: uQqfgiQS5rkAUghiTINqXPCd_W7IXyu4 X-Proofpoint-ORIG-GUID: uQqfgiQS5rkAUghiTINqXPCd_W7IXyu4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfX4uky9Uno6ecS IJZoEpAMfKDpQyRyUz2Md8B6eMVzbU1wglWGEqJLdiF6DoIQamOYAgYo7CK5lNJKOXYFjhUAuAf NUCaI9TV70rEkLt4Ii1Kv76v+fx4b7wKQ4i+ZwcvfkSLrPG7FV6jRByqFKv/4jabWOWWXXOK+0f Dn3zEZqLo5M6JCir5WqNdajyo3TUiqTV3iE7fMW2rMJxCLaDY+qRAbGyPviYf45uJlOgAISK9xS AAxAlXMyF7zquCyR4DnpLLO03j0tdlSaNscieBqCDCsKY8h+WlMMdKUzPcb3j++9xyAlmZGbk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 suspectscore=0 spamscore=0 mlxlogscore=616 malwarescore=0 phishscore=0 bulkscore=0 mlxscore=0 clxscore=1030 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.83; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433819475116600 Content-Type: text/plain; charset="utf-8" While figuring out a better spot for it, put it in hv_arch_vm_create(). Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index edfd29de75..bb31df90b8 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1001,6 +1001,21 @@ hv_return_t hvf_arch_vm_create(MachineState *ms, uin= t32_t pa_range) chosen_ipa_bit_size =3D pa_range; =20 ret =3D hv_vm_create(config); + if (hvf_irqchip_in_kernel()) { + /* + * Instantiate GIC. + * This must be done prior to the creation of any vCPU + * but past hv_vm_create() + */ + hv_gic_config_t cfg =3D hv_gic_config_create(); + hv_gic_config_set_distributor_base(cfg, 0x08000000); + hv_gic_config_set_redistributor_base(cfg, 0x080A0000); + hv_return_t err =3D hv_gic_create(cfg); + if (err !=3D HV_SUCCESS) { + error_report("error creating platform VGIC"); + goto cleanup; + } + } =20 cleanup: os_release(config); --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433893; cv=none; d=zohomail.com; s=zohoarc; b=Ec8F3Ibud6hSA3kbmSLo0wUu8OF6BaJyaMTaYCTfZME6rMIHOiF6SE9s95iHkLT67E3+bJAKffGmm7gzTEaKB6hquYfp//w/ki1Fr0unPZ5zbVqBstHlJRgJd+PxX0bZuyklhNTsY6WLyQu1mvz6yOeHDvgwdzle5u2s+6TaXNQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433893; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cBn1WfKnGFblnfiu+ECL4GTAAk/dYzreQo9gWD9hOmQ=; b=HLVM8V0gL8bZ8gJRuPxMRVRozcymAjKRHBF0mttlhggWmnod+Lsmz5CBK1Sy45BCe7x1/sBoVzTIIiuaSi+vDklr8GTMbm/QGjyp/wSRs0iE/UzPJEFgaasQc74jytnZ44YCJE/TSF2yFxdp3H0ixH/HDXQZ4jFq3tNXT1/bSxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753433893942264.3019565370646; Fri, 25 Jul 2025 01:58:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEDt-0007fm-1Z; Fri, 25 Jul 2025 04:56:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDr-0007d2-PV for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:11 -0400 Received: from p-west3-cluster4-host9-snip4-7.eps.apple.com ([57.103.74.238] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDq-0001uZ-74 for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:11 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id EFA1F1800209; Fri, 25 Jul 2025 08:56:03 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 7760C18000B8; Fri, 25 Jul 2025 08:56:00 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=cBn1WfKnGFblnfiu+ECL4GTAAk/dYzreQo9gWD9hOmQ=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=dKdjDAMvvsw2y5uVzOmWpynu0oAw9EREEECtXdF+B/hipHt5cvtvkV14N4mStSscOnifOcZDJMx08ZuAiXkWODYuFqkU0uLrin2fyJyzxQ6amlDmPb6yNrcRNWg3viC77K4P4OsPGHhr/N0EW/AukXgrzrJpc5JkS/IQ8pd81l9h26aHlKkYI6M9hVFHgX7u3FiCTl718aI5eXjhx0PUDGC5prRWi95jU6SMAxTdZLAt0/sxkMFIZyV2aAlCBCAyTXObeOrIFORE95sZAI38uchPFGTySN8clT3MknQgjltJY9C/mQCjjCvXlQrL3cn36LM6VLpCMmnU6TO3ylAJ1w== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 4/9] target/arm: add asserts for code paths not leveraged when using the vGIC Date: Fri, 25 Jul 2025 10:55:40 +0200 Message-Id: <20250725085545.93619-5-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: V-3nCKTX28TIiCqpkctns3c9gKtgpOJ6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfX1/ve2PByr/ZI uHUALPlSq/TUAruYSJJOblgjV31BZO+NEEr1RspQJ5hImtGQE1CALi7WbyE4BWReD1hJBvLQrJW 5uEcRR/aoIGvULT5EyYoRZjUShwq4iE0m8ohl4AvUFM7/qAY7kIMhTFmYFIt/R5BMheTJlXMaC/ O9b3W1O23mQxepqR3Ba7wD80IbmnuLfZbxT3qqYiqIph5A5qEvOdH4KBug21avLDbPlCDZ+wacD tw8E5OXWSpTnvYVMJuBIoe4xIXFIuUJMDAa0tNCjwkLc9+mzZBK90oUoolB9gYkBrV/wbJ2K0= X-Proofpoint-ORIG-GUID: V-3nCKTX28TIiCqpkctns3c9gKtgpOJ6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 mlxlogscore=662 spamscore=0 malwarescore=0 mlxscore=0 clxscore=1030 phishscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.238; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433896273116600 Content-Type: text/plain; charset="utf-8" When using the vGIC, timers are directly handled by the platform, so no vme= xits ought to happen in that case. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index bb31df90b8..7b4e8297af 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1378,6 +1378,9 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: case SYSREG_ICC_CTLR_EL1: + if (hvf_irqchip_in_kernel()) { + abort(); + } /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ if (hvf_sysreg_read_cp(cpu, reg, val)) { return 0; @@ -1694,6 +1697,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_ICC_SGI0R_EL1: case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: + if (hvf_irqchip_in_kernel()) { + abort(); + } /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ if (hvf_sysreg_write_cp(cpu, reg, val)) { return 0; @@ -1957,6 +1963,10 @@ int hvf_vcpu_exec(CPUState *cpu) /* This is the main one, handle below. */ break; case HV_EXIT_REASON_VTIMER_ACTIVATED: + /* This is only for when a user-mode irqchip is used. */ + if (hvf_irqchip_in_kernel()) { + assert("vtimer activated vmexit when using platform GIC"); + } qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); cpu->accel->vtimer_masked =3D true; return 0; --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433832; cv=none; d=zohomail.com; s=zohoarc; b=BSvMRtw97VwZXUGYgZVRtUqAIHq/h0DqEOLPxezgEivXVM8omOnBsjbRJvsoMuBwRYlyLTXdvMXmvdeIjPnVlGfGY5aP38KtfwAFtqJF57BiV+/YFF7DfJwwXYZLm5kM18UOWqtny/gg0zTR94qs+KPms+zjYxVcWMGP0TmBqH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433832; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EpKTZUrzGqh7QlkHDN+x4Y1lmFmnUo3cInD8kXnLXJM=; b=lr6xXz2Vzdoq8yYDdPQEuFqQefQ1BC8YzBXk4RRrLHaQbRXPzISGXJpAZ5SDUQRNiZrM0E946eDG4En8QHUZacF07kPUXHR1kRMfdujZC2jnLMCDfX9pBfq7+UsVtTncsWRmYFh27BNqOFU66u177mWfqIf00xo7nSIVxYWcEHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753433832832750.2262012373741; Fri, 25 Jul 2025 01:57:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEDx-0007m5-HC; Fri, 25 Jul 2025 04:56:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDu-0007hi-LB for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:15 -0400 Received: from p-west3-cluster2-host12-snip4-5.eps.apple.com ([57.103.74.98] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDq-0001uk-Cu for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:13 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id C5B831800094; Fri, 25 Jul 2025 08:56:06 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 744671800221; Fri, 25 Jul 2025 08:56:03 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=EpKTZUrzGqh7QlkHDN+x4Y1lmFmnUo3cInD8kXnLXJM=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=gBwOlyWDK8icTlBCKACMC6aZ9YbXn2uFWmywKTK2pCQRdBlw3e3menUNO5FnzMli3g/X1lyFhg7YIkqgHp632peVHPs8Qgi1y7QgXju+lmhJJ4Lp0eBDbtYkFRbflwDNrURTO9gqMt+j5q829Ury05IFhEgQyxuHr+7VCV7xfcNyHR41LYXrpZju5/fJCI81RWY26aGDsVJ1H+NnpG7IVR3lU4vwaZYytYnoF6kgczfDjpD14QvYzxjZl2fCkGoPc0ZQaOLBURAo4CZzmYv6Qg3x9r5qticxVvUE1iNiUEDiKeMcDdE2VjSG/IjRVoypiActoofRZ1Qh6tru1zZcDg== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 5/9] hw/intc: Add hvf vGIC interrupt controller support Date: Fri, 25 Jul 2025 10:55:41 +0200 Message-Id: <20250725085545.93619-6-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: jul_mPOVoW7TYH-34x85vlTG-_EuyUNU X-Proofpoint-ORIG-GUID: jul_mPOVoW7TYH-34x85vlTG-_EuyUNU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfX6LPO2QAl4y+P FObyMNYU36roJa43dtJfI5wftT2syKRBpK9CIipeyl9nc8sYmu48053QiWEHT0CZx3ZhabLvWw8 tZH4TAvjnfA9sUO3vlsuelCRY0P874x7a1ggky22qXG23mcxh3NfnQiOnSV/qn0mqIasKmU18VO 6YmCpLmWI3D37M+R276PbPbaRSU3tZaJK0Hs1mdoqy/5q2Az3M567SYTVxYcTuu4TzMVsE4+TQy gbqRt5vPMAEw4nE8gZr1Kb76woGR6JVNmd1RcvcG4FxX+UtYT4VcXdKmg1y/10Py8VDG5HTM0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 mlxscore=0 adultscore=0 clxscore=1030 mlxlogscore=999 phishscore=0 spamscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.98; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433833729116600 Content-Type: text/plain; charset="utf-8" This opens up the door to nested virtualisation support. Signed-off-by: Mohamed Mediouni --- hw/intc/arm_gicv3_hvf.c | 624 ++++++++++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + 2 files changed, 625 insertions(+) create mode 100644 hw/intc/arm_gicv3_hvf.c diff --git a/hw/intc/arm_gicv3_hvf.c b/hw/intc/arm_gicv3_hvf.c new file mode 100644 index 0000000000..23f1641318 --- /dev/null +++ b/hw/intc/arm_gicv3_hvf.c @@ -0,0 +1,624 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller using HVF platform support + * + * Copyright (c) 2025 Mohamed Mediouni + * Based on vGICv3 KVM code by Pavel Fedin + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "system/runstate.h" +#include "system/hvf.h" +#include "system/hvf_int.h" +#include "gicv3_internal.h" +#include "vgic_common.h" +#include "qom/object.h" +#include "target/arm/cpregs.h" +#include + +struct HVFARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#define TYPE_HVF_GICV3 "hvf-arm-gicv3" +typedef struct HVFARMGICv3Class HVFARMGICv3Class; + +/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ +DECLARE_OBJ_CHECKERS(GICv3State, HVFARMGICv3Class, + HVF_GICV3, TYPE_HVF_GICV3); + +/* + * Loop through each distributor IRQ related register; since bits + * corresponding to SPIs and PPIs are RAZ/WI when affinity routing + * is enabled, we skip those. + */ +#define for_each_dist_irq_reg(_irq, _max, _field_width) \ + for (_irq =3D GIC_INTERNAL; _irq < _max; _irq +=3D (32 / _field_width)) + +static void hvf_dist_get_priority(GICv3State *s, hv_gic_distributor_reg_t = offset + , uint8_t *bmp) +{ + uint64_t reg; + uint32_t *field; + int irq; + field =3D (uint32_t *)(bmp); + + for_each_dist_irq_reg(irq, s->num_irq, 8) { + hv_gic_get_distributor_reg(offset, ®); + *field =3D reg; + offset +=3D 4; + field++; + } +} + +static void hvf_dist_put_priority(GICv3State *s, hv_gic_distributor_reg_t = offset + , uint8_t *bmp) +{ + uint32_t reg, *field; + int irq; + field =3D (uint32_t *)(bmp); + + for_each_dist_irq_reg(irq, s->num_irq, 8) { + reg =3D *field; + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + field++; + } +} + +static void hvf_dist_get_edge_trigger(GICv3State *s, hv_gic_distributor_re= g_t offset, + uint32_t *bmp) +{ + uint64_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 2) { + hv_gic_get_distributor_reg(offset, ®); + reg =3D half_unshuffle32(reg >> 1); + if (irq % 32 !=3D 0) { + reg =3D (reg << 16); + } + *gic_bmp_ptr32(bmp, irq) |=3D reg; + offset +=3D 4; + } +} + +static void hvf_dist_put_edge_trigger(GICv3State *s, hv_gic_distributor_re= g_t offset, + uint32_t *bmp) +{ + uint32_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 2) { + reg =3D *gic_bmp_ptr32(bmp, irq); + if (irq % 32 !=3D 0) { + reg =3D (reg & 0xffff0000) >> 16; + } else { + reg =3D reg & 0xffff; + } + reg =3D half_shuffle32(reg) << 1; + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + } +} + +/* Read a bitmap register group from the kernel VGIC. */ +static void hvf_dist_getbmp(GICv3State *s, hv_gic_distributor_reg_t offset= , uint32_t *bmp) +{ + uint64_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 1) { + + hv_gic_get_distributor_reg(offset, ®); + *gic_bmp_ptr32(bmp, irq) =3D reg; + offset +=3D 4; + } +} + +static void hvf_dist_putbmp(GICv3State *s, hv_gic_distributor_reg_t offset, + hv_gic_distributor_reg_t clroffset, uint32_t *= bmp) +{ + uint32_t reg; + int irq; + + for_each_dist_irq_reg(irq, s->num_irq, 1) { + /* + * If this bitmap is a set/clear register pair, first write to the + * clear-reg to clear all bits before using the set-reg to write + * the 1 bits. + */ + if (clroffset !=3D 0) { + reg =3D 0; + hv_gic_set_distributor_reg(clroffset, reg); + clroffset +=3D 4; + } + reg =3D *gic_bmp_ptr32(bmp, irq); + hv_gic_set_distributor_reg(offset, reg); + offset +=3D 4; + } +} + +static void hvf_gicv3_check(GICv3State *s) +{ + uint64_t reg; + uint32_t num_irq; + + /* Sanity checking s->num_irq */ + hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_TYPER, ®); + num_irq =3D ((reg & 0x1f) + 1) * 32; + + if (num_irq < s->num_irq) { + error_report("Model requests %u IRQs, but HVF supports max %u", + s->num_irq, num_irq); + abort(); + } +} + +static void hvf_gicv3_put(GICv3State *s) +{ + uint32_t reg; + uint64_t reg64, redist_typer; + int ncpu, i; + + hvf_gicv3_check(s); + + hv_vcpu_t vcpu0 =3D s->cpu[0].cpu->accel->fd; + hv_gic_get_redistributor_reg(vcpu0, HV_GIC_REDISTRIBUTOR_REG_GICR_TYPER + , &redist_typer); + + reg =3D s->gicd_ctlr; + hv_gic_set_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, reg); + + if (redist_typer & GICR_TYPER_PLPIS) { + error_report("ITS is not supported on HVF."); + abort(); + } + + /* Redistributor state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + + reg =3D c->gicr_waker; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= GROUPR0, reg); + + reg =3D c->gicr_igroupr0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= GROUPR0, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CENABLER0, reg); + reg =3D c->gicr_ienabler0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= SENABLER0, reg); + + /* Restore config before pending so we treat level/edge correctly = */ + reg =3D half_shuffle32(c->edge_trigger >> 16) << 1; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CFGR1, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CPENDR0, reg); + reg =3D c->gicr_ipendr0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= SPENDR0, reg); + + reg =3D ~0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= CACTIVER0, reg); + reg =3D c->gicr_iactiver0; + hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_I= SACTIVER0, reg); + + for (i =3D 0; i < GIC_INTERNAL; i +=3D 4) { + reg =3D c->gicr_ipriorityr[i] | + (c->gicr_ipriorityr[i + 1] << 8) | + (c->gicr_ipriorityr[i + 2] << 16) | + (c->gicr_ipriorityr[i + 3] << 24); + hv_gic_set_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, reg); + } + } + + /* s->enable bitmap -> GICD_ISENABLERn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0 + , GICD_ICENABLER, s->enabled); + + /* s->group bitmap -> GICD_IGROUPRn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0 + , 0, s->group); + + /* Restore targets before pending to ensure the pending state is set on + * the appropriate CPU interfaces in the kernel + */ + + /* s->gicd_irouter[irq] -> GICD_IROUTERn */ + for (i =3D GIC_INTERNAL; i < s->num_irq; i++) { + uint32_t offset =3D HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32 + (sizeo= f(uint32_t) * i) + - (sizeof(uint32_t) * GIC_INTERNAL); + hv_gic_set_distributor_reg(offset, s->gicd_irouter[i]); + } + + + /* + * s->trigger bitmap -> GICD_ICFGRn + * (restore configuration registers before pending IRQs so we treat + * level/edge correctly) + */ + hvf_dist_put_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0, s->ed= ge_trigger); + + /* s->pending bitmap -> GICD_ISPENDRn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0, + HV_GIC_DISTRIBUTOR_REG_GICD_ICPENDR0, s->pending); + + /* s->active bitmap -> GICD_ISACTIVERn */ + hvf_dist_putbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0, + HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0, s->active); + + /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ + hvf_dist_put_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0, s->g= icd_ipriority); + + /* CPU interface state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + int num_pri_bits; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, c->icc_sre_el1); + + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1, + c->icc_ctlr_el1[GICV3_NS]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1, + c->icc_igrpen[GICV3_G0]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1, + c->icc_igrpen[GICV3_G1NS]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1, c->icc_pmr_el1); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1, c->icc_bpr[GICV3= _G0]); + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1, c->icc_bpr[GICV3= _G1NS]); + + num_pri_bits =3D ((c->icc_ctlr_el1[GICV3_NS] & + ICC_CTLR_EL1_PRIBITS_MASK) >> + ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; + + switch (num_pri_bits) { + case 7: + reg64 =3D c->icc_apr[GICV3_G0][3]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3, reg64); + reg64 =3D c->icc_apr[GICV3_G0][2]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2, reg64); + /* fall through */ + case 6: + reg64 =3D c->icc_apr[GICV3_G0][1]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1, reg64); + /* fall through */ + default: + reg64 =3D c->icc_apr[GICV3_G0][0]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1, reg64); + } + + switch (num_pri_bits) { + case 7: + reg64 =3D c->icc_apr[GICV3_G1NS][3]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3, reg64); + reg64 =3D c->icc_apr[GICV3_G1NS][2]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2, reg64); + /* fall through */ + case 6: + reg64 =3D c->icc_apr[GICV3_G1NS][1]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1, reg64); + /* fall through */ + default: + reg64 =3D c->icc_apr[GICV3_G1NS][0]; + hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, reg64); + } + } +} + +static void hvf_gicv3_get(GICv3State *s) +{ + uint64_t reg, redist_typer; + int ncpu, i; + + hvf_gicv3_check(s); + + hv_vcpu_t vcpu0 =3D s->cpu[0].cpu->accel->fd; + hv_gic_get_redistributor_reg(vcpu0, + HV_GIC_REDISTRIBUTOR_REG_GICR_TYPER, &redist_typer); + + hv_gic_get_distributor_reg(HV_GIC_DISTRIBUTOR_REG_GICD_CTLR, ®); + s->gicd_ctlr =3D reg; + + /* Redistributor state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_IGROUPR0, ®); + c->gicr_igroupr0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ISENABLER0, ®); + c->gicr_ienabler0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ICFGR1, ®); + c->edge_trigger =3D half_unshuffle32(reg >> 1) << 16; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ISPENDR0, ®); + c->gicr_ipendr0 =3D reg; + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_ISACTIVER0, ®); + c->gicr_iactiver0 =3D reg; + + for (i =3D 0; i < GIC_INTERNAL; i +=3D 4) { + hv_gic_get_redistributor_reg(vcpu, + HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, ®); + c->gicr_ipriorityr[i] =3D extract32(reg, 0, 8); + c->gicr_ipriorityr[i + 1] =3D extract32(reg, 8, 8); + c->gicr_ipriorityr[i + 2] =3D extract32(reg, 16, 8); + c->gicr_ipriorityr[i + 3] =3D extract32(reg, 24, 8); + } + } + + if (redist_typer & GICR_TYPER_PLPIS) { + error_report("ITS is not supported on HVF."); + abort(); + } + + /* GICD_IGROUPRn -> s->group bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_IGROUPR0, s->group); + + /* GICD_ISENABLERn -> s->enabled bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISENABLER0, s->enabled); + + /* GICD_ISPENDRn -> s->pending bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISPENDR0, s->pending); + + /* GICD_ISACTIVERn -> s->active bitmap */ + hvf_dist_getbmp(s, HV_GIC_DISTRIBUTOR_REG_GICD_ISACTIVER0, s->active); + + /* GICD_ICFGRn -> s->trigger bitmap */ + hvf_dist_get_edge_trigger(s, HV_GIC_DISTRIBUTOR_REG_GICD_ICFGR0 + , s->edge_trigger); + + /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ + hvf_dist_get_priority(s, HV_GIC_DISTRIBUTOR_REG_GICD_IPRIORITYR0 + , s->gicd_ipriority); + + /* GICD_IROUTERn -> s->gicd_irouter[irq] */ + for (i =3D GIC_INTERNAL; i < s->num_irq; i++) { + uint32_t offset =3D HV_GIC_DISTRIBUTOR_REG_GICD_IROUTER32 + + (sizeof(uint32_t) * i) - (sizeof(uint32_t) * GIC_INTERNAL); + hv_gic_get_distributor_reg(offset, &s->gicd_irouter[i]); + } + + /* CPU interface state (one per CPU) */ + + for (ncpu =3D 0; ncpu < s->num_cpu; ncpu++) { + GICv3CPUState *c =3D &s->cpu[ncpu]; + hv_vcpu_t vcpu =3D c->cpu->accel->fd; + int num_pri_bits; + + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, &c->icc_sre_el1); + + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1, + &c->icc_ctlr_el1[GICV3_NS]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1, + &c->icc_igrpen[GICV3_G0]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1, + &c->icc_igrpen[GICV3_G1NS]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1 + , &c->icc_pmr_el1); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1 + , &c->icc_bpr[GICV3_G0]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1 + , &c->icc_bpr[GICV3_G1NS]); + num_pri_bits =3D ((c->icc_ctlr_el1[GICV3_NS] & + ICC_CTLR_EL1_PRIBITS_MASK) >> + ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; + + switch (num_pri_bits) { + case 7: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3 + , &c->icc_apr[GICV3_G0][3]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2 + , &c->icc_apr[GICV3_G0][2]); + /* fall through */ + case 6: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1 + , &c->icc_apr[GICV3_G0][1]); + /* fall through */ + default: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + , &c->icc_apr[GICV3_G0][0]); + } + + switch (num_pri_bits) { + case 7: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3 + , &c->icc_apr[GICV3_G1NS][3]); + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2 + , &c->icc_apr[GICV3_G1NS][2]); + /* fall through */ + case 6: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1 + , &c->icc_apr[GICV3_G1NS][1]); + /* fall through */ + default: + hv_gic_get_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + , &c->icc_apr[GICV3_G1NS][0]); + } + } +} + +static void hvf_gicv3_set_irq(void *opaque, int irq, int level) +{ + GICv3State *s =3D (GICv3State *)opaque; + if (irq > s->num_irq) { + return; + } + hv_gic_set_spi(GIC_INTERNAL + irq, !!level); +} + +static void hvf_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3State *s; + GICv3CPUState *c; + + c =3D (GICv3CPUState *)env->gicv3state; + s =3D c->gic; + + c->icc_pmr_el1 =3D 0; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; + + c->icc_sre_el1 =3D 0x7; + memset(c->icc_apr, 0, sizeof(c->icc_apr)); + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); + + if (s->migration_blocker) { + return; + } + + /* Initialize to actual HW supported configuration */ + hv_gic_get_icc_reg(c->cpu->accel->fd, + HV_GIC_ICC_REG_CTLR_EL1, &c->icc_ctlr_el1[GICV3_NS]); + + c->icc_ctlr_el1[GICV3_S] =3D c->icc_ctlr_el1[GICV3_NS]; +} + +static void hvf_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + HVFARMGICv3Class *kgc =3D HVF_GICV3_GET_CLASS(s); + + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj, type); + } + + hvf_gicv3_put(s); +} + + +/* + * CPU interface registers of GIC needs to be reset on CPU reset. + * For the calling arm_gicv3_icc_reset() on CPU reset, we register + * below ARMCPRegInfo. As we reset the whole cpu interface under single + * register reset, we define only one register of CPU interface instead + * of defining all the registers. + */ +static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { + { .name =3D "ICC_CTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 4, + /* + * If ARM_CP_NOP is used, resetfn is not called, + * So ARM_CP_NO_RAW is appropriate type. + */ + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, + .readfn =3D arm_cp_read_zero, + .writefn =3D arm_cp_write_ignore, + /* + * We hang the whole cpu interface reset routine off here + * rather than parcelling it out into one little function + * per register + */ + .resetfn =3D hvf_gicv3_icc_reset, + }, +}; + +static void hvf_gicv3_realize(DeviceState *dev, Error **errp) +{ + GICv3State *s =3D HVF_GICV3(dev); + HVFARMGICv3Class *kgc =3D HVF_GICV3_GET_CLASS(s); + Error *local_err =3D NULL; + int i; + + kgc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by HVF"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, hvf_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); + + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + } + + if (s->maint_irq && s->maint_irq !=3D HV_GIC_INT_MAINTENANCE) { + error_setg(errp, "vGIC maintenance IRQ mismatch with the hardcoded= one in HVF."); + return; + } +} + +static void hvf_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + HVFARMGICv3Class *kgc =3D HVF_GICV3_CLASS(klass); + + agcc->pre_save =3D hvf_gicv3_get; + agcc->post_load =3D hvf_gicv3_put; + + device_class_set_parent_realize(dc, hvf_gicv3_realize, + &kgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, hvf_gicv3_reset_hold, NUL= L, + &kgc->parent_phases); +} + +static const TypeInfo hvf_arm_gicv3_info =3D { + .name =3D TYPE_HVF_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D hvf_gicv3_class_init, + .class_size =3D sizeof(HVFARMGICv3Class), +}; + +static void hvf_gicv3_register_types(void) +{ + type_register_static(&hvf_arm_gicv3_info); +} + +type_init(hvf_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3137521a4a..f446e966e3 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -42,6 +42,7 @@ specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('a= rm_gicv3_cpuif_common.c specific_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.= c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_true: files('= arm_gicv3_hvf.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433853; cv=none; d=zohomail.com; s=zohoarc; b=PUgbnc2e7cUU5LWMYg7eI9V2pvsXpMTvEnM33/aw/i1eepQYqCFZUDKORhdWrIPqZpgALpSLmloZ30TKY0lDSY2InasskjT/zWZrigawi3VBNbexiQsGJtcTtLlJpNNJges9Yv5m0hdmqMwWQQZ2qXOc2I2+0/XpsJ65RjPJAHU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433853; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2+oeV/qLEBELCeNzr/+3bJX/+e9peu0Bo6BJXQ9Vgx8=; b=iwXvTDZzZjx7P6nmtWsK3zCiusBcibZJg6QpXsUc44iSEwQcfm4e0kv1qTdRD1pmfQVkSJ5+OPsVFcusQSkpTtikB3R356dzLCFfq7P3guZtiuraZZwOvkSKg7Qj+aeFHbDKOfg6uBir+zQkT5WDy+tdgGmfqMKthePuoJe2FYQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753433853615964.3566354908068; Fri, 25 Jul 2025 01:57:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEDz-0007rl-7F; Fri, 25 Jul 2025 04:56:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDw-0007jR-2c for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:16 -0400 Received: from p-west3-cluster2-host9-snip4-10.eps.apple.com ([57.103.74.13] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDt-0001vn-VQ for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:15 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id 628B61800221; Fri, 25 Jul 2025 08:56:09 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 75F21180020A; Fri, 25 Jul 2025 08:56:06 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=2+oeV/qLEBELCeNzr/+3bJX/+e9peu0Bo6BJXQ9Vgx8=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=WzUM2qj9Rh5yskebJs96JJmdDxrEKRMItGzmTRisA+S05uT3Bhx+StXE+bhEs1ijDhTZ4Mx4qX5XcTA/PG1ydTQjSi6I+1Av/Sxsc3mjk3yTBZkEVvXSx78UT9Uf3nQvWPEkVhEgpSRZ0OMvIYUiWanrrjS+Z4PQt/Q6JV5aUB0MfBAFSjDjnWKoyu6Q3ktOjIKqZR/OrES8EIQ9XUiCILODjdLZefp8mGuOiae+cr5zSERioSMUgCJkZgrK1wISKMYQSb72wlH0jthRUx8BkQDyWceH8QW8vn4BxE/28Kbvh2jjIvzkfXQ801PMtCcieGyTpYgtPYZRlyAlGI51wg== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 6/9] hw/arm, target/arm: nested virtualisation on HVF Date: Fri, 25 Jul 2025 10:55:42 +0200 Message-Id: <20250725085545.93619-7-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfXwb539ZTEQaE3 bkX0dF7m2wP66UlmVS6oL+A8F0+uyJLqTuYMLFa4QqNwnSw5ZCQsmYLYFqOVIxqTASkaCiYb4ow VlbyKn/nXwBY7dHeAG71p2UnX49ZI4vKiEHQQepNyixu9sTCmaTfN2RelDAKUq0egEo7abviQCH 7KVauCsmOs38hkd49zjBBmU3l8Bb1Z2VxmCBfeqYBhUHeLOXgt9KB7tKEco9ZyyYpoN+dELELRw oKmgMe7EI1yIcRlDpxUfB234UrWRzUqWPpMtepdQe5jKsmeG1E2YWBtoUzYvSuLfz2LCAoZxo= X-Proofpoint-ORIG-GUID: gaDKiDnxaunoXy-MnL-biczS5jkbx3Ub X-Proofpoint-GUID: gaDKiDnxaunoXy-MnL-biczS5jkbx3Ub X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 suspectscore=0 spamscore=0 clxscore=1030 malwarescore=0 mlxscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.13; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433855991116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni --- hw/arm/virt.c | 9 ++++++--- target/arm/hvf-stub.c | 15 +++++++++++++++ target/arm/hvf/hvf.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/hvf_arm.h | 3 +++ 4 files changed, 59 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a26bde4c75..ab27547707 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -817,8 +817,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) g_assert_not_reached(); } =20 - if (kvm_enabled() && vms->virt && - (revision !=3D 3 || !kvm_irqchip_in_kernel())) { + if (kvm_enabled() && vms->virt && (revision !=3D 3 || !kvm_irqchip_in_= kernel())) { error_report("KVM EL2 is only supported with in-kernel GICv3"); exit(1); } @@ -2278,7 +2277,8 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled())= { + if (vms->virt && !kvm_enabled() && !tcg_enabled() + &&!hvf_enabled() && !qtest_enabled()) { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", current_accel_name()); @@ -2548,6 +2548,9 @@ static void virt_set_virt(Object *obj, bool value, Er= ror **errp) VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 vms->virt =3D value; +#if defined(CONFIG_HVF) && defined(__aarch64__) + hvf_arm_el2_enable(value); +#endif } =20 static bool virt_get_highmem(Object *obj, Error **errp) diff --git a/target/arm/hvf-stub.c b/target/arm/hvf-stub.c index ff137267a0..95ec4ea62f 100644 --- a/target/arm/hvf-stub.c +++ b/target/arm/hvf-stub.c @@ -18,3 +18,18 @@ uint32_t hvf_arm_get_max_ipa_bit_size(void) { g_assert_not_reached(); } + +bool hvf_arm_el2_supported(void) +{ + g_assert_not_reached(); +} + +bool hvf_arm_el2_enabled(void) +{ + g_assert_not_reached(); +} + +void hvf_arm_el2_enable(bool) +{ + g_assert_not_reached(); +} diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 7b4e8297af..c32e6ab289 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -26,6 +26,7 @@ #include "system/address-spaces.h" #include "system/memory.h" #include "hw/boards.h" +#include "hw/arm/virt.h" #include "hw/irq.h" #include "qemu/main-loop.h" #include "system/cpus.h" @@ -891,6 +892,10 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) (1ULL << ARM_FEATURE_PMU) | (1ULL << ARM_FEATURE_GENERIC_TIMER); =20 + if (hvf_arm_el2_enabled()) { + ahcf->features |=3D 1ULL << ARM_FEATURE_EL2; + } + /* We set up a small vcpu to extract host registers */ =20 if (hv_vcpu_create(&fd, &exit, NULL) !=3D HV_SUCCESS) { @@ -964,6 +969,25 @@ uint32_t hvf_arm_get_max_ipa_bit_size(void) return round_down_to_parange_bit_size(max_ipa_size); } =20 +bool hvf_arm_el2_supported(void) +{ + bool is_nested_virt_supported; + hv_return_t ret =3D hv_vm_config_get_el2_supported(&is_nested_virt_sup= ported); + assert_hvf_ok(ret); + return is_nested_virt_supported; +} + +static bool is_nested_virt_enabled =3D false; +bool hvf_arm_el2_enabled(void) +{ + return is_nested_virt_enabled; +} + +void hvf_arm_el2_enable(bool enable) +{ + is_nested_virt_enabled =3D enable; +} + void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) { if (!arm_host_cpu_features.dtb_compatible) { @@ -1000,6 +1024,13 @@ hv_return_t hvf_arch_vm_create(MachineState *ms, uin= t32_t pa_range) } chosen_ipa_bit_size =3D pa_range; =20 + if (hvf_arm_el2_enabled()) { + ret =3D hv_vm_config_set_el2_enabled(config, true); + if (ret !=3D HV_SUCCESS) { + goto cleanup; + } + } + ret =3D hv_vm_create(config); if (hvf_irqchip_in_kernel()) { /* @@ -1146,6 +1177,10 @@ static bool hvf_handle_psci_call(CPUState *cpu) int target_el =3D 1; int32_t ret =3D 0; =20 + if (hvf_arm_el2_enabled()) { + target_el =3D 2; + } + trace_hvf_psci_call(param[0], param[1], param[2], param[3], arm_cpu_mp_affinity(arm_cpu)); =20 diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea82f2691d..bf55e7ae28 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -24,5 +24,8 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 uint32_t hvf_arm_get_default_ipa_bit_size(void); uint32_t hvf_arm_get_max_ipa_bit_size(void); +bool hvf_arm_el2_supported(void); +bool hvf_arm_el2_enabled(void); +void hvf_arm_el2_enable(bool); =20 #endif --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433905; cv=none; d=zohomail.com; s=zohoarc; b=OcU3Gxw0Y4WJhjMQKh/lygow8mew2mVqJFnA1kZ4rtT/dVW1CQRy3xXxhnEFZmlayB7F2xGk8jYqyFJ7dHFRhQaQOXXD3ZFCgLHNULL5JQaJE3GowH4YJld+ksoASynQzjKX24VajKG2miFRCiBUBTemQliQv+0hLfrI1acK5UY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433905; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=o7HSavF17IoPSUVxM9m4KStfJoakR87pLkUftbbgFiA=; b=TC+sPlGNWWQAL7u6gurrgewnB17f7XbtECplmiTgg39LAJDXlqI6fNMFPzM1mOehU74jkD/LyQoDc1gDV9scBIHCWsY2J6HqRic/mwoTD1ZCgzIR5AQskLFK77LJltDWnN3QWDklN0PPd4bHAbD7ECK5w8I1ikGu3BDs7jJl9rg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753433905482423.6685495784245; Fri, 25 Jul 2025 01:58:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEE4-00082z-9T; Fri, 25 Jul 2025 04:56:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEE0-0007uw-Ow for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:20 -0400 Received: from p-west3-cluster2-host4-snip4-7.eps.apple.com ([57.103.74.80] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDy-0001xn-Ho for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:20 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id 51F1C1800215; Fri, 25 Jul 2025 08:56:12 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 75AA11800223; Fri, 25 Jul 2025 08:56:09 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=o7HSavF17IoPSUVxM9m4KStfJoakR87pLkUftbbgFiA=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=SPao8+kL4zdgApKkwJ9Gbb9kojM3Da773smQsSLMm4buU3457DWzJRFpfGdhwNWKGlmkSkKo9/YIJLOP9Pv5QEj9Usq4PqJSKb9fu3XwVeIEhEOhhPOwTd/EkvEoWnBWPXf6Xp7QyNjyHtmqLVUM0TV92lJ69kWxdD4BcSKB+R5o0qTQsqn7AZJCcYXHEdKpYBL5rX5hzffsJkEgqYhB+f7YhkSNftFqM78DQlve6p+Uqa3JtH9cASvWEDANGkaQdwQiDfR0NL/oL1GccJjjyyAo37jEsjYypIdf4R/Il2xBVme/hRRc7JB39RruNU7ZCCuG+KqOy1pMQF52P/MkUA== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 7/9] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Date: Fri, 25 Jul 2025 10:55:43 +0200 Message-Id: <20250725085545.93619-8-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: un0dC8_aLvOIuQJJwKDuoFe87U3-H9po X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfXyVLOUf4AYxDv AcYg00DemeqTQzVVNDtacI8fMxVP6J+6azhOlYTEHFYP2dQbzcjxnHYTYNJh0Syb4aZIUN+82Jr J7uda7B/zFzHimC1FXxHXFqOikk9ugNzLC0+fEbv52LjVUCUozE0kQEJyMD9RJ2MLYyU3UlDlAh zZKsIBsOStJ5NxtprQdDM+qtNrILTkAfbUccxk3TpRFElXVOh4yMRduUI7D/nY+y0kc2X+rrwSq rUz6C9+pUjRWIqpgINYn9ncbkqfQunSTdHo9kxU9yznp+Z/LtR2CMrNBjavVvGqMtbgfDGqQ8= X-Proofpoint-ORIG-GUID: un0dC8_aLvOIuQJJwKDuoFe87U3-H9po X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 mlxlogscore=770 phishscore=0 spamscore=0 malwarescore=0 clxscore=1030 bulkscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.80; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433906552116600 Content-Type: text/plain; charset="utf-8" HVF traps accesses to CNTHCTL_EL2. For nested guests, HVF traps accesses to= MDCCINT_EL1. Pass through those accesses to the Hypervisor.framework library. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index c32e6ab289..5344e23db1 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -21,6 +21,7 @@ #include "cpregs.h" #include "cpu-sysregs.h" =20 +#include #include =20 #include "system/address-spaces.h" @@ -296,6 +297,10 @@ void hvf_arm_init_debug(void) #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) =20 +/* EL2 registers */ +#define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0) +#define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0) + #define WFX_IS_WFE (1 << 0) =20 #define TMR_CTL_ENABLE (1 << 0) @@ -1388,6 +1393,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t r= eg, uint64_t *val) case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; + case SYSREG_CNTHCTL_EL2: + assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); + return 0; + case SYSREG_MDCCINT_EL1: + assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1704,6 +1715,12 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t = reg, uint64_t val) case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; + case SYSREG_CNTHCTL_EL2: + assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); + return 0; + case SYSREG_MDCCINT_EL1: + assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); + return 0; case SYSREG_LORC_EL1: /* Dummy register */ return 0; --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433818; cv=none; d=zohomail.com; s=zohoarc; b=VluPKBWSVjq9VZfVZkXss0H1qJPPAiYMdtNM99SIcXjQ9GuK0U6JRSg6b382MJzyTU2ozbJm1AmE8Buf6vnZF0mIC+8yxXL8biKJKeWrrCd07QW4cQqhh4QcEL0yphHJQW/Eui7E/aCv7QxhEQT80+KBuF5PLwFugXrA7k1x34M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433818; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H+G8NdbLWhFyN/c0flpd353cGqPvisDi5OyrcVlr0Uw=; b=IFNLHEGFz28mZNUzaGlWYsadjZCS7MHxqCU01lMmY+VGNq+zmpCJOjhD6eIP9d5sf3hfjnjYTt1/BvDcInKgElEqOOxImIVyM4H/OGTfjXB9TEY1q0VKBAV1BkMAMeZiCTJNFRUFta4QpJu11VEhkrPyvicSvSy7XAe14yVAlEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753433818242472.6974722823534; Fri, 25 Jul 2025 01:56:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEE0-0007uV-5r; Fri, 25 Jul 2025 04:56:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDz-0007rR-29 for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:19 -0400 Received: from p-west3-cluster2-host11-snip4-10.eps.apple.com ([57.103.74.93] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEDx-0001xA-AY for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:18 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id 43CE81800099; Fri, 25 Jul 2025 08:56:15 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 65833180020A; Fri, 25 Jul 2025 08:56:12 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=H+G8NdbLWhFyN/c0flpd353cGqPvisDi5OyrcVlr0Uw=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=WvQ0GAQtujcBxp0mSrI6nEq81tBNCRW9elW23wcNVVBbDxnRWl43Dhsg0hQRqHNxxG70N8KaqDEkHerGBCEwaDRoD4rCxANBnhCZV0zCtS8/iZCTx61RvOyBZ2tLXczVBrhJDCkqnQfxb7pOTF/5kZYp7lX2dukTYO153XOdNqAE36pmwd6KUrJ+XvNPx27fORwmR7l9/Hx8gmlkqUSr0+asa1NjrsVc4044w+F0dwktBDBS5z1QVfDhIlPgqImLqi12ETJnPF4Qeu/RFuecgqK//C/Eq1iylzN+YqJbqBoJJUZ0pmAv2YzxULpzvO+cPEGR3myvR0NRimSo+JDyfw== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 8/9] hw/arm: virt: add GICv2m for the case when ITS is not available Date: Fri, 25 Jul 2025 10:55:44 +0200 Message-Id: <20250725085545.93619-9-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 2WqEGet0XPtr9VVUcw4nLjkcm-SXiYzg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfX939l4zMJqQUk MkvyEBwPZUA4CY6y517MiMDmTcbV54EX+lrT7hY15CkZQjBxE9bw356w0YZPsbk+wnTL20WC0pn zO/SJp1BtVkjq7m+loHwH7MwvyQBt0U60Gyk4M0VzlE/uMJrM0Y/JDZbtoOczXKdV9hU5qe/AF1 CsMFr5xjzlJAAkhhVbmpDL6CQXeGnEv1k+TLv3D7zE9rj8oTloNGIZ/8BOwANmx1jb5g3sIV12B UuyR30F+8WaVd+Xx9oH0nwPi0KhGcmKh3LjR+qX+yIlMUUSmDJiX+tdMRuHyCW8Jr4yS+2Hos= X-Proofpoint-GUID: 2WqEGet0XPtr9VVUcw4nLjkcm-SXiYzg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 spamscore=0 clxscore=1030 malwarescore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.93; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433819534116600 Content-Type: text/plain; charset="utf-8" On Hypervisor.framework for macOS and WHPX for Windows, the provided enviro= nment is a GICv3 without ITS. As such, support a GICv3 w/ GICv2m for that scenario. Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 4 +++- hw/arm/virt.c | 8 ++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b01fc4f8ef..969fa3f686 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -848,7 +848,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } - } else { + } + + if (!vms->its && !vms->no_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ab27547707..2d23e7f46f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -952,6 +952,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { create_its(vms); + } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { + create_v2m(vms); } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { create_v2m(vms); } @@ -2407,6 +2409,8 @@ static void machvirt_init(MachineState *machine) vms->ns_el2_virt_timer_irq =3D ns_el2_virt_timer_present() && !vmc->no_ns_el2_virt_timer_irq; =20 + vms->no_gicv3_with_gicv2m =3D vmc->no_gicv3_with_gicv2m; + fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); =20 @@ -3418,6 +3422,7 @@ static void virt_instance_init(Object *obj) vms->its =3D true; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; + vms->no_gicv3_with_gicv2m =3D false; =20 /* Default disallows iommu instantiation */ vms->iommu =3D VIRT_IOMMU_NONE; @@ -3470,8 +3475,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(10, 1) =20 static void virt_machine_10_0_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_10_1_options(mc); compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len); + vmc->no_gicv3_with_gicv2m =3D true; } DEFINE_VIRT_MACHINE(10, 0) =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 365a28b082..725ec18fd2 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -131,6 +131,7 @@ struct VirtMachineClass { bool no_cpu_topology; bool no_tcg_lpa2; bool no_ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; bool no_nested_smmu; }; =20 @@ -178,6 +179,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; CXLState cxl_devices_state; }; =20 --=20 2.39.5 (Apple Git-154) From nobody Sat Nov 15 09:32:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1753433871; cv=none; d=zohomail.com; s=zohoarc; b=YzyBInPG2qc3zjifuigR+nrU5d3o6N6zjGTNyE91MeiaGnuD7//0Nk1fjyNm4Mmj97CSfTU6KLO4e6niMV3ewUSYiQyOAaWW3VCptZoe4ujPCJjqZlUakjopOqAkXFZXTw81PJJ1Ky6OepeTGBNaafpuAmEflhp178oWK0nV04U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753433871; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cEp+5SNb7OEsXQ14HiaE7C8WyWAj0nHhP97faFYP8HQ=; b=j6h8ySawN5WUox119lCf7pkwygmpoc94UsOqLDMIrVoYQGnRnUjhdLGmBTZX01GUX8U+Oh2nT7r/R5A6T+lQRQYPknozhRDzlFzpTXFuYtKwZL+IMLhdktSWaXN65vNgQc1FJKX15gJ6SXatbmaBLuGL/X27r+1Nfw6Io1slPsE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175343387136496.9356751051995; Fri, 25 Jul 2025 01:57:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ufEE8-0008Ft-OQ; Fri, 25 Jul 2025 04:56:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEE6-0008BY-Tk for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:26 -0400 Received: from p-west3-cluster4-host8-snip4-10.eps.apple.com ([57.103.74.151] helo=outbound.ms.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ufEE4-0001zi-Sj for qemu-devel@nongnu.org; Fri, 25 Jul 2025 04:56:26 -0400 Received: from outbound.ms.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPS id F155D18000B9; Fri, 25 Jul 2025 08:56:17 +0000 (UTC) Received: from localhost.localdomain (ms-asmtp-me-k8s.p00.prod.me.com [17.57.154.37]) by p00-icloudmta-asmtp-us-west-3a-20-percent-0 (Postfix) with ESMTPSA id 314EC180022E; Fri, 25 Jul 2025 08:56:15 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=cEp+5SNb7OEsXQ14HiaE7C8WyWAj0nHhP97faFYP8HQ=; h=From:To:Subject:Date:Message-Id:MIME-Version:x-icloud-hme; b=R6FolhBaKLBHM1enNnEqsuJJ3btS/AhcQH41TAg18+GyVnfLBT1XSPzBaJwXcaJGWpO+GFEJ8OBX34mxuh22JpAlilgMHjeIQ2x/e7nl1/+3NHUmcrCXUXgBwmQPcwauyKehbGE1CxqyKmdNtigcLQBwrpPjk/W+DTADqhypNkeSHU9kgqzT70u8zcsAp7g0zTa4ozydnBpbj0aSWRwO0lFvYHHjjAe0nfZcCFsjz39G4B/0KXfWQJo7Nzf0Q63ycnljPlc5Ss7troeebyOuKDZjrID+hLqIdPwpwCLaD2HGNhAMuPFKbDATbMWwqHPsc5yAjSvQZJsf8P8+zhCdsA== X-Client-IP: 46.189.47.18 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Mads Ynddal , qemu-arm@nongnu.org, Paolo Bonzini , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , Cameron Esfahani , Phil Dennis-Jordan , Peter Maydell , Alexander Graf , Shannon Zhao , Roman Bolshakov , Mohamed Mediouni Subject: [PATCH v2 9/9] target/arm: hvf: use LOG_UNIMP for CNTP_CVAL_EL0/SYSREG_CNTP_CTL_EL0 Date: Fri, 25 Jul 2025 10:55:45 +0200 Message-Id: <20250725085545.93619-10-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725085545.93619-1-mohamed@unpredictable.fr> References: <20250725085545.93619-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: blxyJ5mnHc4Vk5y2YgNK1RkpbSTs4ruQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3NSBTYWx0ZWRfXzBS+XVbc3L1J 3J8iZLdF7TTzpvmLc8eDS8bXpSI+H4k9JvZhVZvzYsXo49Ky30hcQj+yHvFFIXrIGPPCZ4hZX2O 2lo6bgGYonWGsd7mikLF0tLApHZggZrt2eL8fTA80EcO2xZ4BW+ABqrAxh6wB0rpkXV4M29US8h HZQvuMaBpCffwAHmw9/u7mIsGWbkKS3dehNjV1XLzaeyWMEnImx/a2UH0/vNAwLDG7DC/hWE9tq pnwJYn0VTzscJedRcmFFphA1pI2XTZFbZGrl6TCC7sgZdAlusGJxOXCRVNq42PiRk+Nl5scLY= X-Proofpoint-ORIG-GUID: blxyJ5mnHc4Vk5y2YgNK1RkpbSTs4ruQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 mlxlogscore=618 phishscore=0 spamscore=0 malwarescore=0 clxscore=1030 bulkscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250075 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.151; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753433871744116600 Content-Type: text/plain; charset="utf-8" Instead of considering reads there to be fatal, mark it as unimplemented. This is to allow experimentation on using configurations other than the App= le vGIC. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 5344e23db1..d01b9b4dcd 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -300,6 +300,7 @@ void hvf_arm_init_debug(void) /* EL2 registers */ #define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0) #define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0) +#define SYSREG_CNTP_CVAL_EL0 SYSREG(3, 3, 14, 2, 2) =20 #define WFX_IS_WFE (1 << 0) =20 @@ -1396,6 +1397,12 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t r= eg, uint64_t *val) case SYSREG_CNTHCTL_EL2: assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHC= TL_EL2, val)); return 0; + case SYSREG_CNTP_CTL_EL0: + qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CTL_EL0\n"); + return 0; + case SYSREG_CNTP_CVAL_EL0: + qemu_log_mask(LOG_UNIMP, "Unsupported read from CNTP_CVAL_EL0\n"); + return 0; case SYSREG_MDCCINT_EL1: assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCI= NT_EL1, val)); return 0; @@ -1712,6 +1719,9 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) */ qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CTL_EL0\n"); return 0; + case SYSREG_CNTP_CVAL_EL0: + qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CVAL_EL0\n"); + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ return 0; --=20 2.39.5 (Apple Git-154)