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Tsirkin" , Peter Maydell , Cameron Esfahani , Roman Bolshakov , Phil Dennis-Jordan , qemu-arm@nongnu.org, Ani Sinha , Mohamed Mediouni Subject: [PATCH 2/9] accel, hw/arm, include/system/hvf: plumbing changes for HVF vGIC Date: Fri, 25 Jul 2025 10:34:24 +0200 Message-Id: <20250725083431.91450-3-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250725083431.91450-1-mohamed@unpredictable.fr> References: <20250725083431.91450-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: wU-1KJ3QpzcZTUk77wI451A8OVDyF3Kd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA3MiBTYWx0ZWRfX52KyaitsMVTH X6RgOnq91bAdqy2yoEG1qA4gl66oK0HXzrbXB8v4CuRg332W3y/bterO9aXZUH4AlVhTlXi0GLs Bmxm4qY7ALxJwcnoOXwXgLl4fyGjWYyeTMMnc3dNLPXpNF3DXiwYNIZQs5s4KpAiwubeBkwbVBX c0KuACKzQyn/LEOZLs/XmfJuQZSvrZuxDkoykiIBxgSU6bIKwWKLFBxhQaJGL2Q//D4IFBAPUfN icG2dR4FT4hKK1w38QNQcdk083RMMAVxsxbe1zRoHMKfyCZMsMRRnrZ6lQqasFI6erv22Zro0= X-Proofpoint-ORIG-GUID: wU-1KJ3QpzcZTUk77wI451A8OVDyF3Kd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 mlxscore=0 bulkscore=0 clxscore=1030 suspectscore=0 mlxlogscore=999 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2507250072 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.74.33; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1753432573755116600 Content-Type: text/plain; charset="utf-8" Misc changes for HVF vGIC enablement. Signed-off-by: Mohamed Mediouni --- accel/hvf/hvf-all.c | 44 ++++++++++++++++++++++++++++++++++++++ accel/stubs/hvf-stub.c | 1 + hw/arm/virt.c | 17 +++++++++------ hw/intc/arm_gicv3_common.c | 3 +++ include/system/hvf.h | 3 +++ system/vl.c | 2 ++ 6 files changed, 64 insertions(+), 6 deletions(-) diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index e67a8105a6..d9408e259f 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -10,6 +10,8 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-common.h" #include "accel/accel-ops.h" #include "system/address-spaces.h" #include "system/memory.h" @@ -20,6 +22,7 @@ #include "trace.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; =20 struct mac_slot { int present; @@ -290,6 +293,41 @@ static int hvf_gdbstub_sstep_flags(AccelState *as) return SSTEP_ENABLE | SSTEP_NOIRQ; } =20 +static void hvf_set_kernel_irqchip(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ +#ifdef __aarch64__ + OnOffSplit mode; + if (!visit_type_OnOffSplit(v, name, &mode, errp)) { + return; + } + + switch (mode) { + case ON_OFF_SPLIT_ON: + hvf_kernel_irqchip =3D true; + break; + + case ON_OFF_SPLIT_OFF: + hvf_kernel_irqchip =3D false; + break; + + case ON_OFF_SPLIT_SPLIT: + error_setg(errp, "HVF: split irqchip is not supported on Arm."); + break; + + default: + /* + * The value was checked in visit_type_OnOffSplit() above. If + * we get here, then something is wrong in QEMU. + */ + abort(); + } +#else + error_setg(errp, "HVF: setting irqchip configuration not supported on = x86_64."); +#endif +} + static void hvf_accel_class_init(ObjectClass *oc, const void *data) { AccelClass *ac =3D ACCEL_CLASS(oc); @@ -297,6 +335,12 @@ static void hvf_accel_class_init(ObjectClass *oc, cons= t void *data) ac->init_machine =3D hvf_accel_init; ac->allowed =3D &hvf_allowed; ac->gdbstub_supported_sstep_flags =3D hvf_gdbstub_sstep_flags; + hvf_kernel_irqchip =3D true; + object_class_property_add(oc, "kernel-irqchip", "on|off|split", + NULL, hvf_set_kernel_irqchip, + NULL, NULL); + object_class_property_set_description(oc, "kernel-irqchip", + "Configure HVF irqchip"); } =20 static const TypeInfo hvf_accel_type =3D { diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c index 42eadc5ca9..6bd08759ba 100644 --- a/accel/stubs/hvf-stub.c +++ b/accel/stubs/hvf-stub.c @@ -10,3 +10,4 @@ #include "system/hvf.h" =20 bool hvf_allowed; +bool hvf_kernel_irqchip; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ef6be3660f..a26bde4c75 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -830,7 +830,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 @@ -853,8 +853,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count); =20 - if (!kvm_irqchip_in_kernel()) { - if (vms->tcg_its) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { + if (vms->its && vms->tcg_its) { object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem), &error_fatal); qdev_prop_set_bit(vms->gic, "has-lpi", true); @@ -864,7 +864,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) ARCH_GIC_MAINT_IRQ); } } else { - if (!kvm_irqchip_in_kernel()) { + if (!kvm_irqchip_in_kernel() && !hvf_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->virt); } @@ -2058,11 +2058,16 @@ static void finalize_gic_version(VirtMachineState *= vms) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; - } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { + } else if (hvf_enabled()) { + if (!hvf_irqchip_in_kernel()) { + gics_supported |=3D VIRT_GIC_VERSION_2_MASK; + } + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; + } else if (tcg_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { gics_supported |=3D VIRT_GIC_VERSION_3_MASK; - if (vms->virt) { + if (vms->virt && !hvf_enabled()) { /* GICv4 only makes sense if CPU has EL2 */ gics_supported |=3D VIRT_GIC_VERSION_4_MASK; } diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index e438d8c042..7c0eb5eb1e 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/hvf.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -662,6 +663,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (hvf_irqchip_in_kernel()) { + return "hvf-arm-gicv3"; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/include/system/hvf.h b/include/system/hvf.h index d3dcf088b3..dc8da85979 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -26,8 +26,11 @@ #ifdef CONFIG_HVF_IS_POSSIBLE extern bool hvf_allowed; #define hvf_enabled() (hvf_allowed) +extern bool hvf_kernel_irqchip; +#define hvf_irqchip_in_kernel() (hvf_kernel_irqchip) #else /* !CONFIG_HVF_IS_POSSIBLE */ #define hvf_enabled() 0 +#define hvf_irqchip_in_kernel() 0 #endif /* !CONFIG_HVF_IS_POSSIBLE */ =20 #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf") diff --git a/system/vl.c b/system/vl.c index 3b7057e6c6..1c072d15a4 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1773,6 +1773,8 @@ static void qemu_apply_legacy_machine_options(QDict *= qdict) false); object_register_sugar_prop(ACCEL_CLASS_NAME("whpx"), "kernel-irqch= ip", value, false); + object_register_sugar_prop(ACCEL_CLASS_NAME("hvf"), "kernel-irqchi= p", value, + false); qdict_del(qdict, "kernel-irqchip"); } =20 --=20 2.39.5 (Apple Git-154)