From nobody Sat Nov 15 12:30:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753407711128596.9712911169948; Thu, 24 Jul 2025 18:41:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uf7Q3-00032D-0z; Thu, 24 Jul 2025 21:40:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uf7Ov-0001bg-PI for qemu-devel@nongnu.org; Thu, 24 Jul 2025 21:39:09 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uf7Ot-0002qw-E8 for qemu-devel@nongnu.org; Thu, 24 Jul 2025 21:39:09 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxDGvq34JooJAxAQ--.34903S3; Fri, 25 Jul 2025 09:37:46 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxdOTk34Joz5wlAA--.62171S16; Fri, 25 Jul 2025 09:37:45 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v3 14/17] target/loongarch: Use mmu idx bitmap method when flush tlb Date: Fri, 25 Jul 2025 09:37:36 +0800 Message-Id: <20250725013739.994437-15-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250725013739.994437-1-maobibo@loongson.cn> References: <20250725013739.994437-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxdOTk34Joz5wlAA--.62171S16 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1753407712150116600 Content-Type: text/plain; charset="utf-8" With API tlb_flush_range_by_mmuidx(), bitmap method of mmu idx should be used rather than itself. And mmu idx comes from page table entry information rather current running mode. Also field KM in TLB misc records bitmap mask of TLB entry which is access in kernel mode. If set, MMU_KERNEL_IDX should be added to flush tlb. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 61cc19610e..d18b382e56 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -110,12 +110,12 @@ static void invalidate_tlb_entry(CPULoongArchState *e= nv, int index) target_ulong addr, mask, pagesize; uint8_t tlb_ps; LoongArchTLB *tlb =3D &env->tlb[index]; - - int mmu_idx =3D cpu_mmu_index(env_cpu(env), false); + int mmu_idx; uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); uint8_t tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); + uint16_t tlb_g, tlb_km; =20 if (!tlb_e) { return; @@ -125,13 +125,28 @@ static void invalidate_tlb_entry(CPULoongArchState *e= nv, int index) pagesize =3D MAKE_64BIT_MASK(tlb_ps, 1); mask =3D MAKE_64BIT_MASK(0, tlb_ps + 1); addr =3D __vaddr((tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask); + tlb_g =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G); + tlb_km =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, KM); + if (tlb_g) { + mmu_idx =3D BIT(MMU_KERNEL_IDX); + } else { + mmu_idx =3D BIT(MMU_USER_IDX); + } =20 if (tlb_v0) { + /* Even page is accessed in kernel mode */ + if (tlb_km & 0x1) { + mmu_idx |=3D BIT(MMU_KERNEL_IDX); + } tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, mmu_idx, TARGET_LONG_BITS); } =20 if (tlb_v1) { + /* Odd page is accessed in kernel mode */ + if (tlb_km & 0x2) { + mmu_idx |=3D BIT(MMU_KERNEL_IDX); + } tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize, mmu_idx, TARGET_LONG_BITS); } --=20 2.39.3