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Thu, 24 Jul 2025 01:51:40 -0700 (PDT) From: Anastasia Belova To: qemu-devel@nongnu.org, Peter Maydell Cc: Anastasia Belova , qemu-arm@nongnu.org, sdl.qemu@linuxtesting.org, Anastasia Belova Subject: [PATCH] target/arm: add bounding a->imm assertion Date: Thu, 24 Jul 2025 11:52:06 +0300 Message-Id: <20250724085206.22398-1-nabelova31@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=nabelova31@gmail.com; helo=mail-lf1-x12c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1753347144541116600 Content-Type: text/plain; charset="utf-8" Add an assertion similar to that in the do_shr_narrow(). This will make sure that functions from sshll_ops have correct arguments. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Anastasia Belova --- target/arm/tcg/translate-sve.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index d23be477b4..47ada85c92 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -6250,6 +6250,7 @@ static bool do_shll_tb(DisasContext *s, arg_rri_esz *= a, if (a->esz < 0 || a->esz > 2) { return false; } + assert(a->imm > 0 && a->imm <=3D (8 << a->esz)); if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd), --=20 2.47.0