From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753179521180511.7031550708417; Tue, 22 Jul 2025 03:18:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ueA4o-0003iZ-SZ; Tue, 22 Jul 2025 06:18:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ueA4k-0003ai-Le for qemu-devel@nongnu.org; Tue, 22 Jul 2025 06:18:23 -0400 Received: from air.basealt.ru ([193.43.8.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ueA4i-0000U5-9a for qemu-devel@nongnu.org; Tue, 22 Jul 2025 06:18:21 -0400 Received: from boringlust.malta.altlinux.ru (obninsk.basealt.ru [217.15.195.17]) (Authenticated sender: rastyoginds) by air.basealt.ru (Postfix) with ESMTPSA id 23C8E23394; Tue, 22 Jul 2025 13:18:18 +0300 (MSK) From: gerben@altlinux.org To: qemu-devel@nongnu.org, philmd@linaro.org Cc: sdl.qemu@linuxtesting.org Subject: [PATCH] target/mips: fix TLB huge page check to use 64-bit shift Date: Tue, 22 Jul 2025 13:17:53 +0300 Message-ID: <20250722101816.16528-1-gerben@altlinux.org> X-Mailer: git-send-email 2.42.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=193.43.8.18; envelope-from=gerben@altlinux.org; helo=air.basealt.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1753179523591116600 Content-Type: text/plain; charset="utf-8" From: Denis Rastyogin Use 1ULL << psn to ensure the shift is done in 64-bit arithmetic, avoiding overflow for large psn values. The 6-bit psn field allows values up to 63, so 64-bit shift is required for correctness. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Denis Rastyogin --- target/mips/tcg/system/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index eccaf3624c..b8b8747064 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -652,7 +652,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, return 0; } =20 - if ((entry & (1 << psn)) && hugepg) { + if ((entry & (1ULL << psn)) && hugepg) { *huge_page =3D true; *hgpg_directory_hit =3D true; entry =3D get_tlb_entry_layout(env, entry, leaf_mop, pf_ptew); --=20 2.42.2