From nobody Sat Nov 15 10:56:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1753118602; cv=none; d=zohomail.com; s=zohoarc; b=QCGLIDHnJxxn8R1MZdUxgdvKnjdo3pnsZth7l8OCRGJSFw9ElhDeQw2jWXViWApwYDEWS97zEfJbgAMZe4QRvj1lP8MSwfEOSViRwdA5JPh/Ptp/az9jJQdJeB0/SnKiR4MY/bOcx0GcwXbk5ZuYuJMB+sOgBj5q2/M3naItJr0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753118602; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=5cn8UaOfiASUSemvFLb4zcRqt0o7fllBY8o3zIV1R6Y=; b=LGxCkpkC2wGREuLa8IZThcnj/WTIsIK4eVu9/2FwMVYJA2FCWXWgRNIq/rHk1RTbNQ8o9cuU4azcVwLtB1xXEVzKMk4K+gjfZ9QWO5JFCxlx7/kyNDcGb6kl6GH4TCeRjn1H/7ajpBvefB8p1FixyaX0PVRMq+mSaBsyg2OwVP0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1753118602483701.8417386932953; Mon, 21 Jul 2025 10:23:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uduEB-0006gg-Db; Mon, 21 Jul 2025 13:23:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uduE5-0006IU-6e for qemu-devel@nongnu.org; Mon, 21 Jul 2025 13:22:57 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uduE1-0001K9-PG for qemu-devel@nongnu.org; Mon, 21 Jul 2025 13:22:56 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bm6ct0mjNz6D9CR; Tue, 22 Jul 2025 01:21:18 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id C5993140277; Tue, 22 Jul 2025 01:22:40 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.48.155.20) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 21 Jul 2025 19:22:40 +0200 To: , , , , CC: , Subject: [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record Date: Mon, 21 Jul 2025 18:22:23 +0100 Message-ID: <20250721172228.2118-3-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250721172228.2118-1-shiju.jose@huawei.com> References: <20250721172228.2118-1-shiju.jose@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.48.155.20] X-ClientProxiedBy: lhrpeml100006.china.huawei.com (7.191.160.224) To frapeml500007.china.huawei.com (7.182.85.172) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shiju.jose@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: From: shiju.jose--- via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1753118603904116600 Content-Type: text/plain; charset="utf-8" From: Shiju Jose CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event table has updated with following new fields. 1. Advanced Programmable Corrected Memory Error Threshold Event Flags 2. Corrected Memory Error Count at Event 3. Memory Event Sub-Type 4. Support for component ID in the PLDM format. Add updates for the above spec changes in the CXL general media event reporting and QMP command to inject general media event. Signed-off-by: Jonathan Cameron Signed-off-by: Shiju Jose --- hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++ hw/mem/cxl_type3_stubs.c | 6 ++++++ include/hw/cxl/cxl_events.h | 7 +++++-- qapi/cxl.json | 18 +++++++++++++++++- 4 files changed, 57 insertions(+), 3 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index aa6e5c1a08..a10e6bf518 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1646,6 +1646,11 @@ static const QemuUUID memory_module_uuid =3D { #define CXL_GMER_VALID_RANK BIT(1) #define CXL_GMER_VALID_DEVICE BIT(2) #define CXL_GMER_VALID_COMPONENT BIT(3) +#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4) + +#define CXL_GMER_EV_DESC_UCE BIT(0) +#define CXL_GMER_EV_DESC_THRESHOLD_EVENT BIT(1) +#define CXL_GMER_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2) =20 static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log) { @@ -1677,6 +1682,12 @@ void qmp_cxl_inject_general_media_event(const char *= path, CxlEventLog log, bool has_rank, uint8_t rank, bool has_device, uint32_t device, const char *component_id, + bool has_comp_id_pldm, + uint8_t is_comp_id_pldm, + bool has_cme_ev_flags, + uint8_t cme_ev_flags, + bool has_cme_count, uint32_t cme_c= ount, + uint8_t sub_type, Error **errp) { Object *obj =3D object_resolve_path(path, NULL); @@ -1737,10 +1748,28 @@ void qmp_cxl_inject_general_media_event(const char = *path, CxlEventLog log, strncpy((char *)gem.component_id, component_id, sizeof(gem.component_id) - 1); valid_flags |=3D CXL_GMER_VALID_COMPONENT; + if (has_comp_id_pldm && is_comp_id_pldm) { + valid_flags |=3D CXL_GMER_VALID_COMPONENT_ID_FORMAT; + } } =20 stw_le_p(&gem.validity_flags, valid_flags); =20 + if (has_cme_ev_flags) { + gem.cme_ev_flags =3D cme_ev_flags; + } else { + gem.cme_ev_flags =3D 0; + } + + if (has_cme_count) { + descriptor |=3D CXL_GMER_EV_DESC_THRESHOLD_EVENT; + st24_le_p(gem.cme_count, cme_count); + } else { + st24_le_p(gem.cme_count, 0); + } + + gem.sub_type =3D sub_type; + if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) { cxl_event_irq_assert(ct3d); } diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c index 91b1478114..28eb880b30 100644 --- a/hw/mem/cxl_type3_stubs.c +++ b/hw/mem/cxl_type3_stubs.c @@ -27,6 +27,12 @@ void qmp_cxl_inject_general_media_event(const char *path= , CxlEventLog log, bool has_rank, uint8_t rank, bool has_device, uint32_t device, const char *component_id, + bool has_comp_id_pldm, + uint8_t is_comp_id_pldm, + bool has_cme_ev_flags, + uint8_t cme_ev_flags, + bool has_cme_count, uint32_t cme_c= ount, + uint8_t sub_type, Error **errp) {} =20 void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h index 4d9cfdb621..352f9891bd 100644 --- a/include/hw/cxl/cxl_events.h +++ b/include/hw/cxl/cxl_events.h @@ -115,10 +115,10 @@ typedef struct CXLEventInterruptPolicy { =20 /* * General Media Event Record - * CXL r3.1 Section 8.2.9.2.1.1; Table 8-45 + * CXL r3.2 Section 8.2.10.2.1.1; Table 8-57 */ #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 -#define CXL_EVENT_GEN_MED_RES_SIZE 0x2e +#define CXL_EVENT_GEN_MED_RES_SIZE 0x29 typedef struct CXLEventGenMedia { CXLEventRecordHdr hdr; uint64_t phys_addr; @@ -130,6 +130,9 @@ typedef struct CXLEventGenMedia { uint8_t rank; uint8_t device[3]; uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; + uint8_t cme_ev_flags; + uint8_t cme_count[3]; + uint8_t sub_type; uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE]; } QEMU_PACKED CXLEventGenMedia; =20 diff --git a/qapi/cxl.json b/qapi/cxl.json index c1fe8319c8..e8060d16f7 100644 --- a/qapi/cxl.json +++ b/qapi/cxl.json @@ -82,6 +82,19 @@ # @component-id: Device specific component identifier for the event. # May describe a field replaceable sub-component of the device. # +# @is-comp-id-pldm: Flag represents device specific component identifier +# format is PLDM or not. +# +# @cme-ev-flags: Advanced programmable corrected memory error +# threshold event flags. +# See CXL r3.2 Table 8-57 General Media Event Record. +# +# @cme-count: Corrected memory error count at event. +# See CXL r3.2 Table 8-57 General Media Event Record. +# +# @sub-type: Memory event sub-type. +# See CXL r3.2 Table 8-57 General Media Event Record. +# # Since: 8.1 ## { 'command': 'cxl-inject-general-media-event', @@ -91,7 +104,10 @@ 'dpa': 'uint64', 'descriptor': 'uint8', 'type': 'uint8', 'transaction-type': 'uint8', '*channel': 'uint8', '*rank': 'uint8', - '*device': 'uint32', '*component-id': 'str' } } + '*device': 'uint32', '*component-id': 'str', + '*is-comp-id-pldm':'uint8', + '*cme-ev-flags':'uint8', '*cme-count':'uint32', + 'sub-type':'uint8' } } =20 ## # @cxl-inject-dram-event: --=20 2.43.0