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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114981; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Oxjl9Plxfxd+LhAa4iwUt8737MCf+RsKZaagKDT9fCg=; b=Rn5pImcLyx3bsZ0bkj3+mDsKj0qJ7OuDZYDxLCJvBxR5seqkGvIIXhF/kRr+3L9De+gEfW NV1ENn1hyDDXhqZ1iGjZyARAsnthHYRk53cj+M6VjzEMwUBr7dG/WSWUSORYZh7dvmL4lE fNYOGxS1/SN10xNca0GJ+/bIoDxDsnk= X-MC-Unique: 6nDJDb2UPqio7kv6Qbq2Eg-1 X-Mimecast-MFC-AGG-ID: 6nDJDb2UPqio7kv6Qbq2Eg_1753114978 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Michael Kowal , Glenn Miles , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/50] ppc/xive2: Reset Generation Flipped bit on END Cache Watch Date: Mon, 21 Jul 2025 18:21:50 +0200 Message-ID: <20250721162233.686837-8-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115032291116600 From: Michael Kowal When the END Event Queue wraps the END EQ Generation bit is flipped and the Generation Flipped bit is set to one. On a END cache Watch read operation, the Generation Flipped bit needs to be reset. While debugging an error modified END not valid error messages to include the method since all were the same. Signed-off-by: Michael Kowal Reviewed-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-8-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 3 ++- hw/intc/xive2.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 6b724fe762f6..ec247ce48ff7 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1325,10 +1325,11 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, = hwaddr offset, case VC_ENDC_WATCH3_DATA0: /* * Load DATA registers from cache with data requested by the - * SPEC register + * SPEC register. Clear gen_flipped bit in word 1. */ watch_engine =3D (offset - VC_ENDC_WATCH0_DATA0) >> 6; pnv_xive2_end_cache_load(xive, watch_engine); + xive->vc_regs[reg] &=3D ~(uint64_t)END2_W1_GEN_FLIPPED; val =3D xive->vc_regs[reg]; break; =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 01cf96a2af65..edf5d9eb94cb 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -374,8 +374,8 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t d= ata) qgen ^=3D 1; end->w1 =3D xive_set_field32(END2_W1_GENERATION, end->w1, qgen); =20 - /* TODO(PowerNV): reset GF bit on a cache watch operation */ - end->w1 =3D xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); + /* Set gen flipped to 1, it gets reset on a cache watch operation = */ + end->w1 =3D xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); } end->w1 =3D xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); } --=20 2.50.1