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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MerIZeYs/yxx3RFuXDtsAm61y3WcL99CR/oPk6azoZ4=; b=AtNCRArk/T8dS0+nWpJnMsZPr6VkCjvXsCNACwctEejyt5QHx87sFEd3ll+d9ZXgUXFALE hyJPwr6qlutujlUa+T+SeIgy5fgJa2UJaOK2WV1L/ysEnBGW2hKbo+xIF21rDMJm7Q6eG1 VyDt+qGSFhD2l1DWZtkdxLsyXpFHzRM= X-MC-Unique: jvx65dfHMFqZpJgYhg-YYA-1 X-Mimecast-MFC-AGG-ID: jvx65dfHMFqZpJgYhg-YYA_1753115098 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 50/50] ppc/xive2: Enable lower level contexts on VP push Date: Mon, 21 Jul 2025 18:22:33 +0200 Message-ID: <20250721162233.686837-51-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115827475116600 From: Nicholas Piggin When pushing a context, the lower-level context becomes valid if it had V=3D1, and so on. Iterate lower level contexts and send them pending interrupts if they become enabled. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-51-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index c3c6871e91b3..ee5fa2617849 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -995,6 +995,12 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, Xiv= eTCTX *tctx, bool v; bool do_restore; =20 + if (xive_ring_valid(tctx, ring)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Attempt to push VP to enable= d" + " ring 0x%02x\n", ring); + return; + } + /* First update the thead context */ switch (size) { case 1: @@ -1021,19 +1027,32 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, = XiveTCTX *tctx, /* Check the interrupt pending bits */ if (v) { Xive2Router *xrtr =3D XIVE2_ROUTER(xptr); - uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); - uint8_t nsr =3D sig_regs[TM_NSR]; + uint8_t cur_ring; =20 xive2_tctx_restore_nvp(xrtr, tctx, ring, nvp_blk, nvp_idx, do_restore); =20 - if (xive_nsr_indicates_group_exception(ring, nsr)) { - /* redistribute precluded active grp interrupt */ - g_assert(ring =3D=3D TM_QW2_HV_POOL); /* PHYS ring has the int= errupt */ - xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, n= sr)); + for (cur_ring =3D TM_QW1_OS; cur_ring <=3D ring; + cur_ring +=3D XIVE_TM_RING_SIZE) { + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, cur_ring); + uint8_t nsr =3D sig_regs[TM_NSR]; + + if (!xive_ring_valid(tctx, cur_ring)) { + continue; + } + + if (cur_ring =3D=3D TM_QW2_HV_POOL) { + if (xive_nsr_indicates_exception(cur_ring, nsr)) { + g_assert(xive_nsr_exception_ring(cur_ring, nsr) =3D=3D + TM_QW3_HV_P= HYS); + xive2_redistribute(xrtr, tctx, + xive_nsr_exception_ring(ring, nsr)); + } + xive2_tctx_process_pending(tctx, TM_QW3_HV_PHYS); + break; + } + xive2_tctx_process_pending(tctx, cur_ring); } - xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? - TM_QW3_HV_PHYS : ring); } } =20 @@ -1159,6 +1178,7 @@ static void xive2_tctx_process_pending(XiveTCTX *tctx= , uint8_t sig_ring) int rc; =20 g_assert(sig_ring =3D=3D TM_QW3_HV_PHYS || sig_ring =3D=3D TM_QW1_OS); + g_assert(sig_regs[TM_WORD2] & 0x80); g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR= ])); =20 /* --=20 2.50.1