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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115100; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w2Ytn8gCoH4cLDg3wEy7JfoNBafewUw23FBIc8zPuso=; b=Hbqys87ujBoYUmFBVLAaK8Su8LKXfHo+bndcfrU6GTgQiC8MACUp/ox0s1jnLPHsEuEEtY YYkxSLrcFieP+tbpLG6Z8E62FhgPKZGnlBzJnIsCxZREG7HsfHl4W9oo5OO1UCJ1VewPM4 Rdp13jGygZ52jTZ7M5YB9fL9M4uFv9o= X-MC-Unique: JJ9-8hoiMAuQyMlU0a8-Uw-1 X-Mimecast-MFC-AGG-ID: JJ9-8hoiMAuQyMlU0a8-Uw_1753115095 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 49/50] ppc/xive: Split need_resend into restore_nvp Date: Mon, 21 Jul 2025 18:22:32 +0200 Message-ID: <20250721162233.686837-50-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115307397116600 From: Nicholas Piggin This is needed by the next patch which will re-send on all lower rings when pushing a context. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-50-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 24 ++++++++++++------------ hw/intc/xive2.c | 28 ++++++++++++++++------------ 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8b7182fbb86c..e0ffcf89ebff 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -606,7 +606,7 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr= , XiveTCTX *tctx, return qw1w2; } =20 -static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, +static void xive_tctx_restore_nvp(XiveRouter *xrtr, XiveTCTX *tctx, uint8_t nvt_blk, uint32_t nvt_idx) { XiveNVT nvt; @@ -632,16 +632,6 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, Xi= veTCTX *tctx, uint8_t *regs =3D &tctx->regs[TM_QW1_OS]; regs[TM_IPB] |=3D ipb; } - - /* - * Always call xive_tctx_recompute_from_ipb(). Even if there were no - * escalation triggered, there could be a pending interrupt which - * was saved when the context was pulled and that we need to take - * into account by recalculating the PIPR (which is not - * saved/restored). - * It will also raise the External interrupt signal if needed. - */ - xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */ } =20 /* @@ -663,7 +653,17 @@ static void xive_tm_push_os_ctx(XivePresenter *xptr, X= iveTCTX *tctx, =20 /* Check the interrupt pending bits */ if (vo) { - xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); + xive_tctx_restore_nvp(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); + + /* + * Always call xive_tctx_recompute_from_ipb(). Even if there were = no + * escalation triggered, there could be a pending interrupt which + * was saved when the context was pulled and that we need to take + * into account by recalculating the PIPR (which is not + * saved/restored). + * It will also raise the External interrupt signal if needed. + */ + xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */ } } =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 1b005687961a..c3c6871e91b3 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -940,14 +940,14 @@ static uint8_t xive2_tctx_restore_ctx(Xive2Router *xr= tr, XiveTCTX *tctx, return cppr; } =20 -static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, +/* Restore TIMA VP context from NVP backlog */ +static void xive2_tctx_restore_nvp(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { - uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; - uint8_t ipb, nsr =3D sig_regs[TM_NSR]; + uint8_t ipb; Xive2Nvp nvp; =20 /* @@ -978,14 +978,6 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, = XiveTCTX *tctx, } /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |=3D ipb; - - if (xive_nsr_indicates_group_exception(ring, nsr)) { - /* redistribute precluded active grp interrupt */ - g_assert(ring =3D=3D TM_QW2_HV_POOL); /* PHYS ring has the grp int= errupt */ - xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); - } - xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? - TM_QW3_HV_PHYS : ring); } =20 /* @@ -1028,8 +1020,20 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, X= iveTCTX *tctx, =20 /* Check the interrupt pending bits */ if (v) { - xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, ring, + Xive2Router *xrtr =3D XIVE2_ROUTER(xptr); + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); + uint8_t nsr =3D sig_regs[TM_NSR]; + + xive2_tctx_restore_nvp(xrtr, tctx, ring, nvp_blk, nvp_idx, do_restore); + + if (xive_nsr_indicates_group_exception(ring, nsr)) { + /* redistribute precluded active grp interrupt */ + g_assert(ring =3D=3D TM_QW2_HV_POOL); /* PHYS ring has the int= errupt */ + xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, n= sr)); + } + xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? + TM_QW3_HV_PHYS : ring); } } =20 --=20 2.50.1