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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115097; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tQkr5sirkIYVlkew3vz7iKEHM5VQk0+durPjB467nNs=; b=dG7AFvkshVLFItu4uvD4fA5b5qt0VwYs+i6hDcrJNHxTiMXwV/NSsPh1bpn9BdV0XhsEUt SZT+vWNe9Pk45NVLqNeDfV7+wB4+FcK4Qfsju9zzK68MSX/OjvY+0wEhhwJUrTvjGNTy3R oyW2VlqLHyqs1A+htNg06/w7oycmuBQ= X-MC-Unique: 3PUIgMrDOca6ZYSgcRrjGA-1 X-Mimecast-MFC-AGG-ID: 3PUIgMrDOca6ZYSgcRrjGA_1753115093 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 48/50] ppc/xive2: Implement PHYS ring VP push TIMA op Date: Mon, 21 Jul 2025 18:22:31 +0200 Message-ID: <20250721162233.686837-49-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115647728116600 From: Nicholas Piggin Implement the phys (aka hard) VP push. PowerVM uses this operation. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-49-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2.h | 2 ++ hw/intc/xive.c | 2 ++ hw/intc/xive2.c | 11 +++++++++++ 3 files changed, 15 insertions(+) diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index 45266c2a8b9e..f4437e2c79a7 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -146,6 +146,8 @@ void xive2_tm_push_pool_ctx(XivePresenter *xptr, XiveTC= TX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive2_tm_push_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 725ba72b8f7a..8b7182fbb86c 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -747,6 +747,8 @@ static const XiveTmOp xive2_tm_operations[] =3D { xive_tm_set_pool_lgs, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true, xive2_tm_set_hv_cppr, NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, false, true, + xive2_tm_push_phys_ctx, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true, NULL, xive_tm_vt_poll }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, true, true, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index f9eaea119289..1b005687961a 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1005,6 +1005,11 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, X= iveTCTX *tctx, =20 /* First update the thead context */ switch (size) { + case 1: + tctx->regs[ring + TM_WORD2] =3D value & 0xff; + cam =3D xive2_tctx_hw_cam_line(xptr, tctx); + cam |=3D ((value & 0xc0) << 24); /* V and H bits */ + break; case 4: cam =3D value; w2 =3D cpu_to_be32(cam); @@ -1040,6 +1045,12 @@ void xive2_tm_push_pool_ctx(XivePresenter *xptr, Xiv= eTCTX *tctx, xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW2_HV_POOL); } =20 +void xive2_tm_push_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); +} + /* returns -1 if ring is invalid, but still populates block and index */ static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, uint8_t *nvp_blk, uint32_t *nvp_idx) --=20 2.50.1