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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114969; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Cn7VHl4DO/rNgK3+mkF6GERVNq6gKa9iNDHFLe9Dwzk=; b=L7FBnWY/hqCJi69p+IM0rKKQG6y8al+scJQHIZZwS1Yc6eDsIDvwNzcMupNDZe1IKUdatJ mY6tkK1mzrIh0hB/BoIgKD3CYfWFsg2A23LILA5SNEFR5vqz22PDikwQsvKvWS0xKOQtPv 9kGjB0BwkgU1E8waXjlMeeP8TmDn6XE= X-MC-Unique: ek7-4CstOvmFTvg1osrdtw-1 X-Mimecast-MFC-AGG-ID: ek7-4CstOvmFTvg1osrdtw_1753114966 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/50] ppc/xive2: Fix calculation of END queue sizes Date: Mon, 21 Jul 2025 18:21:46 +0200 Message-ID: <20250721162233.686837-4-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115048644116600 From: Glenn Miles The queue size of an Event Notification Descriptor (END) is determined by the 'cl' and QsZ fields of the END. If the cl field is 1, then the queue size (in bytes) will be the size of a cache line 128B * 2^QsZ and QsZ is limited to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ limited to 12. Fixes: f8a233dedf2 ("ppc/xive2: Introduce a XIVE2 core framework") Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-4-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2_regs.h | 1 + hw/intc/xive2.c | 25 +++++++++++++++++++------ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index b11395c56350..3c28de8a304d 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -87,6 +87,7 @@ typedef struct Xive2End { #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31) uint32_t w3; #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24) +#define END2_W3_CL PPC_BIT32(27) #define END2_W3_QSIZE PPC_BITMASK32(28, 31) uint32_t w4; #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index a08cf906d0e6..cb75ca879853 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -188,12 +188,27 @@ void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t= lisn, GString *buf) (uint32_t) xive_get_field64(EAS2_END_DATA, eas-= >w)); } =20 +#define XIVE2_QSIZE_CHUNK_CL 128 +#define XIVE2_QSIZE_CHUNK_4k 4096 +/* Calculate max number of queue entries for an END */ +static uint32_t xive2_end_get_qentries(Xive2End *end) +{ + uint32_t w3 =3D end->w3; + uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, w3); + if (xive_get_field32(END2_W3_CL, w3)) { + g_assert(qsize <=3D 4); + return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); + } else { + g_assert(qsize <=3D 12); + return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); + } +} + void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString= *buf) { uint64_t qaddr_base =3D xive2_end_qaddr(end); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); int i; =20 /* @@ -223,8 +238,7 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t e= nd_idx, GString *buf) uint64_t qaddr_base =3D xive2_end_qaddr(end); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); =20 uint32_t nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6); uint32_t nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6); @@ -341,13 +355,12 @@ void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint3= 2_t nvgc_idx, GString *buf) static void xive2_end_enqueue(Xive2End *end, uint32_t data) { uint64_t qaddr_base =3D xive2_end_qaddr(end); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); =20 uint64_t qaddr =3D qaddr_base + (qindex << 2); uint32_t qdata =3D cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); =20 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdat= a), MEMTXATTRS_UNSPECIFIED)) { --=20 2.50.1