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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114964; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IKlPWOpl+9mEBH6KpFIBAbr5kvTW7uY4p2qdsndGhfo=; b=F/HnZY6YXZtfj5VJKBN9G/2peuYVPPx5NI0K7PdKoVopc110XmOpgneu6jhJ1B3ks3Xx2r 7IXYiRkvUDLu0no1nbaqZwWzC2ccZBj1puvExe2wEXEmHhDs3poRVGQNVs9lm74C/xd9B4 UrmayPPh/Ok9MOzDNlc8n7ME6G/xwg0= X-MC-Unique: OCOxaZ7eMNSF81Jnw4tCNQ-1 X-Mimecast-MFC-AGG-ID: OCOxaZ7eMNSF81Jnw4tCNQ_1753114960 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/50] ppc/xive: Fix xive trace event output Date: Mon, 21 Jul 2025 18:21:44 +0200 Message-ID: <20250721162233.686837-2-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753114999620116600 From: Nicholas Piggin Typo, IBP should be IPB. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-2-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/trace-events | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 334aa6a97bad..9ed2616e58fe 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -274,9 +274,9 @@ kvm_xive_cpu_connect(uint32_t id) "connect CPU%d to KVM= device" kvm_xive_source_reset(uint32_t srcno) "IRQ 0x%x" =20 # xive.c -xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, = uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IBP=3D0x%02x PIPR=3D0x%= 02x CPPR=3D0x%02x NSR=3D0x%02x ACK" -xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, = uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IBP=3D0x%02x PIPR=3D0x%= 02x CPPR=3D0x%02x NSR=3D0x%02x raise !" -xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr= , uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IBP=3D0x%02x PIPR=3D0= x%02x new CPPR=3D0x%02x NSR=3D0x%02x" +xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, = uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IPB=3D0x%02x PIPR=3D0x%= 02x CPPR=3D0x%02x NSR=3D0x%02x ACK" +xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, = uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IPB=3D0x%02x PIPR=3D0x%= 02x CPPR=3D0x%02x NSR=3D0x%02x raise !" +xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr= , uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IPB=3D0x%02x PIPR=3D0= x%02x new CPPR=3D0x%02x NSR=3D0x%02x" xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"= PRIx64" IRQ 0x%x val=3D0x%"PRIx64 xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%= "PRIx64" IRQ 0x%x val=3D0x%"PRIx64 xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_dat= a) "END 0x%02x/0x%04x -> enqueue 0x%08x" --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114966; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5VCJItz73tYeT0KX7Z2+/ORjgJwylt6FqVpui1hOIZY=; b=Tq3sszpOJSzOSq7ICf/wt+zLgRQzgaC5E2kZkR5kJHw5xBuLD8Qgv5gOmoCknsSTp9+K6Y XiXxbcc1gA0f59uABSjYXLhx4jyCdPQ8Z1eMRUAMsJx9w408kH1ZoDMkH1dDVYiiGNj/nW L1bhtBY5p1uKFPcu3XEhTK5DCYWUieI= X-MC-Unique: meKwutT7ORyP2dzbSEmQYA-1 X-Mimecast-MFC-AGG-ID: meKwutT7ORyP2dzbSEmQYA_1753114963 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/50] ppc/xive: Report access size in XIVE TM operation error logs Date: Mon, 21 Jul 2025 18:21:45 +0200 Message-ID: <20250721162233.686837-3-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115052317116600 From: Nicholas Piggin Report access size in XIVE TM operation error logs. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-3-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 27b473e4d762..120376fb6b6d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -326,7 +326,7 @@ static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr of= fset, uint64_t value, */ if (size < 4 || !mask || ring_offset =3D=3D TM_QW0_USER) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA= @%" - HWADDR_PRIx"\n", offset); + HWADDR_PRIx" size %d\n", offset, size); return; } =20 @@ -357,7 +357,7 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr= offset, unsigned size) */ if (size < 4 || !mask || ring_offset =3D=3D TM_QW0_USER) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA = @%" - HWADDR_PRIx"\n", offset); + HWADDR_PRIx" size %d\n", offset, size); return -1; } =20 @@ -688,7 +688,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *= tctx, hwaddr offset, xto =3D xive_tm_find_op(tctx->xptr, offset, size, true); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " - "@%"HWADDR_PRIx"\n", offset); + "@%"HWADDR_PRIx" size %d\n", offset, size); } else { xto->write_handler(xptr, tctx, offset, value, size); } @@ -727,7 +727,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCT= X *tctx, hwaddr offset, xto =3D xive_tm_find_op(tctx->xptr, offset, size, false); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to T= IMA" - "@%"HWADDR_PRIx"\n", offset); + "@%"HWADDR_PRIx" size %d\n", offset, size); return -1; } ret =3D xto->read_handler(xptr, tctx, offset, size); --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=Cn7VHl4DO/rNgK3+mkF6GERVNq6gKa9iNDHFLe9Dwzk=; b=L7FBnWY/hqCJi69p+IM0rKKQG6y8al+scJQHIZZwS1Yc6eDsIDvwNzcMupNDZe1IKUdatJ mY6tkK1mzrIh0hB/BoIgKD3CYfWFsg2A23LILA5SNEFR5vqz22PDikwQsvKvWS0xKOQtPv 9kGjB0BwkgU1E8waXjlMeeP8TmDn6XE= X-MC-Unique: ek7-4CstOvmFTvg1osrdtw-1 X-Mimecast-MFC-AGG-ID: ek7-4CstOvmFTvg1osrdtw_1753114966 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/50] ppc/xive2: Fix calculation of END queue sizes Date: Mon, 21 Jul 2025 18:21:46 +0200 Message-ID: <20250721162233.686837-4-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115048644116600 From: Glenn Miles The queue size of an Event Notification Descriptor (END) is determined by the 'cl' and QsZ fields of the END. If the cl field is 1, then the queue size (in bytes) will be the size of a cache line 128B * 2^QsZ and QsZ is limited to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ limited to 12. Fixes: f8a233dedf2 ("ppc/xive2: Introduce a XIVE2 core framework") Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-4-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2_regs.h | 1 + hw/intc/xive2.c | 25 +++++++++++++++++++------ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index b11395c56350..3c28de8a304d 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -87,6 +87,7 @@ typedef struct Xive2End { #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31) uint32_t w3; #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24) +#define END2_W3_CL PPC_BIT32(27) #define END2_W3_QSIZE PPC_BITMASK32(28, 31) uint32_t w4; #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index a08cf906d0e6..cb75ca879853 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -188,12 +188,27 @@ void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t= lisn, GString *buf) (uint32_t) xive_get_field64(EAS2_END_DATA, eas-= >w)); } =20 +#define XIVE2_QSIZE_CHUNK_CL 128 +#define XIVE2_QSIZE_CHUNK_4k 4096 +/* Calculate max number of queue entries for an END */ +static uint32_t xive2_end_get_qentries(Xive2End *end) +{ + uint32_t w3 =3D end->w3; + uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, w3); + if (xive_get_field32(END2_W3_CL, w3)) { + g_assert(qsize <=3D 4); + return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); + } else { + g_assert(qsize <=3D 12); + return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); + } +} + void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString= *buf) { uint64_t qaddr_base =3D xive2_end_qaddr(end); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); int i; =20 /* @@ -223,8 +238,7 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t e= nd_idx, GString *buf) uint64_t qaddr_base =3D xive2_end_qaddr(end); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); =20 uint32_t nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6); uint32_t nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6); @@ -341,13 +355,12 @@ void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint3= 2_t nvgc_idx, GString *buf) static void xive2_end_enqueue(Xive2End *end, uint32_t data) { uint64_t qaddr_base =3D xive2_end_qaddr(end); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); =20 uint64_t qaddr =3D qaddr_base + (qindex << 2); uint32_t qdata =3D cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); =20 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdat= a), MEMTXATTRS_UNSPECIFIED)) { --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115108; cv=none; d=zohomail.com; s=zohoarc; b=brjHrxZhos5zjtdHy3pYyN2F8IbvYJKgAQrSlsL2V++aJs3g0FFkcjOtFWcpK9unGNI6k6LRQLhzyxAtPmN1UOdJCS684oi2iUu8dmKytVQ6l7PmFOoADagJ3zr2xYyazzY7H3m48nlPOV6ikM8PSzoJ6jOWOLkbDbN2r9Jshi8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753115108; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 21 Jul 2025 16:22:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114974; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LFIA52aLnJLo4iSfDSS+0eck6FoSAwP11FgR2rElbiU=; b=X1NzwxOyV6TGjsDsaekBwbHel+WKdoDqhh71p/19fvzgt5LianNQq2Wr8GHefvZIZuPn/I 4860YjwWM+mCM10WP6LVt9JA/kyPfhzYw1z52U0q0JeiGs6SKtbanb9C7Jh4Lvbwp5RIy+ pyYZY+EGPVwY+z5Hwrypc0PQXUCC+Ko= X-MC-Unique: 4rRK5E_vPLWASb9WVJNFIA-1 X-Mimecast-MFC-AGG-ID: 4rRK5E_vPLWASb9WVJNFIA_1753114969 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Michael Kowal , Glenn Miles , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 04/50] ppc/xive2: Remote VSDs need to match on forwarding address Date: Mon, 21 Jul 2025 18:21:47 +0200 Message-ID: <20250721162233.686837-5-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115108972116600 From: Michael Kowal In a multi chip environment there will be remote/forwarded VSDs. The check to find a matching INT controller (XIVE) of the remote block number was checking the INTs chip number. Block numbers are not tied to a chip number. The matching remote INT is the one that matches the forwarded VSD address with VSD types associated MMIO BAR. Signed-off-by: Michael Kowal Reviewed-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-5-npiggin@gm= ail.com [ clg: Fixed log format in pnv_xive2_get_remote() ] Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index ec8b0c68f1a4..6b724fe762f6 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -101,12 +101,10 @@ static uint32_t pnv_xive2_block_id(PnvXive2 *xive) } =20 /* - * Remote access to controllers. HW uses MMIOs. For now, a simple scan - * of the chips is good enough. - * - * TODO: Block scope support + * Remote access to INT controllers. HW uses MMIOs(?). For now, a simple + * scan of all the chips INT controller is good enough. */ -static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) +static PnvXive2 *pnv_xive2_get_remote(uint32_t vsd_type, hwaddr fwd_addr) { PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); int i; @@ -115,10 +113,23 @@ static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) Pnv10Chip *chip10 =3D PNV10_CHIP(pnv->chips[i]); PnvXive2 *xive =3D &chip10->xive; =20 - if (pnv_xive2_block_id(xive) =3D=3D blk) { + /* + * Is this the XIVE matching the forwarded VSD address is for this + * VSD type + */ + if ((vsd_type =3D=3D VST_ESB && fwd_addr =3D=3D xive->esb_base) = || + (vsd_type =3D=3D VST_END && fwd_addr =3D=3D xive->end_base) = || + ((vsd_type =3D=3D VST_NVP || + vsd_type =3D=3D VST_NVG) && fwd_addr =3D=3D xive->nvpg_base)= || + (vsd_type =3D=3D VST_NVC && fwd_addr =3D=3D xive->nvc_base))= { return xive; } } + + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: >>>>> %s vsd_type %u fwd_addr 0x%"HWADDR_PRIx + " NOT FOUND\n", + __func__, vsd_type, fwd_addr); return NULL; } =20 @@ -251,8 +262,7 @@ static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint= 32_t type, uint8_t blk, =20 /* Remote VST access */ if (GETFIELD(VSD_MODE, vsd) =3D=3D VSD_MODE_FORWARD) { - xive =3D pnv_xive2_get_remote(blk); - + xive =3D pnv_xive2_get_remote(type, (vsd & VSD_ADDRESS_MASK)); return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115071; cv=none; d=zohomail.com; s=zohoarc; b=RsDyLPAivlE3Xnov2s2Cvg/aEp0aIc6KAINT4B9csWWih4j4Gom3MDHm+WAFyfo/DzfwEoy1gN0QeP6IsvwSX9GHXc10CUdZEQtXiwG3ZCp5J1nYKiGSmZHMndMEVUXSU5K97ufU3agvVhhZBtkuUlrD7FiKpvtp1a7jjoIwSRw= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:22:51 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id BB49C1956050; Mon, 21 Jul 2025 16:22:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114974; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nibxoopfG+ra1bTOd7GpQ9uJEvgBpG4MlJh1Ogsz96o=; b=F/hY5Bcwja2awFCsh9M7BywUJ9hOAWuMoSxwvke45ENG2AwCRHWu6zVBnKBuo3uCnvSsNZ C+yKB7IfYt0QcJgKcHd7p/MjEtd07xU3R1ApQgd6WjLtnswmVk+8szHyhJtMiXpgje7LlK 0AbTIiDjzd8/N+IrpyKhddJb5Xdt6o0= X-MC-Unique: XSj0CjW8NcGyIcwBMHCkzQ-1 X-Mimecast-MFC-AGG-ID: XSj0CjW8NcGyIcwBMHCkzQ_1753114972 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/50] ppc/xive2: fix context push calculation of IPB priority Date: Mon, 21 Jul 2025 18:21:48 +0200 Message-ID: <20250721162233.686837-6-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115072618116600 From: Nicholas Piggin Pushing a context and loading IPB from NVP is defined to merge ('or') that IPB into the TIMA IPB register. PIPR should therefore be calculated based on the final IPB value, not just the NVP value. Fixes: 9d2b6058c5b ("ppc/xive2: Add grouping level to notification") Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-6-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index cb75ca879853..01cf96a2af65 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -835,8 +835,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, X= iveTCTX *tctx, nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); } + /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |=3D ipb; - backlog_prio =3D xive_ipb_to_pipr(ipb); + backlog_prio =3D xive_ipb_to_pipr(regs[TM_IPB]); backlog_level =3D 0; =20 first_group =3D xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=G+vpGBIdAyFmIOhIassfZzr92Quav/tsXT1F0h3i0Ho=; b=Sdg8O8GcfIeEZR+jBPROMyYPs/GD8uznkfxwbCZBEa6EcTzx5EJ/i8eNvu1Coo1gZRORb0 LfQWE316FG9TzEQUSakLSnQon8I+4xmiheK+ZOBl5t803PZenlbE8Ma8gnJx0k9lWWdLsL 4EgvCjJG0KilCpjpLEq292Y9PHUUCUc= X-MC-Unique: V34ETTSfMfuFxk_jYGTe2Q-1 X-Mimecast-MFC-AGG-ID: V34ETTSfMfuFxk_jYGTe2Q_1753114975 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/50] ppc/xive: Fix PHYS NSR ring matching Date: Mon, 21 Jul 2025 18:21:49 +0200 Message-ID: <20250721162233.686837-7-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115046496116600 From: Nicholas Piggin Test that the NSR exception bit field is equal to the pool ring value, rather than any common bits set, which is more correct (although there is no practical bug because the LSI NSR type is not implemented and POOL/PHYS NSR are encoded with exclusive bits). Fixes: 4c3ccac636 ("pnv/xive: Add special handling for pool targets") Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-7-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 120376fb6b6d..bc829bebe9d0 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -54,7 +54,8 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t = ring) uint8_t *alt_regs; =20 /* POOL interrupt uses IPB in QW2, POOL ring */ - if ((ring =3D=3D TM_QW3_HV_PHYS) && (nsr & (TM_QW3_NSR_HE_POOL << = 6))) { + if ((ring =3D=3D TM_QW3_HV_PHYS) && + ((nsr & TM_QW3_NSR_HE) =3D=3D (TM_QW3_NSR_HE_POOL << 6))) { alt_ring =3D TM_QW2_HV_POOL; } else { alt_ring =3D ring; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114981; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Oxjl9Plxfxd+LhAa4iwUt8737MCf+RsKZaagKDT9fCg=; b=Rn5pImcLyx3bsZ0bkj3+mDsKj0qJ7OuDZYDxLCJvBxR5seqkGvIIXhF/kRr+3L9De+gEfW NV1ENn1hyDDXhqZ1iGjZyARAsnthHYRk53cj+M6VjzEMwUBr7dG/WSWUSORYZh7dvmL4lE fNYOGxS1/SN10xNca0GJ+/bIoDxDsnk= X-MC-Unique: 6nDJDb2UPqio7kv6Qbq2Eg-1 X-Mimecast-MFC-AGG-ID: 6nDJDb2UPqio7kv6Qbq2Eg_1753114978 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Michael Kowal , Glenn Miles , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/50] ppc/xive2: Reset Generation Flipped bit on END Cache Watch Date: Mon, 21 Jul 2025 18:21:50 +0200 Message-ID: <20250721162233.686837-8-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115032291116600 From: Michael Kowal When the END Event Queue wraps the END EQ Generation bit is flipped and the Generation Flipped bit is set to one. On a END cache Watch read operation, the Generation Flipped bit needs to be reset. While debugging an error modified END not valid error messages to include the method since all were the same. Signed-off-by: Michael Kowal Reviewed-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-8-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 3 ++- hw/intc/xive2.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 6b724fe762f6..ec247ce48ff7 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1325,10 +1325,11 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, = hwaddr offset, case VC_ENDC_WATCH3_DATA0: /* * Load DATA registers from cache with data requested by the - * SPEC register + * SPEC register. Clear gen_flipped bit in word 1. */ watch_engine =3D (offset - VC_ENDC_WATCH0_DATA0) >> 6; pnv_xive2_end_cache_load(xive, watch_engine); + xive->vc_regs[reg] &=3D ~(uint64_t)END2_W1_GEN_FLIPPED; val =3D xive->vc_regs[reg]; break; =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 01cf96a2af65..edf5d9eb94cb 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -374,8 +374,8 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t d= ata) qgen ^=3D 1; end->w1 =3D xive_set_field32(END2_W1_GENERATION, end->w1, qgen); =20 - /* TODO(PowerNV): reset GF bit on a cache watch operation */ - end->w1 =3D xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); + /* Set gen flipped to 1, it gets reset on a cache watch operation = */ + end->w1 =3D xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); } end->w1 =3D xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); } --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PeaxLgyiIYKj0kt5yg0H9AiCj069c/p8og5RfRh37nA=; b=UzqVyQdiLYrZycS71pQuyKhxlbTjK+yrJhaJYRZPpq2y2FLuEOvUmFUDqjBipaCcS3RuQt iCcdkFPJQ9dMWVm6T3UodFZf3PgXkE1SsN2ygUC7H66hp6kJNUbGGXKa8XIpCtN2loVNUU eLqeKFudaNFQmjPeU+yPJc3pZuYHQ8M= X-MC-Unique: DI98qf95OJ-sz9uemG2XAw-1 X-Mimecast-MFC-AGG-ID: DI98qf95OJ-sz9uemG2XAw_1753114981 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/50] ppc/xive2: Use fair irq target search algorithm Date: Mon, 21 Jul 2025 18:21:51 +0200 Message-ID: <20250721162233.686837-9-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115108989116600 From: Glenn Miles The current xive algorithm for finding a matching group vCPU target always uses the first vCPU found. And, since it always starts the search with thread 0 of a core, thread 0 is almost always used to handle group interrupts. This can lead to additional interrupt latency and poor performance for interrupt intensive work loads. Changing this to use a simple round-robin algorithm for deciding which thread number to use when starting a search, which leads to a more distributed use of threads for handling group interrupts. [npiggin: Also round-robin among threads, not just cores] Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-9-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index ec247ce48ff7..25dc8a372d2f 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -643,13 +643,18 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, u= int8_t format, int i, j; bool gen1_tima_os =3D xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; + static int next_start_core; + static int next_start_thread; + int start_core =3D next_start_core; + int start_thread =3D next_start_thread; =20 for (i =3D 0; i < chip->nr_cores; i++) { - PnvCore *pc =3D chip->cores[i]; + PnvCore *pc =3D chip->cores[(i + start_core) % chip->nr_cores]; CPUCore *cc =3D CPU_CORE(pc); =20 for (j =3D 0; j < cc->nr_threads; j++) { - PowerPCCPU *cpu =3D pc->threads[j]; + /* Start search for match with different thread each call */ + PowerPCCPU *cpu =3D pc->threads[(j + start_thread) % cc->nr_th= reads]; XiveTCTX *tctx; int ring; =20 @@ -694,6 +699,15 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, ui= nt8_t format, if (!match->tctx) { match->ring =3D ring; match->tctx =3D tctx; + + next_start_thread =3D j + start_thread + 1; + if (next_start_thread >=3D cc->nr_threads) { + next_start_thread =3D 0; + next_start_core =3D i + start_core + 1; + if (next_start_core >=3D chip->nr_cores) { + next_start_core =3D 0; + } + } } count++; } --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=5HMbXVPwEREx4z0xNHGKAjtCskhCG3OzH+66bN8KWJ0=; b=DsT3WMG9rKBYq3TwUM8gAkanELNzVOiDlw9y3U4Tc+UX+hv+YZpmv2YEHcBFhffn6bOhrL mEg/O9kWszIrA/PeLmgWc6uxdZO8WT/tpaK1nkuceReWKFLuV7csPvQTVxQ1nUWWDcoffN VUS9fOsp0VNlt1HgwbOZbyzeGoEhEpE= X-MC-Unique: J1ls4oRrPLCueQf2Kr5OMw-1 X-Mimecast-MFC-AGG-ID: J1ls4oRrPLCueQf2Kr5OMw_1753114983 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 09/50] ppc/xive2: Fix irq preempted by lower priority group irq Date: Mon, 21 Jul 2025 18:21:52 +0200 Message-ID: <20250721162233.686837-10-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115742465116600 From: Glenn Miles A problem was seen where uart interrupts would be lost resulting in the console hanging. Traces showed that a lower priority interrupt was preempting a higher priority interrupt, which would result in the higher priority interrupt never being handled. The new interrupt's priority was being compared against the CPPR (Current Processor Priority Register) instead of the PIPR (Post Interrupt Priority Register), as was required by the XIVE spec. This allowed for a window between raising an interrupt and ACK'ing the interrupt where a lower priority interrupt could slip in. Fixes: 26c55b99418 ("ppc/xive2: Process group backlog when updating the CPP= R") Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-10-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index edf5d9eb94cb..36e842f041e5 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1283,7 +1283,7 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring,= uint8_t priority) * priority to know if the thread can take the interrupt now or if * it is precluded. */ - if (priority < alt_regs[TM_CPPR]) { + if (priority < alt_regs[TM_PIPR]) { return false; } return true; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=zNNGby1h709b31T6L7CLVx3l9zQwZoveLZOvkgOivvU=; b=DqoecJtiMmRpLLnxlcNO14Lg9dhKa7GqRFHcT65GjxGVBLNy1LfmTvytCnpRH55Y3LydqB y9wXkJwjzkCNk8KaqgCyGSsopH48IK3aEbj+gEUcESu91FA0c/fZ2FLqIOezPrR6WYaQVB HRP2MMmVpGrkx5UoB9Cb2XGvOzp16/U= X-MC-Unique: DfnAs3a7NT-I7MQ8pzxs6w-1 X-Mimecast-MFC-AGG-ID: DfnAs3a7NT-I7MQ8pzxs6w_1753114986 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 10/50] ppc/xive2: Fix treatment of PIPR in CPPR update Date: Mon, 21 Jul 2025 18:21:53 +0200 Message-ID: <20250721162233.686837-11-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115090703116600 From: Glenn Miles According to the XIVE spec, updating the CPPR should also update the PIPR. The final value of the PIPR depends on other factors, but it should never be set to a value that is above the CPPR. Also added support for redistributing an active group interrupt when it is precluded as a result of changing the CPPR value. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-11-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 36e842f041e5..c23933f8f550 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -995,7 +995,9 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) } } } - regs[TM_PIPR] =3D pipr_min; + + /* PIPR should not be set to a value greater than CPPR */ + regs[TM_PIPR] =3D (pipr_min > cppr) ? cppr : pipr_min; =20 rc =3D xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); if (rc) { --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=huq/UJ1M6qqDhg8wbK2KFQkzbvprHoeS0OWsYnauCdQ=; b=LMkvuqHvMiOhlPMEyqPhkeBwJJQuC8XOGHjVl7NtzJIeQV1BIg+bRAPbUwS7YMX1mJ9Mgm oLAdITckk86VNvzwLw/42XzlSiPG2XNfjtphOlhEXAhHO3WX6cz1L8fVzsHKRBJnb6Xw9j Aw1s1CZUiabodQWtmDfNtq4/yDWyoxg= X-MC-Unique: iOqjA_5xMRKyFJzVmMRYZg-1 X-Mimecast-MFC-AGG-ID: iOqjA_5xMRKyFJzVmMRYZg_1753114989 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 11/50] ppc/xive2: Do not present group interrupt on OS-push if precluded by CPPR Date: Mon, 21 Jul 2025 18:21:54 +0200 Message-ID: <20250721162233.686837-12-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116261272116600 From: Nicholas Piggin Group interrupts should not be taken from the backlog and presented if they are precluded by CPPR. Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS con= text") Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-12-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index c23933f8f550..181d1ae5f940 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -845,7 +845,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, X= iveTCTX *tctx, group_prio =3D xive2_presenter_backlog_scan(xptr, nvp_blk, nvp_idx, first_group, &group_leve= l); regs[TM_LSMFB] =3D group_prio; - if (regs[TM_LGS] && group_prio < backlog_prio) { + if (regs[TM_LGS] && group_prio < backlog_prio && + group_prio < regs[TM_CPPR]) { + /* VP can take a group interrupt */ xive2_presenter_backlog_decr(xptr, nvp_blk, nvp_idx, group_prio, group_level); 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753114996; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=O6MQGkz4Wgu6/6GQyFnRG9Xy+yrPEm89A5MiJBkiVz4=; b=cXMHwIcjPrKZQ6sHrgqlFNR+ZfcRhMGHGdWtFOqDVLd2Sbv2ZVch/VU0M8Ly5fLp0bh6Lk 0TGJe5RAdUtXZK7yavA9QS25QJ070bgLLt+nrdlaKcvSBvQq4uOrEQGiPLmXafU7BE4bLI GCWfCx96NlEXESK1lXOH86Wg3M7a/8Y= X-MC-Unique: 72NvYdWjM12kdZ4wfhbMHA-1 X-Mimecast-MFC-AGG-ID: 72NvYdWjM12kdZ4wfhbMHA_1753114992 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 12/50] ppc/xive2: Set CPPR delivery should account for group priority Date: Mon, 21 Jul 2025 18:21:55 +0200 Message-ID: <20250721162233.686837-13-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115449397116600 From: Nicholas Piggin The group interrupt delivery flow selects the group backlog scan if LSMFB < IPB, but that scan may find an interrupt with a priority >=3D IPB. In that case, the VP-direct interrupt should be chosen. This extends to selecting the lowest prio between POOL and PHYS rings. Implement this just by re-starting the selection logic if the backlog irq was not found or priority did not match LSMFB (LSMFB is updated so next time around it would see the right value and not loop infinitely). Signed-off-by: Nicholas Piggin Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-13-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 181d1ae5f940..cca121b5f13c 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -939,7 +939,7 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) { uint8_t *regs =3D &tctx->regs[ring]; Xive2Router *xrtr =3D XIVE2_ROUTER(tctx->xptr); - uint8_t old_cppr, backlog_prio, first_group, group_level =3D 0; + uint8_t old_cppr, backlog_prio, first_group, group_level; uint8_t pipr_min, lsmfb_min, ring_min; bool group_enabled; uint32_t nvp_blk, nvp_idx; @@ -961,10 +961,12 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8= _t ring, uint8_t cppr) * Recompute the PIPR based on local pending interrupts. It will * be adjusted below if needed in case of pending group interrupts. */ +again: pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]); group_enabled =3D !!regs[TM_LGS]; - lsmfb_min =3D (group_enabled) ? regs[TM_LSMFB] : 0xff; + lsmfb_min =3D group_enabled ? regs[TM_LSMFB] : 0xff; ring_min =3D ring; + group_level =3D 0; =20 /* PHYS updates also depend on POOL values */ if (ring =3D=3D TM_QW3_HV_PHYS) { @@ -998,9 +1000,6 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_= t ring, uint8_t cppr) } } =20 - /* PIPR should not be set to a value greater than CPPR */ - regs[TM_PIPR] =3D (pipr_min > cppr) ? cppr : pipr_min; - rc =3D xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); if (rc) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\= n"); @@ -1019,7 +1018,7 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8= _t ring, uint8_t cppr) =20 if (group_enabled && lsmfb_min < cppr && - lsmfb_min < regs[TM_PIPR]) { + lsmfb_min < pipr_min) { /* * Thread has seen a group interrupt with a higher priority * than the new cppr or pending local interrupt. Check the @@ -1048,12 +1047,25 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uin= t8_t ring, uint8_t cppr) nvp_blk, nvp_idx, first_group, &group_le= vel); tctx->regs[ring_min + TM_LSMFB] =3D backlog_prio; - if (backlog_prio !=3D 0xFF) { - xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx, - backlog_prio, group_level); - regs[TM_PIPR] =3D backlog_prio; + if (backlog_prio !=3D lsmfb_min) { + /* + * If the group backlog scan finds a less favored or no interr= upt, + * then re-do the processing which may turn up a more favored + * interrupt from IPB or the other pool. Backlog should not + * find a priority < LSMFB. + */ + g_assert(backlog_prio >=3D lsmfb_min); + goto again; } + + xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx, + backlog_prio, group_level); + pipr_min =3D backlog_prio; } + + /* PIPR should not be set to a value greater than CPPR */ + regs[TM_PIPR] =3D (pipr_min > cppr) ? cppr : pipr_min; + /* CPPR has changed, check if we need to raise a pending exception */ xive_tctx_notify(tctx, ring_min, group_level); } --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115162; cv=none; d=zohomail.com; s=zohoarc; b=GWLz1mRiLvvOBCRBD0xLNE/0kJibPAviOjsZ3bHl19ZN7l7XNU09wshuzTGA0ECVyjKrUOj5VSbOrhT1SI9DYfN4k+ZUU/mn/RYiVS6CjuBkMn4UgQ2uprDmD2tITTFXpAlJxXQf48uxNZiX/8KUpjm2UcWYngWJ0lIwUT41mYM= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:23:15 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0A7F1195608D; Mon, 21 Jul 2025 16:23:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115002; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jnnN5+GtdpuH7z4EFdFOk5KedjDZ6TIb4J90RWfBUp0=; b=jWEVvqAWW8G4PwLgkszHM3rNJizUHaxr6LTMBL4OgVbRxNVwWmAHTaqoRFECwWCS+mxrnK 0WYfjxWWHt1+pTzES8HM/Xr7f1p08VIzH5RkwQnynqeSdPuMG9A83/bDNTH3NU/SWRTz9D iOc4TTqaItlLvBJ9+W2IMeNdKuHNARY= X-MC-Unique: -czOhk3vN5-2bbkpgk-row-1 X-Mimecast-MFC-AGG-ID: -czOhk3vN5-2bbkpgk-row_1753114995 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 13/50] ppc/xive: tctx_notify should clear the precluded interrupt Date: Mon, 21 Jul 2025 18:21:56 +0200 Message-ID: <20250721162233.686837-14-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115163475116600 From: Nicholas Piggin If CPPR is lowered to preclude the pending interrupt, NSR should be cleared and the qemu_irq should be lowered. This avoids some cases of supurious interrupts. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-14-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index bc829bebe9d0..a0a60a24f510 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -110,6 +110,9 @@ void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uin= t8_t group_level) regs[TM_IPB], alt_regs[TM_PIPR], alt_regs[TM_CPPR], alt_regs[TM_NSR]); qemu_irq_raise(xive_tctx_output(tctx, ring)); + } else { + alt_regs[TM_NSR] =3D 0; + qemu_irq_lower(xive_tctx_output(tctx, ring)); } } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=mOnTSLxJi5yj63cfC5aTMnrzLcPnJGX7PJdWzyG0SaU=; b=asfoMaIdOSfXxd16GSKKAaKsyfrxk28MC/Wj5TKWD9uE3uhUtJBBlJ7HEM6w1Ruu5J0HY2 AhvSTaIgb4UDTLyVWg5hCB23+7COWDaD9qMqZYhAhYO1KHEGqWT5XID+HkndIYpzllSbcy JB1ejeHC+CdlESSR93wRSY78djReSQk= X-MC-Unique: ODq7BigxPXudfA59YZgs4w-1 X-Mimecast-MFC-AGG-ID: ODq7BigxPXudfA59YZgs4w_1753114998 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 14/50] ppc/xive: Explicitly zero NSR after accepting Date: Mon, 21 Jul 2025 18:21:57 +0200 Message-ID: <20250721162233.686837-15-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115214270116600 From: Nicholas Piggin Have xive_tctx_accept clear NSR in one shot rather than masking out bits as they are tested, which makes it clear it's reset to 0, and does not have a partial NSR value in the register. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-15-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index a0a60a24f510..b35d2ec1793e 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -68,13 +68,11 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_= t ring) * If the interrupt was for a specific VP, reset the pending * buffer bit, otherwise clear the logical server indicator */ - if (regs[TM_NSR] & TM_NSR_GRP_LVL) { - regs[TM_NSR] &=3D ~TM_NSR_GRP_LVL; - } else { + if (!(regs[TM_NSR] & TM_NSR_GRP_LVL)) { alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); } =20 - /* Drop the exception bit and any group/crowd */ + /* Clear the exception from NSR */ regs[TM_NSR] =3D 0; =20 trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115004; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aoGnDApgNu0EkgdF9KtXDN8OWeByCAqj+mmqYM6gKEA=; b=dunV1qNaJf78GWsF8vRqu74Ma3mxuHT5epI7qkAucpUMVtUGYZbUkAIharlEYEe7rtMll2 Y9SkOzKDt9rGyB68Y1bYrzKJRXNk562i0HE33zhXAmRSeaxnxO4+B2XfdJhwIET9Zxw3za qHoCvhPFoYgCQdrHGArqJIGoLnUzl5M= X-MC-Unique: mrY21r5vPuC9SIJsS3Q6dg-1 X-Mimecast-MFC-AGG-ID: mrY21r5vPuC9SIJsS3Q6dg_1753115001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 15/50] ppc/xive: Move NSR decoding into helper functions Date: Mon, 21 Jul 2025 18:21:58 +0200 Message-ID: <20250721162233.686837-16-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115477547116600 From: Nicholas Piggin Rather than functions to return masks to test NSR bits, have functions to test those bits directly. This should be no functional change, it just makes the code more readable. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-16-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 4 ++++ hw/intc/xive.c | 51 +++++++++++++++++++++++++++++++++++-------- 2 files changed, 46 insertions(+), 9 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 538f43868172..28f0f1b79ad7 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -365,6 +365,10 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring) return *((uint32_t *) &ring[TM_WORD2]); } =20 +bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr); +bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr); +uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr); + /* * XIVE Router */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index b35d2ec1793e..8537cad27b2a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -25,6 +25,45 @@ /* * XIVE Thread Interrupt Management context */ +bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr) +{ + switch (ring) { + case TM_QW1_OS: + return !!(nsr & TM_QW1_NSR_EO); + case TM_QW2_HV_POOL: + case TM_QW3_HV_PHYS: + return !!(nsr & TM_QW3_NSR_HE); + default: + g_assert_not_reached(); + } +} + +bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr) +{ + if ((nsr & TM_NSR_GRP_LVL) > 0) { + g_assert(xive_nsr_indicates_exception(ring, nsr)); + return true; + } + return false; +} + +uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr) +{ + /* NSR determines if pool/phys ring is for phys or pool interrupt */ + if ((ring =3D=3D TM_QW3_HV_PHYS) || (ring =3D=3D TM_QW2_HV_POOL)) { + uint8_t he =3D (nsr & TM_QW3_NSR_HE) >> 6; + + if (he =3D=3D TM_QW3_NSR_HE_PHYS) { + return TM_QW3_HV_PHYS; + } else if (he =3D=3D TM_QW3_NSR_HE_POOL) { + return TM_QW2_HV_POOL; + } else { + /* Don't support LSI mode */ + g_assert_not_reached(); + } + } + return ring; +} =20 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) { @@ -48,18 +87,12 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_= t ring) =20 qemu_irq_lower(xive_tctx_output(tctx, ring)); =20 - if (regs[TM_NSR] !=3D 0) { + if (xive_nsr_indicates_exception(ring, nsr)) { uint8_t cppr =3D regs[TM_PIPR]; uint8_t alt_ring; uint8_t *alt_regs; =20 - /* POOL interrupt uses IPB in QW2, POOL ring */ - if ((ring =3D=3D TM_QW3_HV_PHYS) && - ((nsr & TM_QW3_NSR_HE) =3D=3D (TM_QW3_NSR_HE_POOL << 6))) { - alt_ring =3D TM_QW2_HV_POOL; - } else { - alt_ring =3D ring; - } + alt_ring =3D xive_nsr_exception_ring(ring, nsr); alt_regs =3D &tctx->regs[alt_ring]; =20 regs[TM_CPPR] =3D cppr; @@ -68,7 +101,7 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t= ring) * If the interrupt was for a specific VP, reset the pending * buffer bit, otherwise clear the logical server indicator */ - if (!(regs[TM_NSR] & TM_NSR_GRP_LVL)) { + if (!xive_nsr_indicates_group_exception(ring, nsr)) { alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=4P91xUOwhTWKJ4gGibaAj8HR9uDmnK4QlXLqudLjOJQ=; b=Z7QjF4eA5k3Jh1PsCejMrIY0BQ+rslTNtp2VDXWepgxqMY7Hh0ijDYJTxFq70/Z2U1rZfA RQBuJqImBmZRhkPu45dsTqI2ghFEVafi0IpRedqAWuhbJMtnw7OvgE4kYY6LyvVA15tISI RMzerLoXA9zMMRURhUiKNgeL+wqBig4= X-MC-Unique: o-Aj0uhTPC6ubbnMVIS8XA-1 X-Mimecast-MFC-AGG-ID: o-Aj0uhTPC6ubbnMVIS8XA_1753115004 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 16/50] ppc/xive: Fix pulling pool and phys contexts Date: Mon, 21 Jul 2025 18:21:59 +0200 Message-ID: <20250721162233.686837-17-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116169611116600 From: Nicholas Piggin This improves the implementation of pulling pool and phys contexts in XIVE1, by following closer the OS pulling code. In particular, the old ring data is returned rather than the modified, and irq signals are reset on pull. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-17-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 66 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 8 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8537cad27b2a..5483a815ef07 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -241,25 +241,75 @@ static uint64_t xive_tm_ack_hv_reg(XivePresenter *xpt= r, XiveTCTX *tctx, return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); } =20 +static void xive_pool_cam_decode(uint32_t cam, uint8_t *nvt_blk, + uint32_t *nvt_idx, bool *vp) +{ + if (nvt_blk) { + *nvt_blk =3D xive_nvt_blk(cam); + } + if (nvt_idx) { + *nvt_idx =3D xive_nvt_idx(cam); + } + if (vp) { + *vp =3D !!(cam & TM_QW2W2_VP); + } +} + +static uint32_t xive_tctx_get_pool_cam(XiveTCTX *tctx, uint8_t *nvt_blk, + uint32_t *nvt_idx, bool *vp) +{ + uint32_t qw2w2 =3D xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); + uint32_t cam =3D be32_to_cpu(qw2w2); + + xive_pool_cam_decode(cam, nvt_blk, nvt_idx, vp); + return qw2w2; +} + +static void xive_tctx_set_pool_cam(XiveTCTX *tctx, uint32_t qw2w2) +{ + memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); +} + static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint32_t qw2w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); uint32_t qw2w2; + uint32_t qw2w2_new; + uint8_t nvt_blk; + uint32_t nvt_idx; + bool vp; =20 - qw2w2 =3D xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); - memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); + qw2w2 =3D xive_tctx_get_pool_cam(tctx, &nvt_blk, &nvt_idx, &vp); + + if (!vp) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pull invalid POOL NVT %x/%x = !?\n", + nvt_blk, nvt_idx); + } + + /* Invalidate CAM line */ + qw2w2_new =3D xive_set_field32(TM_QW2W2_VP, qw2w2, 0); + xive_tctx_set_pool_cam(tctx, qw2w2_new); + + xive_tctx_reset_signal(tctx, TM_QW1_OS); + xive_tctx_reset_signal(tctx, TM_QW2_HV_POOL); return qw2w2; } =20 static uint64_t xive_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint8_t qw3b8_prev =3D tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; - uint8_t qw3b8; + uint8_t qw3b8 =3D tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; + uint8_t qw3b8_new; + + qw3b8 =3D tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; + if (!(qw3b8 & TM_QW3B8_VT)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid PHYS thread!= ?\n"); + } + qw3b8_new =3D qw3b8 & ~TM_QW3B8_VT; + tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] =3D qw3b8_new; =20 - qw3b8 =3D qw3b8_prev & ~TM_QW3B8_VT; - tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] =3D qw3b8; + xive_tctx_reset_signal(tctx, TM_QW1_OS); + xive_tctx_reset_signal(tctx, TM_QW3_HV_PHYS); return qw3b8; } =20 @@ -489,7 +539,7 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr= , XiveTCTX *tctx, qw1w2 =3D xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); =20 if (!vo) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?= \n", + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pull invalid OS NVT %x/%x !?= \n", nvt_blk, nvt_idx); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115319569116600 From: Glenn Miles Add support for XIVE ESB Interrupt Escalation. Suggested-by: Michael Kowal [This change was taken from a patch provided by Michael Kowal.] Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-18-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2.h | 1 + include/hw/ppc/xive2_regs.h | 13 +++++--- hw/intc/xive2.c | 62 ++++++++++++++++++++++++++++++------- 3 files changed, 59 insertions(+), 17 deletions(-) diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index 8cdf8191742e..2436ddb5e53c 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -80,6 +80,7 @@ int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, uint32_t xive2_router_get_config(Xive2Router *xrtr); =20 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); +void xive2_notify(Xive2Router *xrtr, uint32_t lisn, bool pq_checked); =20 /* * XIVE2 Presenter (POWER10) diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 3c28de8a304d..2c535ec0d0f1 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -39,15 +39,18 @@ =20 typedef struct Xive2Eas { uint64_t w; -#define EAS2_VALID PPC_BIT(0) -#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ blo= ck# */ -#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ in= dex */ -#define EAS2_MASKED PPC_BIT(32) /* Masked */ -#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the E= Q */ +#define EAS2_VALID PPC_BIT(0) +#define EAS2_QOS PPC_BIT(1, 2) /* Quality of Service(unimp= ) */ +#define EAS2_RESUME PPC_BIT(3) /* END Resume(unimp) */ +#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */ +#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */ +#define EAS2_MASKED PPC_BIT(32) /* Masked */ +#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */ } Xive2Eas; =20 #define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID) #define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED) +#define xive2_eas_is_resume(eas) (be64_to_cpu((eas)->w) & EAS2_RESUME) =20 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf); =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index cca121b5f13c..541b05225cd2 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1552,18 +1552,39 @@ do_escalation: } } =20 - /* - * The END trigger becomes an Escalation trigger - */ - xive2_router_end_notify(xrtr, - xive_get_field32(END2_W4_END_BLOCK, end.w4), - xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), - xive_get_field32(END2_W5_ESC_END_DATA, end.w5)= ); + if (xive2_end_is_escalate_end(&end)) { + /* + * Perform END Adaptive escalation processing + * The END trigger becomes an Escalation trigger + */ + xive2_router_end_notify(xrtr, + xive_get_field32(END2_W4_END_BLOCK, end= .w4), + xive_get_field32(END2_W4_ESC_END_INDEX, end= .w4), + xive_get_field32(END2_W5_ESC_END_DATA, end= .w5)); + } /* end END adaptive escalation */ + + else { + uint32_t lisn; /* Logical Interrupt Source Number */ + + /* + * Perform ESB escalation processing + * E[N] =3D=3D 1 --> N + * Req[Block] <- E[ESB_Block] + * Req[Index] <- E[ESB_Index] + * Req[Offset] <- 0x000 + * Execute Req command + */ + lisn =3D XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4), + xive_get_field32(END2_W4_ESC_END_INDEX, end.w4)); + + xive2_notify(xrtr, lisn, true /* pq_checked */); + } + + return; } =20 -void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) +void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked) { - Xive2Router *xrtr =3D XIVE2_ROUTER(xn); uint8_t eas_blk =3D XIVE_EAS_BLOCK(lisn); uint32_t eas_idx =3D XIVE_EAS_INDEX(lisn); Xive2Eas eas; @@ -1606,13 +1627,30 @@ void xive2_router_notify(XiveNotifier *xn, uint32_t= lisn, bool pq_checked) return; } =20 + /* TODO: add support for EAS resume */ + if (xive2_eas_is_resume(&eas)) { + qemu_log_mask(LOG_UNIMP, + "XIVE: EAS resume processing unimplemented - LISN %x= \n", + lisn); + return; + } + /* * The event trigger becomes an END trigger */ xive2_router_end_notify(xrtr, - xive_get_field64(EAS2_END_BLOCK, eas.w), - xive_get_field64(EAS2_END_INDEX, eas.w), - xive_get_field64(EAS2_END_DATA, eas.w)); + xive_get_field64(EAS2_END_BLOCK, eas.w), + xive_get_field64(EAS2_END_INDEX, eas.w), + xive_get_field64(EAS2_END_DATA, eas.w)); + return; +} + +void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) +{ + Xive2Router *xrtr =3D XIVE2_ROUTER(xn); + + xive2_notify(xrtr, lisn, pq_checked); + return; } =20 static const Property xive2_router_properties[] =3D { --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115868; cv=none; d=zohomail.com; s=zohoarc; b=WNEStjcq+Vb7ZkpB6zAQfatiCxwFQMfiq9r00bgvsVzQhPhtkEQhrzMWLIPT/05ijz2UpU+GKSAeV70y5hhcXtrC8KncotE1qlxjIU8sIULA5QMzm0/8lnC9PS8h+iXGL89KGOt7wfDiHlVHuEuCiyVtFBv4r9cM9qp8wueGrMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753115868; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 21 Jul 2025 16:23:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115017; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jzuyb0TwYPkuBmLFTkEwXo7WimGA6V333RZVisJcj7U=; b=FG+HfR3ShNIXKFh1OZHUVTfpCEsYslXmy5jnJvdxzzhnZNJMOs/f9pz//BchrkgZAaVHKm G1iDYwR7g93FEngicgETcweK/xzWtyWHfUVHmWJSZANDV0dTFePB9ZXE5h3CQHZhgJ9/1K VroRQex+0GLlo1IvWsBdoLhDOSSRE3A= X-MC-Unique: CcKn392TO6KUpuK5e_G0bg-1 X-Mimecast-MFC-AGG-ID: CcKn392TO6KUpuK5e_G0bg_1753115010 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Michael Kowal , Glenn Miles , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 18/50] pnv/xive2: Print value in invalid register write logging Date: Mon, 21 Jul 2025 18:22:01 +0200 Message-ID: <20250721162233.686837-19-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115870041116600 From: Michael Kowal This can make it easier to see what the target system is trying to do. [npiggin: split from larger patch] Signed-off-by: Michael Kowal Reviewed-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-19-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 25dc8a372d2f..9d53537e3e09 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1197,7 +1197,8 @@ static void pnv_xive2_ic_cq_write(void *opaque, hwadd= r offset, case CQ_FIRMASK_OR: /* FIR error reporting */ break; default: - xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); + xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx" value 0x%"PR= Ix64, + offset, val); return; } =20 @@ -1495,7 +1496,8 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwadd= r offset, break; =20 default: - xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); + xive2_error(xive, "VC: invalid write @0x%"HWADDR_PRIx" value 0x%"P= RIx64, + offset, val); return; } =20 @@ -1703,7 +1705,8 @@ static void pnv_xive2_ic_pc_write(void *opaque, hwadd= r offset, break; =20 default: - xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); + xive2_error(xive, "PC: invalid write @0x%"HWADDR_PRIx" value 0x%"P= RIx64, + offset, val); return; } =20 @@ -1790,7 +1793,8 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hw= addr offset, xive->tctxt_regs[reg] =3D val; break; default: - xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); + xive2_error(xive, "TCTXT: invalid write @0x%"HWADDR_PRIx + " data 0x%"PRIx64, offset, val); return; } } @@ -1861,7 +1865,8 @@ static void pnv_xive2_xscom_write(void *opaque, hwadd= r offset, pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); break; default: - xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); + xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx + " value 0x%"PRIx64, offset, val); } } =20 @@ -1929,7 +1934,8 @@ static void pnv_xive2_ic_notify_write(void *opaque, h= waddr offset, break; =20 default: - xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); + xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx + " value 0x%"PRIx64, offset, val); } } =20 @@ -1971,7 +1977,8 @@ static void pnv_xive2_ic_lsi_write(void *opaque, hwad= dr offset, { PnvXive2 *xive =3D PNV_XIVE2(opaque); =20 - xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); + xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx" value 0x%"PRIx64, + offset, val); } =20 static const MemoryRegionOps pnv_xive2_ic_lsi_ops =3D { @@ -2074,7 +2081,8 @@ static void pnv_xive2_ic_sync_write(void *opaque, hwa= ddr offset, inject_type =3D PNV_XIVE2_QUEUE_NXC_ST_RMT_CI; break; default: - xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); + xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx" value 0x%"P= RIx64, + offset, val); return; } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115018; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fafAR+MZ+XdSYEtCgiGonqqx3/PnRIji9nRwNDPHnq8=; b=f0Jb5CiAyAR3gaDSqNYszIR76sCRGg55B1JShpgIJONIr9NUJ3MExDWjIqJIBYD/GUEYA6 nr/tng5kSIq6g5g9d1u2albA3+ppNL9GCtnGDPRYGPy2cHZtXCmK6AR0UTpLyHR0TAvI+L kNPQ9vQz046Wb4ikvelxZbacQZbC6aM= X-MC-Unique: z3rEQt5uMJ6FT7ghQ-If-A-1 X-Mimecast-MFC-AGG-ID: z3rEQt5uMJ6FT7ghQ-If-A_1753115013 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 19/50] pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL Date: Mon, 21 Jul 2025 18:22:02 +0200 Message-ID: <20250721162233.686837-20-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115311297116600 From: Nicholas Piggin Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC register, so don't clear it on read. Don't bother clearing the reads-as-zero CONFLICT bit because it's masked at write already. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-20-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 9d53537e3e09..e15f414d0bb3 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1329,7 +1329,6 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hw= addr offset, case VC_ENDC_WATCH2_SPEC: case VC_ENDC_WATCH3_SPEC: watch_engine =3D (offset - VC_ENDC_WATCH0_SPEC) >> 6; - xive->vc_regs[reg] &=3D ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFL= ICT); pnv_xive2_endc_cache_watch_release(xive, watch_engine); val =3D xive->vc_regs[reg]; break; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=Ac/QUVQGSJO1a5hZVsjUbANeNkNU/atUCzOkeaMJXV0=; b=THhIW017X5cgvZbo9uoHmouR5MfAzi2hAFm8xxAI/Xas3ZbrdfqSRUTCrszShWGBLqJH7g 2yTWmT3dNtF77wEdIf4dxFgo0M2cWi+odnDYRRYqapUNW+R+YFO//sx5EHdCgF8BLETz/X 86Pnej4I5XgfNW2fKZhP0qM9pN1Ub8c= X-MC-Unique: fvGerBM_Orqh30blk3q3zA-1 X-Mimecast-MFC-AGG-ID: fvGerBM_Orqh30blk3q3zA_1753115016 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Michael Kowal , Glenn Miles , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers Date: Mon, 21 Jul 2025 18:22:03 +0200 Message-ID: <20250721162233.686837-21-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115855770116600 From: Michael Kowal Writes to the Flush Control registers were logged as invalid when they are allowed. Clearing the unsupported want_cache_disable feature is supported, so don't log an error in that case. Signed-off-by: Michael Kowal Reviewed-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-21-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index e15f414d0bb3..386175a68b29 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1411,7 +1411,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwad= dr offset, /* * ESB cache updates (not modeled) */ - /* case VC_ESBC_FLUSH_CTRL: */ + case VC_ESBC_FLUSH_CTRL: + if (val & VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE) { + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx + " value 0x%"PRIx64" bit[2] poll_want_cache_disable= ", + offset, val); + return; + } + break; case VC_ESBC_FLUSH_POLL: xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |=3D VC_ESBC_FLUSH_CTRL_POL= L_VALID; /* ESB update */ @@ -1427,7 +1434,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwad= dr offset, /* * EAS cache updates (not modeled) */ - /* case VC_EASC_FLUSH_CTRL: */ + case VC_EASC_FLUSH_CTRL: + if (val & VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE) { + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx + " value 0x%"PRIx64" bit[2] poll_want_cache_disable= ", + offset, val); + return; + } + break; case VC_EASC_FLUSH_POLL: xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |=3D VC_EASC_FLUSH_CTRL_POL= L_VALID; /* EAS update */ @@ -1466,7 +1480,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwad= dr offset, break; =20 =20 - /* case VC_ENDC_FLUSH_CTRL: */ + case VC_ENDC_FLUSH_CTRL: + if (val & VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE) { + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx + " value 0x%"PRIx64" bit[2] poll_want_cache_disable= ", + offset, val); + return; + } + break; case VC_ENDC_FLUSH_POLL: xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |=3D VC_ENDC_FLUSH_CTRL_POL= L_VALID; break; @@ -1687,7 +1708,14 @@ static void pnv_xive2_ic_pc_write(void *opaque, hwad= dr offset, pnv_xive2_nxc_update(xive, watch_engine); break; =20 - /* case PC_NXC_FLUSH_CTRL: */ + case PC_NXC_FLUSH_CTRL: + if (val & PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE) { + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx + " value 0x%"PRIx64" bit[2] poll_want_cache_disable= ", + offset, val); + return; + } + break; case PC_NXC_FLUSH_POLL: xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |=3D PC_NXC_FLUSH_CTRL_POLL_= VALID; break; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115116; cv=none; d=zohomail.com; s=zohoarc; b=KrtHdgbjXTI1SXkKvOavJmOdc658XNFRUk3gyJZn/L4kbjI+sjyloGUnv4JC/jRCVZHnYoQWYqWyvrCdX1z3r4Dq2zpx4+TPqAv0NkD+qRDITkVxF65Dy7AEHddYia8V6cReAGFN+MTZqYI80VNADQX4bl/vZqGMmQ1ct8msvqA= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:23:38 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B0C3B195608D; Mon, 21 Jul 2025 16:23:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115024; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qd1iNcZC0N9VKbrwXqHYfPlyCqr8C4u9TzFB9ZV+KSY=; b=iR1ZYa8RkBlMt+I9L0a4Gt+U1Qejo8sWXL86WPUFfqe0Dtn2yPSd6aRx1Y2932ijdqO5xh ggIZWkJfdCTSs7dZbR4Eir7dJ1ZfYyZ9bXgexRjz56Akux/51n9PYO0L824KGK+xRaV4N5 J6ziS9fosDQJl+EYQNLWIpJswl5buBI= X-MC-Unique: wAz6JxDTM-6YUVFDguNR4A-1 X-Mimecast-MFC-AGG-ID: wAz6JxDTM-6YUVFDguNR4A_1753115019 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 21/50] ppc/xive2: add interrupt priority configuration flags Date: Mon, 21 Jul 2025 18:22:04 +0200 Message-ID: <20250721162233.686837-22-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115117356116600 From: Glenn Miles Adds support for extracting additional configuration flags from the XIVE configuration register that are needed for redistribution of group interrupts. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-22-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2_regs.h | 1 + include/hw/ppc/xive2.h | 8 +++++--- hw/intc/pnv_xive2.c | 16 ++++++++++++---- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index e8b87b3d2c13..d53300f709b0 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -66,6 +66,7 @@ #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25= ]=3D0 */ #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25= ]=3D0 */ #define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28) +#define CQ_XIVE_CFG_EN_VP_GRP_PRIORITY PPC_BIT(32) /* 0 if bit[25= ]=3D1 */ #define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25= ]=3D1 */ #define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25= ]=3D1 */ =20 diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index 2436ddb5e53c..760b94a962e7 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -29,9 +29,11 @@ OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2= _ROUTER); * Configuration flags */ =20 -#define XIVE2_GEN1_TIMA_OS 0x00000001 -#define XIVE2_VP_SAVE_RESTORE 0x00000002 -#define XIVE2_THREADID_8BITS 0x00000004 +#define XIVE2_GEN1_TIMA_OS 0x00000001 +#define XIVE2_VP_SAVE_RESTORE 0x00000002 +#define XIVE2_THREADID_8BITS 0x00000004 +#define XIVE2_EN_VP_GRP_PRIORITY 0x00000008 +#define XIVE2_VP_INT_PRIO 0x00000030 =20 typedef struct Xive2RouterClass { SysBusDeviceClass parent; diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 386175a68b29..7b4a33228e05 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -605,20 +605,28 @@ static uint32_t pnv_xive2_get_config(Xive2Router *xrt= r) { PnvXive2 *xive =3D PNV_XIVE2(xrtr); uint32_t cfg =3D 0; + uint64_t reg =3D xive->cq_regs[CQ_XIVE_CFG >> 3]; =20 - if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { + if (reg & CQ_XIVE_CFG_GEN1_TIMA_OS) { cfg |=3D XIVE2_GEN1_TIMA_OS; } =20 - if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { + if (reg & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { cfg |=3D XIVE2_VP_SAVE_RESTORE; } =20 - if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, - xive->cq_regs[CQ_XIVE_CFG >> 3]) =3D=3D CQ_XIVE_CFG_THREADID= _8BITS) { + if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, reg) =3D=3D + CQ_XIVE_CFG_THREADID_8BITS) { cfg |=3D XIVE2_THREADID_8BITS; } =20 + if (reg & CQ_XIVE_CFG_EN_VP_GRP_PRIORITY) { + cfg |=3D XIVE2_EN_VP_GRP_PRIORITY; + } + + cfg =3D SETFIELD(XIVE2_VP_INT_PRIO, cfg, + GETFIELD(CQ_XIVE_CFG_VP_INT_PRIO, reg)); + return cfg; } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115331; cv=none; d=zohomail.com; s=zohoarc; b=ScRazS0zunXTIGVpxnlHMaN/SOXXuM2SQjecU9S3NB1XNCzwhlqZIWxIYM5EgQASWhWtmu0m1qZBtUtVykHA97p6F8dmWe+/Ymk78JZ2x8mZJ4k5m2JqPqgjxmmTu1hENj+M1bLvtArzF4egHBF3ud6Y7p6XKGr9VAboy0aBVLI= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:23:41 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 63923195608D; Mon, 21 Jul 2025 16:23:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wbsatBWGHnXK0ln5RenIDg9eQQYBOHkeiL6Ce6cZ+TY=; b=a1WWEMhvKBioM1btrJrpFAmhGGJY2nqObx0P/DH96R6vJ6joC11OnsbUWM0qT5dU1utTx5 1HB3hLOcPbgriDneVId/+vCqJXHilOh0FqDFO3/FqNQY8cdfLyxHCLQhewkL3qMFLI7HRG jDguevlJHvblq4MEU0H4ROa8S6IItQM= X-MC-Unique: 57TcfSAqNRm2W4OOBNdvsg-1 X-Mimecast-MFC-AGG-ID: 57TcfSAqNRm2W4OOBNdvsg_1753115021 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 22/50] ppc/xive2: Support redistribution of group interrupts Date: Mon, 21 Jul 2025 18:22:05 +0200 Message-ID: <20250721162233.686837-23-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115331704116600 From: Glenn Miles When an XIVE context is pulled while it has an active, unacknowledged group interrupt, XIVE will check to see if a context on another thread can handle the interrupt and, if so, notify that context. If there are no contexts that can handle the interrupt, then the interrupt is added to a backlog and XIVE will attempt to escalate the interrupt, if configured to do so, allowing the higher privileged handler to activate a context that can handle the original interrupt. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-23-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2_regs.h | 3 ++ hw/intc/xive2.c | 84 +++++++++++++++++++++++++++++++++++-- 2 files changed, 83 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 2c535ec0d0f1..e22203814312 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -224,6 +224,9 @@ typedef struct Xive2Nvgc { #define NVGC2_W0_VALID PPC_BIT32(0) #define NVGC2_W0_PGONEXT PPC_BITMASK32(26, 31) uint32_t w1; +#define NVGC2_W1_PSIZE PPC_BITMASK32(0, 1) +#define NVGC2_W1_END_BLK PPC_BITMASK32(4, 7) +#define NVGC2_W1_END_IDX PPC_BITMASK32(8, 31) uint32_t w2; uint32_t w3; uint32_t w4; diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 541b05225cd2..9ef372b6d1d9 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -19,6 +19,10 @@ #include "hw/ppc/xive2_regs.h" #include "trace.h" =20 +static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, + uint32_t end_idx, uint32_t end_data, + bool redistribute); + uint32_t xive2_router_get_config(Xive2Router *xrtr) { Xive2RouterClass *xrc =3D XIVE2_ROUTER_GET_CLASS(xrtr); @@ -597,6 +601,68 @@ static uint32_t xive2_tctx_hw_cam_line(XivePresenter *= xptr, XiveTCTX *tctx) return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); } =20 +static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, + uint8_t nvp_blk, uint32_t nvp_idx, uint8_t = ring) +{ + uint8_t nsr =3D tctx->regs[ring + TM_NSR]; + uint8_t crowd =3D NVx_CROWD_LVL(nsr); + uint8_t group =3D NVx_GROUP_LVL(nsr); + uint8_t nvgc_blk; + uint8_t nvgc_idx; + uint8_t end_blk; + uint32_t end_idx; + uint8_t pipr =3D tctx->regs[ring + TM_PIPR]; + Xive2Nvgc nvgc; + uint8_t prio_limit; + uint32_t cfg; + + /* convert crowd/group to blk/idx */ + if (group > 0) { + nvgc_idx =3D (nvp_idx & (0xffffffff << group)) | + ((1 << (group - 1)) - 1); + } else { + nvgc_idx =3D nvp_idx; + } + + if (crowd > 0) { + crowd =3D (crowd =3D=3D 3) ? 4 : crowd; + nvgc_blk =3D (nvp_blk & (0xffffffff << crowd)) | + ((1 << (crowd - 1)) - 1); + } else { + nvgc_blk =3D nvp_blk; + } + + /* Use blk/idx to retrieve the NVGC */ + if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", + crowd ? "NVC" : "NVG", nvgc_blk, nvgc_idx); + return; + } + + /* retrieve the END blk/idx from the NVGC */ + end_blk =3D xive_get_field32(NVGC2_W1_END_BLK, nvgc.w1); + end_idx =3D xive_get_field32(NVGC2_W1_END_IDX, nvgc.w1); + + /* determine number of priorities being used */ + cfg =3D xive2_router_get_config(xrtr); + if (cfg & XIVE2_EN_VP_GRP_PRIORITY) { + prio_limit =3D 1 << GETFIELD(NVGC2_W1_PSIZE, nvgc.w1); + } else { + prio_limit =3D 1 << GETFIELD(XIVE2_VP_INT_PRIO, cfg); + } + + /* add priority offset to end index */ + end_idx +=3D pipr % prio_limit; + + /* trigger the group END */ + xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); + + /* clear interrupt indication for the context */ + tctx->regs[ring + TM_NSR] =3D 0; + tctx->regs[ring + TM_PIPR] =3D tctx->regs[ring + TM_CPPR]; + xive_tctx_reset_signal(tctx, ring); +} + static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size, uint8_t ri= ng) { @@ -608,6 +674,7 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, = XiveTCTX *tctx, uint8_t cur_ring; bool valid; bool do_save; + uint8_t nsr; =20 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); =20 @@ -624,6 +691,12 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr,= XiveTCTX *tctx, memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); } =20 + /* Active group/crowd interrupts need to be redistributed */ + nsr =3D tctx->regs[ring + TM_NSR]; + if (xive_nsr_indicates_group_exception(ring, nsr)) { + xive2_redistribute(xrtr, tctx, nvp_blk, nvp_idx, ring); + } + if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring); } @@ -1352,7 +1425,8 @@ static bool xive2_router_end_es_notify(Xive2Router *x= rtr, uint8_t end_blk, * message has the same parameters than in the function below. */ static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, - uint32_t end_idx, uint32_t end_data) + uint32_t end_idx, uint32_t end_data, + bool redistribute) { Xive2End end; uint8_t priority; @@ -1380,7 +1454,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, return; } =20 - if (xive2_end_is_enqueue(&end)) { + if (!redistribute && xive2_end_is_enqueue(&end)) { xive2_end_enqueue(&end, end_data); /* Enqueuing event data modifies the EQ toggle and index */ xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); @@ -1560,7 +1634,8 @@ do_escalation: xive2_router_end_notify(xrtr, xive_get_field32(END2_W4_END_BLOCK, end= .w4), xive_get_field32(END2_W4_ESC_END_INDEX, end= .w4), - xive_get_field32(END2_W5_ESC_END_DATA, end= .w5)); + xive_get_field32(END2_W5_ESC_END_DATA, end= .w5), + false); } /* end END adaptive escalation */ =20 else { @@ -1641,7 +1716,8 @@ void xive2_notify(Xive2Router *xrtr , uint32_t lisn, = bool pq_checked) xive2_router_end_notify(xrtr, xive_get_field64(EAS2_END_BLOCK, eas.w), xive_get_field64(EAS2_END_INDEX, eas.w), - xive_get_field64(EAS2_END_DATA, eas.w)); + xive_get_field64(EAS2_END_DATA, eas.w), + false); return; } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ae03GpkOra3utBvabjI+lTPzw6ZwaHjahEszLORnpAU=; b=PZL876FLlNbixlGQBi8bQ2Q9AwNjouYBG0Gv6etoLjwDIRJ5SwIpn9a4PHwTiIDCcCgJA3 yUUwEZUhGbSBuud/pUMib+9XzNRB3sB6oyTEhRw6kDlVt8qGS5BMhg1zj9vh44YDa3z3OF WOQgO+YH4u640Fnsp0mLMVbc0UUp00I= X-MC-Unique: WYm42aLINumeuWb6aU6jsA-1 X-Mimecast-MFC-AGG-ID: WYm42aLINumeuWb6aU6jsA_1753115024 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 23/50] ppc/xive: Add more interrupt notification tracing Date: Mon, 21 Jul 2025 18:22:06 +0200 Message-ID: <20250721162233.686837-24-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116078410116600 From: Glenn Miles Add more tracing around notification, redistribution, and escalation. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-24-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 3 +++ hw/intc/xive2.c | 13 ++++++++----- hw/intc/trace-events | 6 ++++++ 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5483a815ef07..d65394651650 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1276,6 +1276,7 @@ static uint64_t xive_source_esb_read(void *opaque, hw= addr addr, unsigned size) =20 /* Forward the source event notification for routing */ if (ret) { + trace_xive_source_notify(srcno); xive_source_notify(xsrc, srcno); } break; @@ -1371,6 +1372,8 @@ out: /* Forward the source event notification for routing */ if (notify) { xive_source_notify(xsrc, srcno); + } else { + trace_xive_source_blocked(srcno); } } =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 9ef372b6d1d9..f810e716dee3 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -616,6 +616,7 @@ static void xive2_redistribute(Xive2Router *xrtr, XiveT= CTX *tctx, uint8_t prio_limit; uint32_t cfg; =20 + trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); /* convert crowd/group to blk/idx */ if (group > 0) { nvgc_idx =3D (nvp_idx & (0xffffffff << group)) | @@ -1455,6 +1456,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, } =20 if (!redistribute && xive2_end_is_enqueue(&end)) { + trace_xive_end_enqueue(end_blk, end_idx, end_data); xive2_end_enqueue(&end, end_data); /* Enqueuing event data modifies the EQ toggle and index */ xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); @@ -1631,11 +1633,11 @@ do_escalation: * Perform END Adaptive escalation processing * The END trigger becomes an Escalation trigger */ - xive2_router_end_notify(xrtr, - xive_get_field32(END2_W4_END_BLOCK, end= .w4), - xive_get_field32(END2_W4_ESC_END_INDEX, end= .w4), - xive_get_field32(END2_W5_ESC_END_DATA, end= .w5), - false); + uint8_t esc_blk =3D xive_get_field32(END2_W4_END_BLOCK, end.w4); + uint32_t esc_idx =3D xive_get_field32(END2_W4_ESC_END_INDEX, end.w= 4); + uint32_t esc_data =3D xive_get_field32(END2_W5_ESC_END_DATA, end.w= 5); + trace_xive_escalate_end(end_blk, end_idx, esc_blk, esc_idx, esc_da= ta); + xive2_router_end_notify(xrtr, esc_blk, esc_idx, esc_data, false); } /* end END adaptive escalation */ =20 else { @@ -1652,6 +1654,7 @@ do_escalation: lisn =3D XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4), xive_get_field32(END2_W4_ESC_END_INDEX, end.w4)); =20 + trace_xive_escalate_esb(end_blk, end_idx, lisn); xive2_notify(xrtr, lisn, true /* pq_checked */); } =20 diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 9ed2616e58fe..018c609ca5eb 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -279,6 +279,8 @@ xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t = ipb, uint8_t pipr, uint8_ xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr= , uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IPB=3D0x%02x PIPR=3D0= x%02x new CPPR=3D0x%02x NSR=3D0x%02x" xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"= PRIx64" IRQ 0x%x val=3D0x%"PRIx64 xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%= "PRIx64" IRQ 0x%x val=3D0x%"PRIx64 +xive_source_notify(uint32_t srcno) "Processing notification for queued IRQ= 0x%x" +xive_source_blocked(uint32_t srcno) "No action needed for IRQ 0x%x current= ly" xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_dat= a) "END 0x%02x/0x%04x -> enqueue 0x%08x" xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_bl= k, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END = 0x%02x/0x%04x data 0x%08x" xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uin= t64_t value) "target=3D%d @0x%"PRIx64" sz=3D%d val=3D0x%" PRIx64 @@ -289,6 +291,10 @@ xive_end_source_read(uint8_t end_blk, uint32_t end_idx= , uint64_t addr) "END 0x%x # xive2.c xive_nvp_backlog_op(uint8_t blk, uint32_t idx, uint8_t op, uint8_t priorit= y, uint8_t rc) "NVP 0x%x/0x%x operation=3D%d priority=3D%d rc=3D%d" xive_nvgc_backlog_op(bool c, uint8_t blk, uint32_t idx, uint8_t op, uint8_= t priority, uint32_t rc) "NVGC crowd=3D%d 0x%x/0x%x operation=3D%d priority= =3D%d rc=3D%d" +xive_redistribute(uint32_t index, uint8_t ring, uint8_t end_blk, uint32_t = end_idx) "Redistribute from target=3D%d ring=3D0x%x NVP 0x%x/0x%x" +xive_end_enqueue(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "Qu= eue event for END 0x%x/0x%x data=3D0x%x" +xive_escalate_end(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint= 32_t esc_idx, uint32_t esc_data) "Escalate from END 0x%x/0x%x to END 0x%x/0= x%x data=3D0x%x" +xive_escalate_esb(uint8_t end_blk, uint32_t end_idx, uint32_t lisn) "Escal= ate from END 0x%x/0x%x to LISN=3D0x%x" =20 # pnv_xive.c pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=3D0x= %"PRIx64 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115169576116600 From: Glenn Miles Change pregs to pool_regs, for clarity. [npiggin: split from larger patch] Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-25-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index f810e716dee3..1f4713dabeb1 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1044,13 +1044,12 @@ again: =20 /* PHYS updates also depend on POOL values */ if (ring =3D=3D TM_QW3_HV_PHYS) { - uint8_t *pregs =3D &tctx->regs[TM_QW2_HV_POOL]; + uint8_t *pool_regs =3D &tctx->regs[TM_QW2_HV_POOL]; =20 /* POOL values only matter if POOL ctx is valid */ - if (pregs[TM_WORD2] & 0x80) { - - uint8_t pool_pipr =3D xive_ipb_to_pipr(pregs[TM_IPB]); - uint8_t pool_lsmfb =3D pregs[TM_LSMFB]; + if (pool_regs[TM_WORD2] & 0x80) { + uint8_t pool_pipr =3D xive_ipb_to_pipr(pool_regs[TM_IPB]); + uint8_t pool_lsmfb =3D pool_regs[TM_LSMFB]; =20 /* * Determine highest priority interrupt and @@ -1064,7 +1063,7 @@ again: } =20 /* Values needed for group priority calculation */ - if (pregs[TM_LGS] && (pool_lsmfb < lsmfb_min)) { + if (pool_regs[TM_LGS] && (pool_lsmfb < lsmfb_min)) { group_enabled =3D true; lsmfb_min =3D pool_lsmfb; if (lsmfb_min < pipr_min) { --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115143; cv=none; d=zohomail.com; s=zohoarc; b=kLiaWNma9UQDBJIwjnYKdya4j7PTI7v1jNbK5/CYKwTx3bQgeLG5ijkPEFAosamjfbgdtRV9FisQ87YFuTHEfa9uDCTZMVtER9kDEBR9x/txpLln1Di8TsgO7XgvPOmPcIw5TnUGdq0SDwgujl4HUpxVySAwcKBvyZtZKWfzD14= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Mon, 21 Jul 2025 16:23:49 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A04CA195608D; Mon, 21 Jul 2025 16:23:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115032; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZbQlkH2kV33T/Osdjmait2KYKih6VX6OQ5Yd5M/d8MU=; b=h4WMZ5nof5HEmhiDPYRVIa29mi7UHEPlxX1+BwpKj0Z1+HnhQ0IFBBAcB69N52lEcz9Imt XZu0puF2rIEpPP0KZhollFLB7W8Jaw3TTV9xDnT4cuTxptWL5IwrqCOFrogowbfCptQNXU TAVJ8T0ZzVxm9EQpf54y0SwSiOD/760= X-MC-Unique: gVFe9pniMJmp4aLv9qewGw-1 X-Mimecast-MFC-AGG-ID: gVFe9pniMJmp4aLv9qewGw_1753115029 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 25/50] ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA op Date: Mon, 21 Jul 2025 18:22:08 +0200 Message-ID: <20250721162233.686837-26-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115145555116600 From: Glenn Miles Booting AIX in a PowerVM partition requires the use of the "Acknowledge O/S Interrupt to even O/S reporting line" special operation provided by the IBM XIVE interrupt controller. This operation is invoked by writing a byte (data is irrelevant) to offset 0xC10 of the Thread Interrupt Management Area (TIMA). It can be used by software to notify the XIVE logic that the interrupt was received. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-26-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 1 + include/hw/ppc/xive2.h | 3 ++- hw/intc/xive.c | 8 ++++--- hw/intc/xive2.c | 50 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 28f0f1b79ad7..46d05d74fbfb 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -561,6 +561,7 @@ void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring= , uint8_t priority, uint8_t group_level); void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring); void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level); +uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring); =20 /* * KVM XIVE device helpers diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index 760b94a962e7..ff02ce254984 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -142,5 +142,6 @@ void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTC= TX *tctx, hwaddr offset, uint64_t value, unsigned size); void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned siz= e); - +void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); #endif /* PPC_XIVE2_H */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index d65394651650..8b705727ae2d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -80,7 +80,7 @@ static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t = ring) } } =20 -static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) +uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) { uint8_t *regs =3D &tctx->regs[ring]; uint8_t nsr =3D regs[TM_NSR]; @@ -340,14 +340,14 @@ static uint64_t xive_tm_vt_poll(XivePresenter *xptr, = XiveTCTX *tctx, =20 static const uint8_t xive_tm_hw_view[] =3D { 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ - 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ + 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */ 0, 0, 3, 3, 0, 3, 3, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ }; =20 static const uint8_t xive_tm_hv_view[] =3D { 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ - 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ + 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */ 0, 0, 3, 3, 0, 3, 3, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ }; @@ -718,6 +718,8 @@ static const XiveTmOp xive2_tm_operations[] =3D { xive_tm_pull_phys_ctx= }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ct= x_ol, NULL }, + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, xive2_tm_ack_os_el, + NULL }, }; =20 static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 1f4713dabeb1..e7e364c13e7d 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1009,6 +1009,56 @@ static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx= , uint8_t ring, return 0; } =20 +static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx, + uint8_t ring, uint8_t cl_ring) +{ + uint64_t rd; + Xive2Router *xrtr =3D XIVE2_ROUTER(xptr); + uint32_t nvp_blk, nvp_idx, xive2_cfg; + Xive2Nvp nvp; + uint64_t phys_addr; + uint8_t OGen =3D 0; + + xive2_tctx_get_nvp_indexes(tctx, cl_ring, &nvp_blk, &nvp_idx); + + if (xive2_router_get_nvp(xrtr, (uint8_t)nvp_blk, nvp_idx, &nvp)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", + nvp_blk, nvp_idx); + return; + } + + if (!xive2_nvp_is_valid(&nvp)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", + nvp_blk, nvp_idx); + return; + } + + + rd =3D xive_tctx_accept(tctx, ring); + + if (ring =3D=3D TM_QW1_OS) { + OGen =3D tctx->regs[ring + TM_OGEN]; + } + xive2_cfg =3D xive2_router_get_config(xrtr); + phys_addr =3D xive2_nvp_reporting_addr(&nvp); + uint8_t report_data[REPORT_LINE_GEN1_SIZE]; + memset(report_data, 0xff, sizeof(report_data)); + if ((OGen =3D=3D 1) || (xive2_cfg & XIVE2_GEN1_TIMA_OS)) { + report_data[8] =3D (rd >> 8) & 0xff; + report_data[9] =3D rd & 0xff; + } else { + report_data[0] =3D (rd >> 8) & 0xff; + report_data[1] =3D rd & 0xff; + } + cpu_physical_memory_write(phys_addr, report_data, REPORT_LINE_GEN1_SIZ= E); +} + +void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); +} + static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { uint8_t *regs =3D &tctx->regs[ring]; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115303; cv=none; d=zohomail.com; s=zohoarc; b=JlyTne8ojaEYUwwa1Ym9n3cnJ1WwBgTCCgRguB6Hj84THXzv5re2ckfCmiqIcfMUVhkQ/7Qa3t9Bf2qf6kqG9EFLNWbKgu+fDhmBTJWmbMZWTUF4VjiLjddimoh0CN6cLCUMlXPd06bnYC8wWsvlcs7jiPsw2vSWvlxSKU2jj6s= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:23:52 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 52E90195608D; Mon, 21 Jul 2025 16:23:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115039; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E4IHHFsRnHNOOaMjSVNzNwIUDK3mKklHBP4ufzDwJW8=; b=i9XSVpR2YtI/twh8S5gBL7q3JLuhOUjKN1vYEp3LHg1Bnql9CU+LpwbeySxdebNZfy57Zg iOFKlERNC39IEb1LyVMSLJS1hFAuSt40AEWNWknhRjyzGarC6P9uoi6SeCjxZnJC/NkneG 5rWn/OL79abbQXM4tdhAt1269vl8jKI= X-MC-Unique: wHOHOwz-OMCBPNNi7dNDFA-1 X-Mimecast-MFC-AGG-ID: wHOHOwz-OMCBPNNi7dNDFA_1753115032 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 26/50] ppc/xive2: Redistribute group interrupt precluded by CPPR update Date: Mon, 21 Jul 2025 18:22:09 +0200 Message-ID: <20250721162233.686837-27-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115305321116600 From: Glenn Miles Add support for redistributing a presented group interrupt if it is precluded as a result of changing the CPPR value. Without this, group interrupts can be lost. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-27-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 82 ++++++++++++++++++++++++++++++++++++------------- 1 file changed, 60 insertions(+), 22 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index e7e364c13e7d..624620e5b44b 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -601,20 +601,37 @@ static uint32_t xive2_tctx_hw_cam_line(XivePresenter = *xptr, XiveTCTX *tctx) return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); } =20 -static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, - uint8_t nvp_blk, uint32_t nvp_idx, uint8_t = ring) +static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t = ring) { - uint8_t nsr =3D tctx->regs[ring + TM_NSR]; + uint8_t *regs =3D &tctx->regs[ring]; + uint8_t nsr =3D regs[TM_NSR]; + uint8_t pipr =3D regs[TM_PIPR]; uint8_t crowd =3D NVx_CROWD_LVL(nsr); uint8_t group =3D NVx_GROUP_LVL(nsr); - uint8_t nvgc_blk; - uint8_t nvgc_idx; - uint8_t end_blk; - uint32_t end_idx; - uint8_t pipr =3D tctx->regs[ring + TM_PIPR]; + uint8_t nvgc_blk, end_blk, nvp_blk; + uint32_t nvgc_idx, end_idx, nvp_idx; Xive2Nvgc nvgc; uint8_t prio_limit; uint32_t cfg; + uint8_t alt_ring; + uint32_t target_ringw2; + uint32_t cam; + bool valid; + bool hw; + + /* redistribution is only for group/crowd interrupts */ + if (!xive_nsr_indicates_group_exception(ring, nsr)) { + return; + } + + alt_ring =3D xive_nsr_exception_ring(ring, nsr); + target_ringw2 =3D xive_tctx_word2(&tctx->regs[alt_ring]); + cam =3D be32_to_cpu(target_ringw2); + + /* extract nvp block and index from targeted ring's cam */ + xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &hw); + + trace_xive_redistribute(tctx->cs->cpu_index, alt_ring, nvp_blk, nvp_id= x); =20 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); /* convert crowd/group to blk/idx */ @@ -659,8 +676,8 @@ static void xive2_redistribute(Xive2Router *xrtr, XiveT= CTX *tctx, xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); =20 /* clear interrupt indication for the context */ - tctx->regs[ring + TM_NSR] =3D 0; - tctx->regs[ring + TM_PIPR] =3D tctx->regs[ring + TM_CPPR]; + regs[TM_NSR] =3D 0; + regs[TM_PIPR] =3D regs[TM_CPPR]; xive_tctx_reset_signal(tctx, ring); } =20 @@ -695,7 +712,7 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, = XiveTCTX *tctx, /* Active group/crowd interrupts need to be redistributed */ nsr =3D tctx->regs[ring + TM_NSR]; if (xive_nsr_indicates_group_exception(ring, nsr)) { - xive2_redistribute(xrtr, tctx, nvp_blk, nvp_idx, ring); + xive2_redistribute(xrtr, tctx, ring); } =20 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { @@ -1059,6 +1076,7 @@ void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX= *tctx, xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); } =20 +/* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { uint8_t *regs =3D &tctx->regs[ring]; @@ -1069,10 +1087,11 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uin= t8_t ring, uint8_t cppr) uint32_t nvp_blk, nvp_idx; Xive2Nvp nvp; int rc; + uint8_t nsr =3D regs[TM_NSR]; =20 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, regs[TM_IPB], regs[TM_PIPR], - cppr, regs[TM_NSR]); + cppr, nsr); =20 if (cppr > XIVE_PRIORITY_MAX) { cppr =3D 0xff; @@ -1081,6 +1100,35 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint= 8_t ring, uint8_t cppr) old_cppr =3D regs[TM_CPPR]; regs[TM_CPPR] =3D cppr; =20 + /* Handle increased CPPR priority (lower value) */ + if (cppr < old_cppr) { + if (cppr <=3D regs[TM_PIPR]) { + /* CPPR lowered below PIPR, must un-present interrupt */ + if (xive_nsr_indicates_exception(ring, nsr)) { + if (xive_nsr_indicates_group_exception(ring, nsr)) { + /* redistribute precluded active grp interrupt */ + xive2_redistribute(xrtr, tctx, ring); + return; + } + } + + /* interrupt is VP directed, pending in IPB */ + regs[TM_PIPR] =3D cppr; + xive_tctx_notify(tctx, ring, 0); /* Ensure interrupt is cleare= d */ + return; + } else { + /* CPPR was lowered, but still above PIPR. No action needed. */ + return; + } + } + + /* CPPR didn't change, nothing needs to be done */ + if (cppr =3D=3D old_cppr) { + return; + } + + /* CPPR priority decreased (higher value) */ + /* * Recompute the PIPR based on local pending interrupts. It will * be adjusted below if needed in case of pending group interrupts. @@ -1129,16 +1177,6 @@ again: return; } =20 - if (cppr < old_cppr) { - /* - * FIXME: check if there's a group interrupt being presented - * and if the new cppr prevents it. If so, then the group - * interrupt needs to be re-added to the backlog and - * re-triggered (see re-trigger END info in the NVGC - * structure) - */ - } - if (group_enabled && lsmfb_min < cppr && lsmfb_min < pipr_min) { --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753116122; cv=none; d=zohomail.com; s=zohoarc; b=DegpuwWT86NTubR3b9CYO9GPsvBEFRkoLcWYdzST/ylVvP8rDhq31e6siIGpRcmFvbT5l/Oof7GuGAVpjOs9h/mrU+spGY2QJ8szPFSlBSWI7MwH630M/ETO4Y69UTQRa8IFj25W4whOhnbVGHlbPrnaUv4Skd90zCCYNpoXfXY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753116122; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 21 Jul 2025 16:23:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115037; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kkRFCiBMKL4MHUQ7Zugvdw1BQnwkezmc+oEfEDLl7GU=; b=HEM9nEyOnrmnez8gWWbyTd7pc6hW7RBO5OyJCmv8oR50xDh8DoITbiKpKL3BxN0Fr+BKFL ZqaNIQRUyaDuyQABayexYIxWeoP0lYYSax9tBQ09xf25nnpaGYH3jnC6sNfTIrj0z0J2cl j3NBQ0BmIjzI+obHMytRyKUG/xJMWPU= X-MC-Unique: Ruov8_hNPCqFfL4sVBzZ_A-1 X-Mimecast-MFC-AGG-ID: Ruov8_hNPCqFfL4sVBzZ_A_1753115035 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 27/50] ppc/xive2: redistribute irqs for pool and phys ctx pull Date: Mon, 21 Jul 2025 18:22:10 +0200 Message-ID: <20250721162233.686837-28-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116129330116600 From: Glenn Miles When disabling (pulling) an xive interrupt context, we need to redistribute any active group interrupts to other threads that can handle the interrupt if possible. This support had already been added for the OS context but had not yet been added to the pool or physical context. Signed-off-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-28-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2.h | 4 ++ include/hw/ppc/xive2_regs.h | 4 +- hw/intc/xive.c | 12 ++--- hw/intc/xive2.c | 94 ++++++++++++++++++++++++++----------- 4 files changed, 79 insertions(+), 35 deletions(-) diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index ff02ce254984..a91b99057c2a 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -140,6 +140,10 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, = uint8_t priority); void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority); void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); +uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size); +uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size); void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned siz= e); void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index e22203814312..f82054661bda 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -209,9 +209,9 @@ static inline uint32_t xive2_nvp_idx(uint32_t cam_line) return cam_line & ((1 << XIVE2_NVP_SHIFT) - 1); } =20 -static inline uint32_t xive2_nvp_blk(uint32_t cam_line) +static inline uint8_t xive2_nvp_blk(uint32_t cam_line) { - return (cam_line >> XIVE2_NVP_SHIFT) & 0xf; + return (uint8_t)((cam_line >> XIVE2_NVP_SHIFT) & 0xf); } =20 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *bu= f); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8b705727ae2d..2f72d6ecd5a5 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -693,7 +693,7 @@ static const XiveTmOp xive2_tm_operations[] =3D { =20 /* MMIOs above 2K : special operations with side effects */ { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, - xive_tm_ack_os_reg }, + xive_tm_ack_os_reg }, { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pendin= g, NULL }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL, @@ -705,17 +705,17 @@ static const XiveTmOp xive2_tm_operations[] =3D { { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL, - xive_tm_pull_pool_ctx= }, + xive2_tm_pull_pool_ct= x }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, - xive_tm_pull_pool_ctx= }, + xive2_tm_pull_pool_ct= x }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, - xive_tm_pull_pool_ctx= }, + xive2_tm_pull_pool_ct= x }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_= ol, NULL }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL, - xive_tm_pull_phys_ctx= }, + xive2_tm_pull_phys_ct= x }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, - xive_tm_pull_phys_ctx= }, + xive2_tm_pull_phys_ct= x }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ct= x_ol, NULL }, { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, xive2_tm_ack_os_el, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 624620e5b44b..2791985cf29b 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -23,6 +23,9 @@ static void xive2_router_end_notify(Xive2Router *xrtr, ui= nt8_t end_blk, uint32_t end_idx, uint32_t end_data, bool redistribute); =20 +static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, + uint8_t *nvp_blk, uint32_t *nvp_idx); + uint32_t xive2_router_get_config(Xive2Router *xrtr) { Xive2RouterClass *xrc =3D XIVE2_ROUTER_GET_CLASS(xrtr); @@ -604,8 +607,10 @@ static uint32_t xive2_tctx_hw_cam_line(XivePresenter *= xptr, XiveTCTX *tctx) static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t = ring) { uint8_t *regs =3D &tctx->regs[ring]; - uint8_t nsr =3D regs[TM_NSR]; - uint8_t pipr =3D regs[TM_PIPR]; + uint8_t *alt_regs =3D (ring =3D=3D TM_QW2_HV_POOL) ? &tctx->regs[TM_QW= 3_HV_PHYS] : + regs; + uint8_t nsr =3D alt_regs[TM_NSR]; + uint8_t pipr =3D alt_regs[TM_PIPR]; uint8_t crowd =3D NVx_CROWD_LVL(nsr); uint8_t group =3D NVx_GROUP_LVL(nsr); uint8_t nvgc_blk, end_blk, nvp_blk; @@ -614,10 +619,6 @@ static void xive2_redistribute(Xive2Router *xrtr, Xive= TCTX *tctx, uint8_t ring) uint8_t prio_limit; uint32_t cfg; uint8_t alt_ring; - uint32_t target_ringw2; - uint32_t cam; - bool valid; - bool hw; =20 /* redistribution is only for group/crowd interrupts */ if (!xive_nsr_indicates_group_exception(ring, nsr)) { @@ -625,11 +626,9 @@ static void xive2_redistribute(Xive2Router *xrtr, Xive= TCTX *tctx, uint8_t ring) } =20 alt_ring =3D xive_nsr_exception_ring(ring, nsr); - target_ringw2 =3D xive_tctx_word2(&tctx->regs[alt_ring]); - cam =3D be32_to_cpu(target_ringw2); =20 - /* extract nvp block and index from targeted ring's cam */ - xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &hw); + /* Don't check return code since ring is expected to be invalidated */ + xive2_tctx_get_nvp_indexes(tctx, alt_ring, &nvp_blk, &nvp_idx); =20 trace_xive_redistribute(tctx->cs->cpu_index, alt_ring, nvp_blk, nvp_id= x); =20 @@ -676,11 +675,23 @@ static void xive2_redistribute(Xive2Router *xrtr, Xiv= eTCTX *tctx, uint8_t ring) xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); =20 /* clear interrupt indication for the context */ - regs[TM_NSR] =3D 0; - regs[TM_PIPR] =3D regs[TM_CPPR]; + alt_regs[TM_NSR] =3D 0; + alt_regs[TM_PIPR] =3D alt_regs[TM_CPPR]; xive_tctx_reset_signal(tctx, ring); } =20 +static uint8_t xive2_hv_irq_ring(uint8_t nsr) +{ + switch (nsr >> 6) { + case TM_QW3_NSR_HE_POOL: + return TM_QW2_HV_POOL; + case TM_QW3_NSR_HE_PHYS: + return TM_QW3_HV_PHYS; + default: + return -1; + } +} + static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size, uint8_t ri= ng) { @@ -696,7 +707,7 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, = XiveTCTX *tctx, =20 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); =20 - if (!valid) { + if (xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?= \n", nvp_blk, nvp_idx); } @@ -706,13 +717,25 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr= , XiveTCTX *tctx, cur_ring +=3D XIVE_TM_RING_SIZE) { uint32_t ringw2 =3D xive_tctx_word2(&tctx->regs[cur_ring]); uint32_t ringw2_new =3D xive_set_field32(TM2_QW1W2_VO, ringw2, 0); + bool is_valid =3D !!(xive_get_field32(TM2_QW1W2_VO, ringw2)); + uint8_t alt_ring; memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); - } =20 - /* Active group/crowd interrupts need to be redistributed */ - nsr =3D tctx->regs[ring + TM_NSR]; - if (xive_nsr_indicates_group_exception(ring, nsr)) { - xive2_redistribute(xrtr, tctx, ring); + /* Skip the rest for USER or invalid contexts */ + if ((cur_ring =3D=3D TM_QW0_USER) || !is_valid) { + continue; + } + + /* Active group/crowd interrupts need to be redistributed */ + alt_ring =3D (cur_ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : c= ur_ring; + nsr =3D tctx->regs[alt_ring + TM_NSR]; + if (xive_nsr_indicates_group_exception(alt_ring, nsr)) { + /* For HV rings, only redistribute if cur_ring matches NSR */ + if ((cur_ring =3D=3D TM_QW1_OS) || + (cur_ring =3D=3D xive2_hv_irq_ring(nsr))) { + xive2_redistribute(xrtr, tctx, cur_ring); + } + } } =20 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { @@ -736,6 +759,18 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, Xiv= eTCTX *tctx, return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); } =20 +uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) +{ + return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW2_HV_POOL); +} + +uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) +{ + return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW3_HV_PHYS); +} + #define REPORT_LINE_GEN1_SIZE 16 =20 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, @@ -993,37 +1028,40 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveT= CTX *tctx, } } =20 +/* returns -1 if ring is invalid, but still populates block and index */ static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, - uint32_t *nvp_blk, uint32_t *nvp_idx) + uint8_t *nvp_blk, uint32_t *nvp_idx) { - uint32_t w2, cam; + uint32_t w2; + uint32_t cam =3D 0; + int rc =3D 0; =20 w2 =3D xive_tctx_word2(&tctx->regs[ring]); switch (ring) { case TM_QW1_OS: if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) { - return -1; + rc =3D -1; } cam =3D xive_get_field32(TM2_QW1W2_OS_CAM, w2); break; case TM_QW2_HV_POOL: if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) { - return -1; + rc =3D -1; } cam =3D xive_get_field32(TM2_QW2W2_POOL_CAM, w2); break; case TM_QW3_HV_PHYS: if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) { - return -1; + rc =3D -1; } cam =3D xive2_tctx_hw_cam_line(tctx->xptr, tctx); break; default: - return -1; + rc =3D -1; } *nvp_blk =3D xive2_nvp_blk(cam); *nvp_idx =3D xive2_nvp_idx(cam); - return 0; + return rc; } =20 static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx, @@ -1031,7 +1069,8 @@ static void xive2_tctx_accept_el(XivePresenter *xptr,= XiveTCTX *tctx, { uint64_t rd; Xive2Router *xrtr =3D XIVE2_ROUTER(xptr); - uint32_t nvp_blk, nvp_idx, xive2_cfg; + uint32_t nvp_idx, xive2_cfg; + uint8_t nvp_blk; Xive2Nvp nvp; uint64_t phys_addr; uint8_t OGen =3D 0; @@ -1084,7 +1123,8 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8= _t ring, uint8_t cppr) uint8_t old_cppr, backlog_prio, first_group, group_level; uint8_t pipr_min, lsmfb_min, ring_min; bool group_enabled; - uint32_t nvp_blk, nvp_idx; + uint8_t nvp_blk; + uint32_t nvp_idx; Xive2Nvp nvp; int rc; uint8_t nsr =3D regs[TM_NSR]; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115318; cv=none; d=zohomail.com; s=zohoarc; b=fhf8yRZ/8iQnkf49zJ+wpS4mzzEFVS1XyUtePPTVb7nd3wbGO/7IyBbxXYcXgrqU+cRWPA8mU6nvbYjpUVetKnUhBaNf2jZKNNQPpr7AklHlMKAhja+Xy+u5aCIkqUO4cm7UQDrXGEJjK7IanMotsqP7bgUC+23ENakYdWDrNPA= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115325889116600 From: Nicholas Piggin Have the match_nvt method only perform a TCTX match but don't present the interrupt, the caller presents. This has no functional change, but allows for more complicated presentation logic after matching. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-29-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 27 +++++++++++++---------- hw/intc/pnv_xive.c | 16 +++++++------- hw/intc/pnv_xive2.c | 16 +++++++------- hw/intc/spapr_xive.c | 18 +++++++-------- hw/intc/xive.c | 51 +++++++++++++++---------------------------- hw/intc/xive2.c | 31 +++++++++++++------------- hw/ppc/pnv.c | 48 ++++++++++++++-------------------------- hw/ppc/spapr.c | 21 +++++++----------- 8 files changed, 97 insertions(+), 131 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 46d05d74fbfb..8152a9df3d39 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -425,6 +425,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *= eas); =20 typedef struct XiveTCTXMatch { XiveTCTX *tctx; + int count; uint8_t ring; bool precluded; } XiveTCTXMatch; @@ -440,10 +441,10 @@ DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESE= NTER, =20 struct XivePresenterClass { InterfaceClass parent; - int (*match_nvt)(XivePresenter *xptr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match); + bool (*match_nvt)(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); bool (*in_kernel)(const XivePresenter *xptr); uint32_t (*get_config)(XivePresenter *xptr); int (*broadcast)(XivePresenter *xptr, @@ -455,12 +456,14 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xi= veTCTX *tctx, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint32_t logic_serv); -bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t priority, - uint32_t logic_serv, bool *precluded); +bool xive_presenter_match(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); =20 uint32_t xive_get_vpgroup_size(uint32_t nvp_index); +uint8_t xive_get_group_level(bool crowd, bool ignore, + uint32_t nvp_blk, uint32_t nvp_index); =20 /* * XIVE Fabric (Interface between Interrupt Controller and Machine) @@ -475,10 +478,10 @@ DECLARE_CLASS_CHECKERS(XiveFabricClass, XIVE_FABRIC, =20 struct XiveFabricClass { InterfaceClass parent; - int (*match_nvt)(XiveFabric *xfb, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match); + bool (*match_nvt)(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); int (*broadcast)(XiveFabric *xfb, uint8_t nvt_blk, uint32_t nvt_idx, bool crowd, bool cam_ignore, uint8_t priority); }; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 935c0e4742f5..c2ca40b8be87 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -470,14 +470,13 @@ static bool pnv_xive_is_cpu_enabled(PnvXive *xive, Po= werPCCPU *cpu) return xive->regs[reg >> 3] & PPC_BIT(bit); } =20 -static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t priorit= y, - uint32_t logic_serv, XiveTCTXMatch *match) +static bool pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t priori= ty, + uint32_t logic_serv, XiveTCTXMatch *match) { PnvXive *xive =3D PNV_XIVE(xptr); PnvChip *chip =3D xive->chip; - int count =3D 0; int i, j; =20 for (i =3D 0; i < chip->nr_cores; i++) { @@ -510,17 +509,18 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, ui= nt8_t format, qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " "thread context NVT %x/%x\n", nvt_blk, nvt_idx); - return -1; + match->count++; + continue; } =20 match->ring =3D ring; match->tctx =3D tctx; - count++; + match->count++; } } } =20 - return count; + return !!match->count; } =20 static uint32_t pnv_xive_presenter_get_config(XivePresenter *xptr) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 7b4a33228e05..e019cad5c14c 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -640,14 +640,13 @@ static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, = PowerPCCPU *cpu) return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); } =20 -static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t priori= ty, - uint32_t logic_serv, XiveTCTXMatch *match) +static bool pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t prior= ity, + uint32_t logic_serv, XiveTCTXMatch *match) { PnvXive2 *xive =3D PNV_XIVE2(xptr); PnvChip *chip =3D xive->chip; - int count =3D 0; int i, j; bool gen1_tima_os =3D xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; @@ -692,7 +691,8 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uin= t8_t format, "thread context NVT %x/%x\n", nvt_blk, nvt_idx); /* Should set a FIR if we ever model it */ - return -1; + match->count++; + continue; } /* * For a group notification, we need to know if the @@ -717,13 +717,13 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, u= int8_t format, } } } - count++; + match->count++; } } } } =20 - return count; + return !!match->count; } =20 static uint32_t pnv_xive2_presenter_get_config(XivePresenter *xptr) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 440edb97d8d3..e393f5dcdccf 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -428,14 +428,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uin= t8_t nvt_blk, g_assert_not_reached(); } =20 -static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, - uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match) +static bool spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, + uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) { CPUState *cs; - int count =3D 0; =20 CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -463,16 +462,17 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, = uint8_t format, if (match->tctx) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thre= ad " "context NVT %x/%x\n", nvt_blk, nvt_idx); - return -1; + match->count++; + continue; } =20 match->ring =3D ring; match->tctx =3D tctx; - count++; + match->count++; } } =20 - return count; + return !!match->count; } =20 static uint32_t spapr_xive_presenter_get_config(XivePresenter *xptr) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 2f72d6ecd5a5..c92e819053e8 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1762,8 +1762,8 @@ uint32_t xive_get_vpgroup_size(uint32_t nvp_index) return 1U << (first_zero + 1); } =20 -static uint8_t xive_get_group_level(bool crowd, bool ignore, - uint32_t nvp_blk, uint32_t nvp_index) +uint8_t xive_get_group_level(bool crowd, bool ignore, + uint32_t nvp_blk, uint32_t nvp_index) { int first_zero; uint8_t level; @@ -1881,15 +1881,14 @@ int xive_presenter_tctx_match(XivePresenter *xptr, = XiveTCTX *tctx, * This is our simple Xive Presenter Engine model. It is merged in the * Router as it does not require an extra object. */ -bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, +bool xive_presenter_match(XiveFabric *xfb, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool crowd, bool cam_ignore, uint8_t priority, - uint32_t logic_serv, bool *precluded) + uint32_t logic_serv, XiveTCTXMatch *match) { XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb); - XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0, .precluded =3D = false }; - uint8_t group_level; - int count; + + memset(match, 0, sizeof(*match)); =20 /* * Ask the machine to scan the interrupt controllers for a match. @@ -1914,22 +1913,8 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t = format, * a new command to the presenters (the equivalent of the "assign" * power bus command in the documented full notify sequence. */ - count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, crowd, cam_ign= ore, - priority, logic_serv, &match); - if (count < 0) { - return false; - } - - /* handle CPU exception delivery */ - if (count) { - group_level =3D xive_get_group_level(crowd, cam_ignore, nvt_blk, n= vt_idx); - trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le= vel); - xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve= l); - } else { - *precluded =3D match.precluded; - } - - return !!count; + return xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, crowd, cam_ignore, + priority, logic_serv, match); } =20 /* @@ -1966,7 +1951,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS= *eas) uint8_t nvt_blk; uint32_t nvt_idx; XiveNVT nvt; - bool found, precluded; + XiveTCTXMatch match; =20 uint8_t end_blk =3D xive_get_field64(EAS_END_BLOCK, eas->w); uint32_t end_idx =3D xive_get_field64(EAS_END_INDEX, eas->w); @@ -2046,16 +2031,16 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveE= AS *eas) return; } =20 - found =3D xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, - false /* crowd */, - xive_get_field32(END_W7_F0_IGNORE, end.w7), - priority, - xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7= ), - &precluded); - /* we don't support VP-group notification on P9, so precluded is not u= sed */ /* TODO: Auto EOI. */ - - if (found) { + /* we don't support VP-group notification on P9, so precluded is not u= sed */ + if (xive_presenter_match(xrtr->xfb, format, nvt_blk, nvt_idx, + false /* crowd */, + xive_get_field32(END_W7_F0_IGNORE, end.w7), + priority, + xive_get_field32(END_W7_F1_LOG_SERVER_ID, end= .w7), + &match)) { + trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, 0); + xive_tctx_pipr_update(match.tctx, match.ring, priority, 0); return; } =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 2791985cf29b..602b23d06d80 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1559,7 +1559,8 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, Xive2End end; uint8_t priority; uint8_t format; - bool found, precluded; + XiveTCTXMatch match; + bool crowd, cam_ignore; uint8_t nvx_blk; uint32_t nvx_idx; =20 @@ -1629,16 +1630,19 @@ static void xive2_router_end_notify(Xive2Router *xr= tr, uint8_t end_blk, */ nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end.w6); nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end.w6); - - found =3D xive_presenter_notify(xrtr->xfb, format, nvx_blk, nvx_idx, - xive2_end_is_crowd(&end), xive2_end_is_ignore(&e= nd), - priority, - xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w= 7), - &precluded); + crowd =3D xive2_end_is_crowd(&end); + cam_ignore =3D xive2_end_is_ignore(&end); =20 /* TODO: Auto EOI. */ - - if (found) { + if (xive_presenter_match(xrtr->xfb, format, nvx_blk, nvx_idx, + crowd, cam_ignore, priority, + xive_get_field32(END2_W7_F1_LOG_SERVER_ID, en= d.w7), + &match)) { + uint8_t group_level; + + group_level =3D xive_get_group_level(crowd, cam_ignore, nvx_blk, n= vx_idx); + trace_xive_presenter_notify(nvx_blk, nvx_idx, match.ring, group_le= vel); + xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve= l); return; } =20 @@ -1656,7 +1660,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, return; } =20 - if (!xive2_end_is_ignore(&end)) { + if (!cam_ignore) { uint8_t ipb; Xive2Nvp nvp; =20 @@ -1685,9 +1689,6 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, } else { Xive2Nvgc nvgc; uint32_t backlog; - bool crowd; - - crowd =3D xive2_end_is_crowd(&end); =20 /* * For groups and crowds, the per-priority backlog @@ -1719,9 +1720,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, if (backlog =3D=3D 1) { XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xrtr->xfb); xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx, - xive2_end_is_crowd(&end), - xive2_end_is_ignore(&end), - priority); + crowd, cam_ignore, priority); =20 if (!xive2_end_is_precluded_escalation(&end)) { /* diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 4a49e9d1a865..d84c9067edb3 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2608,62 +2608,46 @@ static void pnv_pic_print_info(InterruptStatsProvid= er *obj, GString *buf) } } =20 -static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t priority, - uint32_t logic_serv, - XiveTCTXMatch *match) +static bool pnv_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t priority, + uint32_t logic_serv, + XiveTCTXMatch *match) { PnvMachineState *pnv =3D PNV_MACHINE(xfb); - int total_count =3D 0; int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); XivePresenter *xptr =3D XIVE_PRESENTER(&chip9->xive); XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); - int count; =20 - count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, - cam_ignore, priority, logic_serv, match); - - if (count < 0) { - return count; - } - - total_count +=3D count; + xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, + cam_ignore, priority, logic_serv, match); } =20 - return total_count; + return !!match->count; } =20 -static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t prior= ity, - uint32_t logic_serv, - XiveTCTXMatch *match) +static bool pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t prio= rity, + uint32_t logic_serv, + XiveTCTXMatch *match) { PnvMachineState *pnv =3D PNV_MACHINE(xfb); - int total_count =3D 0; int i; =20 for (i =3D 0; i < pnv->num_chips; i++) { Pnv10Chip *chip10 =3D PNV10_CHIP(pnv->chips[i]); XivePresenter *xptr =3D XIVE_PRESENTER(&chip10->xive); XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); - int count; - - count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, - cam_ignore, priority, logic_serv, match); - - if (count < 0) { - return count; - } =20 - total_count +=3D count; + xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, + cam_ignore, priority, logic_serv, match); } =20 - return total_count; + return !!match->count; } =20 static int pnv10_xive_broadcast(XiveFabric *xfb, diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 40f53ad7b344..1855a3cd8d03 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4468,21 +4468,14 @@ static void spapr_pic_print_info(InterruptStatsProv= ider *obj, GString *buf) /* * This is a XIVE only operation */ -static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool crowd, bool cam_ignore, uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match) +static bool spapr_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool crowd, bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) { SpaprMachineState *spapr =3D SPAPR_MACHINE(xfb); XivePresenter *xptr =3D XIVE_PRESENTER(spapr->active_intc); XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); - int count; - - count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, cam_ig= nore, - priority, logic_serv, match); - if (count < 0) { - return count; - } =20 /* * When we implement the save and restore of the thread interrupt @@ -4493,12 +4486,14 @@ static int spapr_match_nvt(XiveFabric *xfb, uint8_t= format, * Until this is done, the sPAPR machine should find at least one * matching context always. */ - if (count =3D=3D 0) { + if (!xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, cam_ignore, + priority, logic_serv, match)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\= n", nvt_blk, nvt_idx); + return false; } =20 - return count; + return true; } =20 int spapr_get_vcpu_id(PowerPCCPU *cpu) --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=yDXV9JEqd2YGulb9ZztH7aN7aI/DnHYJgwb9sf9N20o=; b=CuYwLsScJCNQhE5VmoFzE/WDEJbO4Ngf6DrHSlSUEpyPw7Nt6yaUoVHSAvOOjbhBjTIqSh q1cyPj1R4mMqwt1mE2Z+SKjA+MiUJNA+szho6gsCNdRGEdDkPwJ+3ScK6LbrNY1zxrzvBs 8su1WCRwXlrhD1nlQX542Hzuq2O9jhc= X-MC-Unique: zhr1gl49MV-68yB-N4hrTw-1 X-Mimecast-MFC-AGG-ID: zhr1gl49MV-68yB-N4hrTw_1753115040 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 29/50] ppc/xive2: Redistribute group interrupt preempted by higher priority interrupt Date: Mon, 21 Jul 2025 18:22:12 +0200 Message-ID: <20250721162233.686837-30-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115208314116600 From: Nicholas Piggin A group interrupt that gets preempted by a higher priority interrupt delivery must be redistributed otherwise it would get lost. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-30-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 602b23d06d80..f51fd38a13eb 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1638,11 +1638,21 @@ static void xive2_router_end_notify(Xive2Router *xr= tr, uint8_t end_blk, crowd, cam_ignore, priority, xive_get_field32(END2_W7_F1_LOG_SERVER_ID, en= d.w7), &match)) { + XiveTCTX *tctx =3D match.tctx; + uint8_t ring =3D match.ring; + uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS= : ring; + uint8_t *aregs =3D &tctx->regs[alt_ring]; + uint8_t nsr =3D aregs[TM_NSR]; uint8_t group_level; =20 + if (priority < aregs[TM_PIPR] && + xive_nsr_indicates_group_exception(alt_ring, nsr)) { + xive2_redistribute(xrtr, tctx, alt_ring); + } + group_level =3D xive_get_group_level(crowd, cam_ignore, nvx_blk, n= vx_idx); - trace_xive_presenter_notify(nvx_blk, nvx_idx, match.ring, group_le= vel); - xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve= l); + trace_xive_presenter_notify(nvx_blk, nvx_idx, ring, group_level); + xive_tctx_pipr_update(tctx, ring, priority, group_level); return; } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; 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bh=nRPLzTi4AJ7cGYGwB/7WBfR4QyoS/tNGoVdjmVxWpzk=; b=RqohfKuGFqPs6t8RqsYRxbleIAwSbyh08hpnYCV31NWAj1gskQN5k+0uJJSwbdOyErix8m utHkS9mDoKL1/PcuYY9+9UDNr0kEB0l6OSw+tFvVZRm7ZhJ5jdTcFxn6M9pxAZqCjfPMiS kWciMXpemvG4Dm4vm8U3iTc9rooR+a0= X-MC-Unique: QnCfZ6pyOY2Lm32Tr4vuyw-1 X-Mimecast-MFC-AGG-ID: QnCfZ6pyOY2Lm32Tr4vuyw_1753115043 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 30/50] ppc/xive: Add xive_tctx_pipr_present() to present new interrupt Date: Mon, 21 Jul 2025 18:22:13 +0200 Message-ID: <20250721162233.686837-31-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115327522116600 From: Nicholas Piggin xive_tctx_pipr_update() is used for multiple things. In an effort to make things simpler and less overloaded, split out the function that is used to present a new interrupt to the tctx. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-31-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 2 ++ hw/intc/xive.c | 8 +++++++- hw/intc/xive2.c | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 8152a9df3d39..0d6b11e818c1 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -562,6 +562,8 @@ void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, uint8_t group_level); +void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, + uint8_t group_level); void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring); void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level); uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index c92e819053e8..038c35846d94 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -225,6 +225,12 @@ void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t rin= g, uint8_t priority, xive_tctx_notify(tctx, ring, group_level); } =20 +void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, + uint8_t group_level) +{ + xive_tctx_pipr_update(tctx, ring, priority, group_level); +} + /* * XIVE Thread Interrupt Management Area (TIMA) */ @@ -2040,7 +2046,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS= *eas) xive_get_field32(END_W7_F1_LOG_SERVER_ID, end= .w7), &match)) { trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, 0); - xive_tctx_pipr_update(match.tctx, match.ring, priority, 0); + xive_tctx_pipr_present(match.tctx, match.ring, priority, 0); return; } =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index f51fd38a13eb..fe40f7f07bdd 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1652,7 +1652,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, =20 group_level =3D xive_get_group_level(crowd, cam_ignore, nvx_blk, n= vx_idx); trace_xive_presenter_notify(nvx_blk, nvx_idx, ring, group_level); - xive_tctx_pipr_update(tctx, ring, priority, group_level); + xive_tctx_pipr_present(tctx, ring, priority, group_level); return; } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753116167; cv=none; d=zohomail.com; s=zohoarc; b=bkX8S8t+3FNM9CcvXKP6LTDfBVjSx4Yo2HV/7te1Tio455uCjTXj1jogQX6q6FjRQcFjcEtK+mzSzJKRmcH4Fgdq39umZ7+qxwqsy/YGNKu3K8WaoBs0BZkD68DfL1K2fOdQf3T9Snr8H2AOFNdKfgeiDDaNlQ28G6gfjaRNlx8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753116167; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 21 Jul 2025 16:24:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115053; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c5EInsA9TzgflXUCHGjdBwKqce/hjrYzL5PyDmrY3Aw=; b=EGbAmlFBsuluMHTlLydLObmiKweEY38gCx3iKGmV0RDHhh9g7k7WziXHmTjidGlqBmW1XN LBAAbNxKJL9cjGBKFhM5rtHmlIp6+4QL9W8Z1gIoksFpxy4DwnnxW7LQH6ZNRcE7loFoas tanxZGlSoAE4bD/j3QUrqzxIr25n+Y0= X-MC-Unique: GIwGHqdPPWCBg-Fml2p9uQ-1 X-Mimecast-MFC-AGG-ID: GIwGHqdPPWCBg-Fml2p9uQ_1753115046 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 31/50] ppc/xive: Fix high prio group interrupt being preempted by low prio VP Date: Mon, 21 Jul 2025 18:22:14 +0200 Message-ID: <20250721162233.686837-32-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116169511116600 From: Nicholas Piggin xive_tctx_pipr_present() as implemented with xive_tctx_pipr_update() causes VP-directed (group=3D=3D0) interrupt to be presented in PIPR and NSR despite being a lower priority than the currently presented group interrupt. This must not happen. The IPB bit should record the low priority VP interrupt, but PIPR and NSR must not present the lower priority interrupt. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-32-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 038c35846d94..7110cf45d74f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -228,7 +228,23 @@ void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t rin= g, uint8_t priority, void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, uint8_t group_level) { - xive_tctx_pipr_update(tctx, ring, priority, group_level); + /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ + uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; + uint8_t *aregs =3D &tctx->regs[alt_ring]; + uint8_t *regs =3D &tctx->regs[ring]; + uint8_t pipr =3D xive_priority_to_pipr(priority); + + if (group_level =3D=3D 0) { + regs[TM_IPB] |=3D xive_priority_to_ipb(priority); + if (pipr >=3D aregs[TM_PIPR]) { + /* VP interrupts can come here with lower priority than PIPR */ + return; + } + } + g_assert(pipr <=3D xive_ipb_to_pipr(regs[TM_IPB])); + g_assert(pipr < aregs[TM_PIPR]); + aregs[TM_PIPR] =3D pipr; + xive_tctx_notify(tctx, ring, group_level); } =20 /* --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115478; cv=none; d=zohomail.com; s=zohoarc; b=bTLNpUXDQuEjz7G7oNbjO0mhcTmCza64Fx73K4M85jepMO78mYTklFfnxqQpRq2Ju6ReQhyUvSISYbLKV/naTsg9jPI9OiOEiB3SfBUu3AcC5YjzCjsIcv+AsPcXT/BHHrEu61DvJVwwM8oIS7tlCjIiTSDx2/EPJG1Fb3+2MJw= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:24:09 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id CF052195608D; Mon, 21 Jul 2025 16:24:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115053; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bMh+LdQrAb64bov6H42Yd32t7AMR09/gX5XqffGEYdg=; b=bKgtcl+Q3sxikBWPNFdzdSJp5v27g/P0oVu5Ee8bfrgHe+68WO4AJD4UuWG91mMBlu9Tiw is5tpWC7rimJOxrACV5qu4DLkT1g4SLv33xCe+0EpMHjyDTBcNemfuWlWgtIw8AgpCqwA/ GwXEoTLZV0nOqohxL2T7SL+1i2l3gXc= X-MC-Unique: uYMmAyBROFy33agyJskrSA-1 X-Mimecast-MFC-AGG-ID: uYMmAyBROFy33agyJskrSA_1753115049 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 32/50] ppc/xive: Split xive recompute from IPB function Date: Mon, 21 Jul 2025 18:22:15 +0200 Message-ID: <20250721162233.686837-33-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115479507116600 From: Nicholas Piggin Further split xive_tctx_pipr_update() by splitting out a new function that is used to re-compute the PIPR from IPB. This is generally only used with XIVE1, because group interrputs require more logic. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-33-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 7110cf45d74f..5deb2f478fcb 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -225,6 +225,20 @@ void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t rin= g, uint8_t priority, xive_tctx_notify(tctx, ring, group_level); } =20 +static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring) +{ + /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ + uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; + uint8_t *aregs =3D &tctx->regs[alt_ring]; + uint8_t *regs =3D &tctx->regs[ring]; + + /* Does not support a presented group interrupt */ + g_assert(!xive_nsr_indicates_group_exception(alt_ring, aregs[TM_NSR])); + + aregs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); + xive_tctx_notify(tctx, ring, 0); +} + void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, uint8_t group_level) { @@ -517,7 +531,12 @@ static void xive_tm_set_os_lgs(XivePresenter *xptr, Xi= veTCTX *tctx, static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned= size) { - xive_tctx_pipr_update(tctx, TM_QW1_OS, value & 0xff, 0); + uint8_t ring =3D TM_QW1_OS; + uint8_t *regs =3D &tctx->regs[ring]; + + /* XXX: how should this work exactly? */ + regs[TM_IPB] |=3D xive_priority_to_ipb(value & 0xff); + xive_tctx_pipr_recompute_from_ipb(tctx, ring); } =20 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, @@ -601,14 +620,14 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, X= iveTCTX *tctx, } =20 /* - * Always call xive_tctx_pipr_update(). Even if there were no + * Always call xive_tctx_recompute_from_ipb(). Even if there were no * escalation triggered, there could be a pending interrupt which * was saved when the context was pulled and that we need to take * into account by recalculating the PIPR (which is not * saved/restored). * It will also raise the External interrupt signal if needed. */ - xive_tctx_pipr_update(tctx, TM_QW1_OS, 0xFF, 0); /* fxb */ + xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */ } =20 /* --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115111; cv=none; d=zohomail.com; s=zohoarc; b=AqOQtqknIQCRG4Wn0cYUDRc8En7MZ4z3c2dUJwvqL0pAck0td6gwsQfPp+09IapTkxplAWwqB3o9ZLI3qbzgcAxBCu5hhI/6ptmeHpUrrTdL88x+er019wWO4IpBUa2gK1pKLv4iPTB6YMFAAta+aTm0dEBWMaCWpb9zC9/Qtd0= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:24:11 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 815A3195608D; Mon, 21 Jul 2025 16:24:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115058; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CED5NJWqTOR25PdPo9U9RAFERqjNgZ7RNQmU3hpk4mI=; b=X0Jgg7E3LM1DusJYO22elm3VjvSWcE/0zeiV86+7p4TdoAIoZ9eYvwRs9/JMvcmOXKiZgX 4ASuSYic/65bMv078+vN9WUzHnbvIb3mylWLOu02sixcJKRgJnDEfull1DhDAPEh6Sbq4w JmW24H3+oZxyG7usSfRblHfidbbXLvY= X-MC-Unique: IMkCYTX-P5mOaPz1h1_iLQ-1 X-Mimecast-MFC-AGG-ID: IMkCYTX-P5mOaPz1h1_iLQ_1753115051 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 33/50] ppc/xive: tctx signaling registers rework Date: Mon, 21 Jul 2025 18:22:16 +0200 Message-ID: <20250721162233.686837-34-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115113110116600 From: Nicholas Piggin The tctx "signaling" registers (PIPR, CPPR, NSR) raise an interrupt on the target CPU thread. The POOL and PHYS rings both raise hypervisor interrupts, so they both share one set of signaling registers in the PHYS ring. The PHYS NSR register contains a field that indicates which ring has presented the interrupt being signaled to the CPU. This sharing results in all the "alt_regs" throughout the code. alt_regs is not very descriptive, and worse is that the name is used for conversions in both directions, i.e., to find the presenting ring from the signaling ring, and the signaling ring from the presenting ring. Instead of alt_regs, use the names sig_regs and sig_ring, and regs and ring for the presenting ring being worked on. Add a helper function to get the sign_regs, and add some asserts to ensure the POOL regs are never used to signal interrupts. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-34-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 26 +++++++++- hw/intc/xive.c | 112 ++++++++++++++++++++++-------------------- hw/intc/xive2.c | 94 ++++++++++++++++------------------- 3 files changed, 126 insertions(+), 106 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 0d6b11e818c1..a3c2f50ecef7 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -539,7 +539,7 @@ static inline uint8_t xive_ipb_to_pipr(uint8_t ibp) } =20 /* - * XIVE Thread Interrupt Management Aera (TIMA) + * XIVE Thread Interrupt Management Area (TIMA) * * This region gives access to the registers of the thread interrupt * management context. It is four page wide, each page providing a @@ -551,6 +551,30 @@ static inline uint8_t xive_ipb_to_pipr(uint8_t ibp) #define XIVE_TM_OS_PAGE 0x2 #define XIVE_TM_USER_PAGE 0x3 =20 +/* + * The TCTX (TIMA) has 4 rings (phys, pool, os, user), but only signals + * (raises an interrupt on) the CPU from 3 of them. Phys and pool both + * cause a hypervisor privileged interrupt so interrupts presented on + * those rings signal using the phys ring. This helper returns the signal + * regs from the given ring. + */ +static inline uint8_t *xive_tctx_signal_regs(XiveTCTX *tctx, uint8_t ring) +{ + /* + * This is a good point to add invariants to ensure nothing has tried = to + * signal using the POOL ring. + */ + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] =3D=3D 0); + + if (ring =3D=3D TM_QW2_HV_POOL) { + /* POOL and PHYS rings share the signal regs (PIPR, NSR, CPPR) */ + ring =3D TM_QW3_HV_PHYS; + } + return &tctx->regs[ring]; +} + void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr off= set, diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5deb2f478fcb..119a178f2e23 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -80,69 +80,77 @@ static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_= t ring) } } =20 -uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) +/* + * interrupt is accepted on the presentation ring, for PHYS ring the NSR + * directs it to the PHYS or POOL rings. + */ +uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) { - uint8_t *regs =3D &tctx->regs[ring]; - uint8_t nsr =3D regs[TM_NSR]; + uint8_t *sig_regs =3D &tctx->regs[sig_ring]; + uint8_t nsr =3D sig_regs[TM_NSR]; =20 - qemu_irq_lower(xive_tctx_output(tctx, ring)); + g_assert(sig_ring =3D=3D TM_QW1_OS || sig_ring =3D=3D TM_QW3_HV_PHYS); + + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] =3D=3D 0); + + qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); =20 - if (xive_nsr_indicates_exception(ring, nsr)) { - uint8_t cppr =3D regs[TM_PIPR]; - uint8_t alt_ring; - uint8_t *alt_regs; + if (xive_nsr_indicates_exception(sig_ring, nsr)) { + uint8_t cppr =3D sig_regs[TM_PIPR]; + uint8_t ring; + uint8_t *regs; =20 - alt_ring =3D xive_nsr_exception_ring(ring, nsr); - alt_regs =3D &tctx->regs[alt_ring]; + ring =3D xive_nsr_exception_ring(sig_ring, nsr); + regs =3D &tctx->regs[ring]; =20 - regs[TM_CPPR] =3D cppr; + sig_regs[TM_CPPR] =3D cppr; =20 /* * If the interrupt was for a specific VP, reset the pending * buffer bit, otherwise clear the logical server indicator */ - if (!xive_nsr_indicates_group_exception(ring, nsr)) { - alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); + if (!xive_nsr_indicates_group_exception(sig_ring, nsr)) { + regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); } =20 /* Clear the exception from NSR */ - regs[TM_NSR] =3D 0; + sig_regs[TM_NSR] =3D 0; =20 - trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, - alt_regs[TM_IPB], regs[TM_PIPR], - regs[TM_CPPR], regs[TM_NSR]); + trace_xive_tctx_accept(tctx->cs->cpu_index, ring, + regs[TM_IPB], sig_regs[TM_PIPR], + sig_regs[TM_CPPR], sig_regs[TM_NSR]); } =20 - return ((uint64_t)nsr << 8) | regs[TM_CPPR]; + return ((uint64_t)nsr << 8) | sig_regs[TM_CPPR]; } =20 void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level) { - /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ - uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; - uint8_t *alt_regs =3D &tctx->regs[alt_ring]; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; =20 - if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) { + if (sig_regs[TM_PIPR] < sig_regs[TM_CPPR]) { switch (ring) { case TM_QW1_OS: - regs[TM_NSR] =3D TM_QW1_NSR_EO | (group_level & 0x3F); + sig_regs[TM_NSR] =3D TM_QW1_NSR_EO | (group_level & 0x3F); break; case TM_QW2_HV_POOL: - alt_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6) | (group_level = & 0x3F); + sig_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6) | (group_level = & 0x3F); break; case TM_QW3_HV_PHYS: - regs[TM_NSR] =3D (TM_QW3_NSR_HE_PHYS << 6) | (group_level & 0x= 3F); + sig_regs[TM_NSR] =3D (TM_QW3_NSR_HE_PHYS << 6) | (group_level = & 0x3F); break; default: g_assert_not_reached(); } trace_xive_tctx_notify(tctx->cs->cpu_index, ring, - regs[TM_IPB], alt_regs[TM_PIPR], - alt_regs[TM_CPPR], alt_regs[TM_NSR]); + regs[TM_IPB], sig_regs[TM_PIPR], + sig_regs[TM_CPPR], sig_regs[TM_NSR]); qemu_irq_raise(xive_tctx_output(tctx, ring)); } else { - alt_regs[TM_NSR] =3D 0; + sig_regs[TM_NSR] =3D 0; qemu_irq_lower(xive_tctx_output(tctx, ring)); } } @@ -159,25 +167,32 @@ void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t r= ing) =20 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { - uint8_t *regs =3D &tctx->regs[ring]; + uint8_t *sig_regs =3D &tctx->regs[ring]; uint8_t pipr_min; uint8_t ring_min; =20 + g_assert(ring =3D=3D TM_QW1_OS || ring =3D=3D TM_QW3_HV_PHYS); + + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] =3D=3D 0); + + /* XXX: should show pool IPB for PHYS ring */ trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, - regs[TM_IPB], regs[TM_PIPR], - cppr, regs[TM_NSR]); + sig_regs[TM_IPB], sig_regs[TM_PIPR], + cppr, sig_regs[TM_NSR]); =20 if (cppr > XIVE_PRIORITY_MAX) { cppr =3D 0xff; } =20 - tctx->regs[ring + TM_CPPR] =3D cppr; + sig_regs[TM_CPPR] =3D cppr; =20 /* * Recompute the PIPR based on local pending interrupts. The PHYS * ring must take the minimum of both the PHYS and POOL PIPR values. */ - pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]); + pipr_min =3D xive_ipb_to_pipr(sig_regs[TM_IPB]); ring_min =3D ring; =20 /* PHYS updates also depend on POOL values */ @@ -186,7 +201,6 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t = ring, uint8_t cppr) =20 /* POOL values only matter if POOL ctx is valid */ if (pool_regs[TM_WORD2] & 0x80) { - uint8_t pool_pipr =3D xive_ipb_to_pipr(pool_regs[TM_IPB]); =20 /* @@ -200,7 +214,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t = ring, uint8_t cppr) } } =20 - regs[TM_PIPR] =3D pipr_min; + sig_regs[TM_PIPR] =3D pipr_min; =20 /* CPPR has changed, check if we need to raise a pending exception */ xive_tctx_notify(tctx, ring_min, 0); @@ -208,56 +222,50 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_= t ring, uint8_t cppr) =20 void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, uint8_t group_level) - { - /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ - uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; - uint8_t *alt_regs =3D &tctx->regs[alt_ring]; +{ + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; =20 if (group_level =3D=3D 0) { /* VP-specific */ regs[TM_IPB] |=3D xive_priority_to_ipb(priority); - alt_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); + sig_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); } else { /* VP-group */ - alt_regs[TM_PIPR] =3D xive_priority_to_pipr(priority); + sig_regs[TM_PIPR] =3D xive_priority_to_pipr(priority); } xive_tctx_notify(tctx, ring, group_level); } =20 static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring) { - /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ - uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; - uint8_t *aregs =3D &tctx->regs[alt_ring]; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; =20 /* Does not support a presented group interrupt */ - g_assert(!xive_nsr_indicates_group_exception(alt_ring, aregs[TM_NSR])); + g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR])); =20 - aregs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); + sig_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); xive_tctx_notify(tctx, ring, 0); } =20 void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, uint8_t group_level) { - /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ - uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; - uint8_t *aregs =3D &tctx->regs[alt_ring]; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; uint8_t pipr =3D xive_priority_to_pipr(priority); =20 if (group_level =3D=3D 0) { regs[TM_IPB] |=3D xive_priority_to_ipb(priority); - if (pipr >=3D aregs[TM_PIPR]) { + if (pipr >=3D sig_regs[TM_PIPR]) { /* VP interrupts can come here with lower priority than PIPR */ return; } } g_assert(pipr <=3D xive_ipb_to_pipr(regs[TM_IPB])); - g_assert(pipr < aregs[TM_PIPR]); - aregs[TM_PIPR] =3D pipr; + g_assert(pipr < sig_regs[TM_PIPR]); + sig_regs[TM_PIPR] =3D pipr; xive_tctx_notify(tctx, ring, group_level); } =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index fe40f7f07bdd..71b40f702a6f 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -606,11 +606,9 @@ static uint32_t xive2_tctx_hw_cam_line(XivePresenter *= xptr, XiveTCTX *tctx) =20 static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t = ring) { - uint8_t *regs =3D &tctx->regs[ring]; - uint8_t *alt_regs =3D (ring =3D=3D TM_QW2_HV_POOL) ? &tctx->regs[TM_QW= 3_HV_PHYS] : - regs; - uint8_t nsr =3D alt_regs[TM_NSR]; - uint8_t pipr =3D alt_regs[TM_PIPR]; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); + uint8_t nsr =3D sig_regs[TM_NSR]; + uint8_t pipr =3D sig_regs[TM_PIPR]; uint8_t crowd =3D NVx_CROWD_LVL(nsr); uint8_t group =3D NVx_GROUP_LVL(nsr); uint8_t nvgc_blk, end_blk, nvp_blk; @@ -618,19 +616,16 @@ static void xive2_redistribute(Xive2Router *xrtr, Xiv= eTCTX *tctx, uint8_t ring) Xive2Nvgc nvgc; uint8_t prio_limit; uint32_t cfg; - uint8_t alt_ring; =20 /* redistribution is only for group/crowd interrupts */ if (!xive_nsr_indicates_group_exception(ring, nsr)) { return; } =20 - alt_ring =3D xive_nsr_exception_ring(ring, nsr); - /* Don't check return code since ring is expected to be invalidated */ - xive2_tctx_get_nvp_indexes(tctx, alt_ring, &nvp_blk, &nvp_idx); + xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx); =20 - trace_xive_redistribute(tctx->cs->cpu_index, alt_ring, nvp_blk, nvp_id= x); + trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); =20 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); /* convert crowd/group to blk/idx */ @@ -675,23 +670,11 @@ static void xive2_redistribute(Xive2Router *xrtr, Xiv= eTCTX *tctx, uint8_t ring) xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); =20 /* clear interrupt indication for the context */ - alt_regs[TM_NSR] =3D 0; - alt_regs[TM_PIPR] =3D alt_regs[TM_CPPR]; + sig_regs[TM_NSR] =3D 0; + sig_regs[TM_PIPR] =3D sig_regs[TM_CPPR]; xive_tctx_reset_signal(tctx, ring); } =20 -static uint8_t xive2_hv_irq_ring(uint8_t nsr) -{ - switch (nsr >> 6) { - case TM_QW3_NSR_HE_POOL: - return TM_QW2_HV_POOL; - case TM_QW3_NSR_HE_PHYS: - return TM_QW3_HV_PHYS; - default: - return -1; - } -} - static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size, uint8_t ri= ng) { @@ -718,7 +701,8 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, = XiveTCTX *tctx, uint32_t ringw2 =3D xive_tctx_word2(&tctx->regs[cur_ring]); uint32_t ringw2_new =3D xive_set_field32(TM2_QW1W2_VO, ringw2, 0); bool is_valid =3D !!(xive_get_field32(TM2_QW1W2_VO, ringw2)); - uint8_t alt_ring; + uint8_t *sig_regs; + memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); =20 /* Skip the rest for USER or invalid contexts */ @@ -727,12 +711,11 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr= , XiveTCTX *tctx, } =20 /* Active group/crowd interrupts need to be redistributed */ - alt_ring =3D (cur_ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : c= ur_ring; - nsr =3D tctx->regs[alt_ring + TM_NSR]; - if (xive_nsr_indicates_group_exception(alt_ring, nsr)) { - /* For HV rings, only redistribute if cur_ring matches NSR */ - if ((cur_ring =3D=3D TM_QW1_OS) || - (cur_ring =3D=3D xive2_hv_irq_ring(nsr))) { + sig_regs =3D xive_tctx_signal_regs(tctx, ring); + nsr =3D sig_regs[TM_NSR]; + if (xive_nsr_indicates_group_exception(cur_ring, nsr)) { + /* Ensure ring matches NSR (for HV NSR POOL vs PHYS rings) */ + if (cur_ring =3D=3D xive_nsr_exception_ring(cur_ring, nsr)) { xive2_redistribute(xrtr, tctx, cur_ring); } } @@ -1118,7 +1101,7 @@ void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX= *tctx, /* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { - uint8_t *regs =3D &tctx->regs[ring]; + uint8_t *sig_regs =3D &tctx->regs[ring]; Xive2Router *xrtr =3D XIVE2_ROUTER(tctx->xptr); uint8_t old_cppr, backlog_prio, first_group, group_level; uint8_t pipr_min, lsmfb_min, ring_min; @@ -1127,33 +1110,41 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uin= t8_t ring, uint8_t cppr) uint32_t nvp_idx; Xive2Nvp nvp; int rc; - uint8_t nsr =3D regs[TM_NSR]; + uint8_t nsr =3D sig_regs[TM_NSR]; + + g_assert(ring =3D=3D TM_QW1_OS || ring =3D=3D TM_QW3_HV_PHYS); + + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] =3D=3D 0); =20 + /* XXX: should show pool IPB for PHYS ring */ trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, - regs[TM_IPB], regs[TM_PIPR], + sig_regs[TM_IPB], sig_regs[TM_PIPR], cppr, nsr); =20 if (cppr > XIVE_PRIORITY_MAX) { cppr =3D 0xff; } =20 - old_cppr =3D regs[TM_CPPR]; - regs[TM_CPPR] =3D cppr; + old_cppr =3D sig_regs[TM_CPPR]; + sig_regs[TM_CPPR] =3D cppr; =20 /* Handle increased CPPR priority (lower value) */ if (cppr < old_cppr) { - if (cppr <=3D regs[TM_PIPR]) { + if (cppr <=3D sig_regs[TM_PIPR]) { /* CPPR lowered below PIPR, must un-present interrupt */ if (xive_nsr_indicates_exception(ring, nsr)) { if (xive_nsr_indicates_group_exception(ring, nsr)) { /* redistribute precluded active grp interrupt */ - xive2_redistribute(xrtr, tctx, ring); + xive2_redistribute(xrtr, tctx, + xive_nsr_exception_ring(ring, nsr)); return; } } =20 /* interrupt is VP directed, pending in IPB */ - regs[TM_PIPR] =3D cppr; + sig_regs[TM_PIPR] =3D cppr; xive_tctx_notify(tctx, ring, 0); /* Ensure interrupt is cleare= d */ return; } else { @@ -1174,9 +1165,9 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8= _t ring, uint8_t cppr) * be adjusted below if needed in case of pending group interrupts. */ again: - pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]); - group_enabled =3D !!regs[TM_LGS]; - lsmfb_min =3D group_enabled ? regs[TM_LSMFB] : 0xff; + pipr_min =3D xive_ipb_to_pipr(sig_regs[TM_IPB]); + group_enabled =3D !!sig_regs[TM_LGS]; + lsmfb_min =3D group_enabled ? sig_regs[TM_LSMFB] : 0xff; ring_min =3D ring; group_level =3D 0; =20 @@ -1265,7 +1256,7 @@ again: } =20 /* PIPR should not be set to a value greater than CPPR */ - regs[TM_PIPR] =3D (pipr_min > cppr) ? cppr : pipr_min; + sig_regs[TM_PIPR] =3D (pipr_min > cppr) ? cppr : pipr_min; =20 /* CPPR has changed, check if we need to raise a pending exception */ xive_tctx_notify(tctx, ring_min, group_level); @@ -1490,9 +1481,7 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, X= iveTCTX *tctx, =20 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority) { - /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ - uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; - uint8_t *alt_regs =3D &tctx->regs[alt_ring]; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); =20 /* * The xive2_presenter_tctx_match() above tells if there's a match @@ -1500,7 +1489,7 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring,= uint8_t priority) * priority to know if the thread can take the interrupt now or if * it is precluded. */ - if (priority < alt_regs[TM_PIPR]) { + if (priority < sig_regs[TM_PIPR]) { return false; } return true; @@ -1640,14 +1629,13 @@ static void xive2_router_end_notify(Xive2Router *xr= tr, uint8_t end_blk, &match)) { XiveTCTX *tctx =3D match.tctx; uint8_t ring =3D match.ring; - uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS= : ring; - uint8_t *aregs =3D &tctx->regs[alt_ring]; - uint8_t nsr =3D aregs[TM_NSR]; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); + uint8_t nsr =3D sig_regs[TM_NSR]; uint8_t group_level; =20 - if (priority < aregs[TM_PIPR] && - xive_nsr_indicates_group_exception(alt_ring, nsr)) { - xive2_redistribute(xrtr, tctx, alt_ring); + if (priority < sig_regs[TM_PIPR] && + xive_nsr_indicates_group_exception(ring, nsr)) { + xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, n= sr)); } =20 group_level =3D xive_get_group_level(crowd, cam_ignore, nvx_blk, n= vx_idx); --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115300; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115303209116600 From: Nicholas Piggin The relationship between an interrupt signaled in the TIMA and the QEMU irq line to the processor to be 1:1, so they should be raised and lowered together and "just in case" lowering should be avoided (it could mask Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-35-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 119a178f2e23..db26dae7dbf4 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -95,8 +95,6 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_rin= g) g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] =3D=3D 0); g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] =3D=3D 0); =20 - qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); - if (xive_nsr_indicates_exception(sig_ring, nsr)) { uint8_t cppr =3D sig_regs[TM_PIPR]; uint8_t ring; @@ -117,6 +115,7 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_r= ing) =20 /* Clear the exception from NSR */ sig_regs[TM_NSR] =3D 0; + qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); =20 trace_xive_tctx_accept(tctx->cs->cpu_index, ring, regs[TM_IPB], sig_regs[TM_PIPR], --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115223; cv=none; d=zohomail.com; s=zohoarc; b=mmsc0MFUlpmNpyFVweo9eG1NzzZMnKJ+t8O8BL7CL//sAGm9GJ0gBELeRvryImQCqQGFvlSlLfA4a9VYJFXE5lIVO5nHWM0mRhjbWjZZJ2FmTd5siWcXt5IXvfgj8O25qcOl8UpWX4pOw8BVQbG7bg9Agaz/prue9F+DKcH0Qn0= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:24:17 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A0BA8195608D; Mon, 21 Jul 2025 16:24:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115064; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3aM5Ia520DaYoYHJUWxL34hd3Pcd0ra2BcSTJ2TP3Xo=; b=EbXglD3O34HVwQsDJaBieX9aNWQjSR6/SYnewxzZP97AQJ7DBZZiZB9eUKNIO8LFFbkDhR b534tf7KlrybJOOwed+p7TO+HcyozWsdgSvuQi2qWbs/QM6KixufvQ1CPooOIfaJq/FgWb g2ymib6nwS9WD0xTp+Ps+IVVZ3KPY6Q= X-MC-Unique: jAS_oAbbNnOeiF_v1JYO_Q-1 X-Mimecast-MFC-AGG-ID: jAS_oAbbNnOeiF_v1JYO_Q_1753115057 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 35/50] ppc/xive: Add xive_tctx_pipr_set() helper function Date: Mon, 21 Jul 2025 18:22:18 +0200 Message-ID: <20250721162233.686837-36-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115240679116600 From: Nicholas Piggin Have xive_tctx_notify() also set the new PIPR value and rename it to xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update() caller because it does not need to update IPB (it already sets it). Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-36-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 5 ++--- hw/intc/xive.c | 39 +++++++++++---------------------------- hw/intc/xive2.c | 16 +++++++--------- 3 files changed, 20 insertions(+), 40 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index a3c2f50ecef7..2372d1014bd2 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -584,12 +584,11 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, GString= *buf); Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); -void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, - uint8_t group_level); +void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t priority, + uint8_t group_level); void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, uint8_t group_level); void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring); -void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level); uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring); =20 /* diff --git a/hw/intc/xive.c b/hw/intc/xive.c index db26dae7dbf4..6ad84f93c77a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -125,12 +125,16 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig= _ring) return ((uint64_t)nsr << 8) | sig_regs[TM_CPPR]; } =20 -void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level) +/* Change PIPR and calculate NSR and irq based on PIPR, CPPR, group */ +void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t pipr, + uint8_t group_level) { uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; =20 - if (sig_regs[TM_PIPR] < sig_regs[TM_CPPR]) { + sig_regs[TM_PIPR] =3D pipr; + + if (pipr < sig_regs[TM_CPPR]) { switch (ring) { case TM_QW1_OS: sig_regs[TM_NSR] =3D TM_QW1_NSR_EO | (group_level & 0x3F); @@ -145,7 +149,7 @@ void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uin= t8_t group_level) g_assert_not_reached(); } trace_xive_tctx_notify(tctx->cs->cpu_index, ring, - regs[TM_IPB], sig_regs[TM_PIPR], + regs[TM_IPB], pipr, sig_regs[TM_CPPR], sig_regs[TM_NSR]); qemu_irq_raise(xive_tctx_output(tctx, ring)); } else { @@ -213,29 +217,10 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_= t ring, uint8_t cppr) } } =20 - sig_regs[TM_PIPR] =3D pipr_min; - - /* CPPR has changed, check if we need to raise a pending exception */ - xive_tctx_notify(tctx, ring_min, 0); + /* CPPR has changed, this may present or preclude a pending exception = */ + xive_tctx_pipr_set(tctx, ring_min, pipr_min, 0); } =20 -void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, - uint8_t group_level) -{ - uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); - uint8_t *regs =3D &tctx->regs[ring]; - - if (group_level =3D=3D 0) { - /* VP-specific */ - regs[TM_IPB] |=3D xive_priority_to_ipb(priority); - sig_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); - } else { - /* VP-group */ - sig_regs[TM_PIPR] =3D xive_priority_to_pipr(priority); - } - xive_tctx_notify(tctx, ring, group_level); - } - static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring) { uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); @@ -244,8 +229,7 @@ static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX = *tctx, uint8_t ring) /* Does not support a presented group interrupt */ g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR])); =20 - sig_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); - xive_tctx_notify(tctx, ring, 0); + xive_tctx_pipr_set(tctx, ring, xive_ipb_to_pipr(regs[TM_IPB]), 0); } =20 void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority, @@ -264,8 +248,7 @@ void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t rin= g, uint8_t priority, } g_assert(pipr <=3D xive_ipb_to_pipr(regs[TM_IPB])); g_assert(pipr < sig_regs[TM_PIPR]); - sig_regs[TM_PIPR] =3D pipr; - xive_tctx_notify(tctx, ring, group_level); + xive_tctx_pipr_set(tctx, ring, pipr, group_level); } =20 /* diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 71b40f702a6f..0ee50a6bca48 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -966,10 +966,10 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr,= XiveTCTX *tctx, } =20 /* - * Compute the PIPR based on the restored state. + * Set the PIPR/NSR based on the restored state. * It will raise the External interrupt signal if needed. */ - xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level); + xive_tctx_pipr_set(tctx, TM_QW1_OS, backlog_prio, backlog_level); } =20 /* @@ -1144,8 +1144,7 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8= _t ring, uint8_t cppr) } =20 /* interrupt is VP directed, pending in IPB */ - sig_regs[TM_PIPR] =3D cppr; - xive_tctx_notify(tctx, ring, 0); /* Ensure interrupt is cleare= d */ + xive_tctx_pipr_set(tctx, ring, cppr, 0); return; } else { /* CPPR was lowered, but still above PIPR. No action needed. */ @@ -1255,11 +1254,10 @@ again: pipr_min =3D backlog_prio; } =20 - /* PIPR should not be set to a value greater than CPPR */ - sig_regs[TM_PIPR] =3D (pipr_min > cppr) ? cppr : pipr_min; - - /* CPPR has changed, check if we need to raise a pending exception */ - xive_tctx_notify(tctx, ring_min, group_level); + if (pipr_min > cppr) { + pipr_min =3D cppr; + } + xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level); } =20 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753116167; cv=none; d=zohomail.com; s=zohoarc; b=EiFc2Ym49QSyYFEy1gzxnbSZtl5vgknwMvyncXCbwuxNKTJO8wsQ2ccrJZzc9wyVezQ7r0JxytO8tiDa4ZMBZ074Zld0lhhIipHrdxQP6onf7uJA9cuKhfAwrk3qmo/OmGU1EmFR8zLvJoPLbJUqw6mysjPlcUT2h1e3D1AFCko= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:24:20 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 234B2195608D; Mon, 21 Jul 2025 16:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115067; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=51nGWzogTVcmJa/tKMAynV/Y5esDhRuxUtEpzYN+gsc=; b=in0PmlvkOhfSCN/yUESzADnlXy1zhJzecf3kwXjfX4ECCZ6zBssaTBDrYxAeY+gytn2mVh UTn3IEgndqmzexPnCD6ItDdQ0riruSDOrstmTiFX8GNmz8/Z0YLvxV4MI5WlTZNUP25UcH sEtgrQLDs9NG8+1nuhC8XVe4s3IrgoA= X-MC-Unique: 9LMg1I0cO-ainuxnE6RB2g-1 X-Mimecast-MFC-AGG-ID: 9LMg1I0cO-ainuxnE6RB2g_1753115060 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 36/50] ppc/xive2: split tctx presentation processing from set CPPR Date: Mon, 21 Jul 2025 18:22:19 +0200 Message-ID: <20250721162233.686837-37-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116169683116601 From: Nicholas Piggin The second part of the set CPPR operation is to process (or re-present) any pending interrupts after CPPR is adjusted. Split this presentation processing out into a standalone function that can be used in other places. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-37-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 137 +++++++++++++++++++++++++++--------------------- 1 file changed, 76 insertions(+), 61 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 0ee50a6bca48..c7356c5b2fd8 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1098,66 +1098,19 @@ void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTC= TX *tctx, xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); } =20 -/* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ -static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) +/* Re-calculate and present pending interrupts */ +static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring) { - uint8_t *sig_regs =3D &tctx->regs[ring]; + uint8_t *sig_regs =3D &tctx->regs[sig_ring]; Xive2Router *xrtr =3D XIVE2_ROUTER(tctx->xptr); - uint8_t old_cppr, backlog_prio, first_group, group_level; + uint8_t backlog_prio, first_group, group_level; uint8_t pipr_min, lsmfb_min, ring_min; + uint8_t cppr =3D sig_regs[TM_CPPR]; bool group_enabled; - uint8_t nvp_blk; - uint32_t nvp_idx; Xive2Nvp nvp; int rc; - uint8_t nsr =3D sig_regs[TM_NSR]; - - g_assert(ring =3D=3D TM_QW1_OS || ring =3D=3D TM_QW3_HV_PHYS); - - g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] =3D=3D 0); - g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] =3D=3D 0); - g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] =3D=3D 0); - - /* XXX: should show pool IPB for PHYS ring */ - trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, - sig_regs[TM_IPB], sig_regs[TM_PIPR], - cppr, nsr); - - if (cppr > XIVE_PRIORITY_MAX) { - cppr =3D 0xff; - } - - old_cppr =3D sig_regs[TM_CPPR]; - sig_regs[TM_CPPR] =3D cppr; - - /* Handle increased CPPR priority (lower value) */ - if (cppr < old_cppr) { - if (cppr <=3D sig_regs[TM_PIPR]) { - /* CPPR lowered below PIPR, must un-present interrupt */ - if (xive_nsr_indicates_exception(ring, nsr)) { - if (xive_nsr_indicates_group_exception(ring, nsr)) { - /* redistribute precluded active grp interrupt */ - xive2_redistribute(xrtr, tctx, - xive_nsr_exception_ring(ring, nsr)); - return; - } - } =20 - /* interrupt is VP directed, pending in IPB */ - xive_tctx_pipr_set(tctx, ring, cppr, 0); - return; - } else { - /* CPPR was lowered, but still above PIPR. No action needed. */ - return; - } - } - - /* CPPR didn't change, nothing needs to be done */ - if (cppr =3D=3D old_cppr) { - return; - } - - /* CPPR priority decreased (higher value) */ + g_assert(sig_ring =3D=3D TM_QW3_HV_PHYS || sig_ring =3D=3D TM_QW1_OS); =20 /* * Recompute the PIPR based on local pending interrupts. It will @@ -1167,11 +1120,11 @@ again: pipr_min =3D xive_ipb_to_pipr(sig_regs[TM_IPB]); group_enabled =3D !!sig_regs[TM_LGS]; lsmfb_min =3D group_enabled ? sig_regs[TM_LSMFB] : 0xff; - ring_min =3D ring; + ring_min =3D sig_ring; group_level =3D 0; =20 /* PHYS updates also depend on POOL values */ - if (ring =3D=3D TM_QW3_HV_PHYS) { + if (sig_ring =3D=3D TM_QW3_HV_PHYS) { uint8_t *pool_regs =3D &tctx->regs[TM_QW2_HV_POOL]; =20 /* POOL values only matter if POOL ctx is valid */ @@ -1201,20 +1154,25 @@ again: } } =20 - rc =3D xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); - if (rc) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\= n"); - return; - } - if (group_enabled && lsmfb_min < cppr && lsmfb_min < pipr_min) { + + uint8_t nvp_blk; + uint32_t nvp_idx; + /* * Thread has seen a group interrupt with a higher priority * than the new cppr or pending local interrupt. Check the * backlog */ + rc =3D xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_i= dx); + if (rc) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid " + "context\n"); + return; + } + if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", nvp_blk, nvp_idx); @@ -1260,6 +1218,63 @@ again: xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level); } =20 +/* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ +static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t sig_ring, uint8_t = cppr) +{ + uint8_t *sig_regs =3D &tctx->regs[sig_ring]; + Xive2Router *xrtr =3D XIVE2_ROUTER(tctx->xptr); + uint8_t old_cppr; + uint8_t nsr =3D sig_regs[TM_NSR]; + + g_assert(sig_ring =3D=3D TM_QW1_OS || sig_ring =3D=3D TM_QW3_HV_PHYS); + + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] =3D=3D 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] =3D=3D 0); + + /* XXX: should show pool IPB for PHYS ring */ + trace_xive_tctx_set_cppr(tctx->cs->cpu_index, sig_ring, + sig_regs[TM_IPB], sig_regs[TM_PIPR], + cppr, nsr); + + if (cppr > XIVE_PRIORITY_MAX) { + cppr =3D 0xff; + } + + old_cppr =3D sig_regs[TM_CPPR]; + sig_regs[TM_CPPR] =3D cppr; + + /* Handle increased CPPR priority (lower value) */ + if (cppr < old_cppr) { + if (cppr <=3D sig_regs[TM_PIPR]) { + /* CPPR lowered below PIPR, must un-present interrupt */ + if (xive_nsr_indicates_exception(sig_ring, nsr)) { + if (xive_nsr_indicates_group_exception(sig_ring, nsr)) { + /* redistribute precluded active grp interrupt */ + xive2_redistribute(xrtr, tctx, + xive_nsr_exception_ring(sig_ring, n= sr)); + return; + } + } + + /* interrupt is VP directed, pending in IPB */ + xive_tctx_pipr_set(tctx, sig_ring, cppr, 0); + return; + } else { + /* CPPR was lowered, but still above PIPR. No action needed. */ + return; + } + } + + /* CPPR didn't change, nothing needs to be done */ + if (cppr =3D=3D old_cppr) { + return; + } + + /* CPPR priority decreased (higher value) */ + xive2_tctx_process_pending(tctx, sig_ring); +} + void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size) { --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115306; cv=none; d=zohomail.com; s=zohoarc; b=Jb5gNAR7RtOmBTdZZktRgCj4x3/5HEaP+1vdp7phjGHHiGOEOSDfwjAtCqf/2CjMM+zwkRFTGYONx8Nq+BjR8RMrXQ5rpufsVGmWVLo0vHqiAtD1rkJOofqZ2K9HSEsr1WEEuD00P55f4ZypXhkV48C/dFz0E3s0Om5GgrD5j8A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Mon, 21 Jul 2025 16:24:23 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 04E0D195608D; Mon, 21 Jul 2025 16:24:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115067; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n9PU1TINKvwzlVlW2Mxn7amCQ1BCtiAX2cpzPNc5w4s=; b=eY9ruN1BSyTNkZUfF0D71XLe6SU70PP9mqcgmobXnuatmpGXnAE3puz0QlWBw0C7AJeAzZ xRecV+/SEBDQPLlwe9vv3zc3PeKRjrkH/zyFK0ciU4z1ojtdFtjrr1tNlsPEFrqkY1YFrB fHjVrLBPDe3emovQhNPDGUaQUI776Go= X-MC-Unique: GVsQnynHM7SKXFlrri1u9Q-1 X-Mimecast-MFC-AGG-ID: GVsQnynHM7SKXFlrri1u9Q_1753115063 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 37/50] ppc/xive2: Consolidate presentation processing in context push Date: Mon, 21 Jul 2025 18:22:20 +0200 Message-ID: <20250721162233.686837-38-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115307319116600 From: Nicholas Piggin OS-push operation must re-present pending interrupts. Use the newly created xive2_tctx_process_pending() function instead of duplicating the logic. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-38-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 42 ++++++++++-------------------------------- 1 file changed, 10 insertions(+), 32 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index c7356c5b2fd8..be945bef1c53 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -903,18 +903,14 @@ static uint8_t xive2_tctx_restore_os_ctx(Xive2Router = *xrtr, XiveTCTX *tctx, return cppr; } =20 +static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring); + static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { - XivePresenter *xptr =3D XIVE_PRESENTER(xrtr); - uint8_t ipb; - uint8_t backlog_level; - uint8_t group_level; - uint8_t first_group; - uint8_t backlog_prio; - uint8_t group_prio; uint8_t *regs =3D &tctx->regs[TM_QW1_OS]; + uint8_t ipb; Xive2Nvp nvp; =20 /* @@ -946,30 +942,8 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, = XiveTCTX *tctx, } /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |=3D ipb; - backlog_prio =3D xive_ipb_to_pipr(regs[TM_IPB]); - backlog_level =3D 0; - - first_group =3D xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); - if (first_group && regs[TM_LSMFB] < backlog_prio) { - group_prio =3D xive2_presenter_backlog_scan(xptr, nvp_blk, nvp_idx, - first_group, &group_leve= l); - regs[TM_LSMFB] =3D group_prio; - if (regs[TM_LGS] && group_prio < backlog_prio && - group_prio < regs[TM_CPPR]) { - - /* VP can take a group interrupt */ - xive2_presenter_backlog_decr(xptr, nvp_blk, nvp_idx, - group_prio, group_level); - backlog_prio =3D group_prio; - backlog_level =3D group_level; - } - } =20 - /* - * Set the PIPR/NSR based on the restored state. - * It will raise the External interrupt signal if needed. - */ - xive_tctx_pipr_set(tctx, TM_QW1_OS, backlog_prio, backlog_level); + xive2_tctx_process_pending(tctx, TM_QW1_OS); } =20 /* @@ -1103,8 +1077,12 @@ static void xive2_tctx_process_pending(XiveTCTX *tct= x, uint8_t sig_ring) { uint8_t *sig_regs =3D &tctx->regs[sig_ring]; Xive2Router *xrtr =3D XIVE2_ROUTER(tctx->xptr); - uint8_t backlog_prio, first_group, group_level; - uint8_t pipr_min, lsmfb_min, ring_min; + uint8_t backlog_prio; + uint8_t first_group; + uint8_t group_level; + uint8_t pipr_min; + uint8_t lsmfb_min; + uint8_t ring_min; uint8_t cppr =3D sig_regs[TM_CPPR]; bool group_enabled; Xive2Nvp nvp; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753116167; cv=none; d=zohomail.com; s=zohoarc; b=m7zmQ28ZT8FI5uOhesrb1B9XKuakR0nXDKUe3ZgVmcc2roVHNoKx0GjLf8biTvKp8dl17u8ZyFNcbm/FLqWJ07x3moPlBhP10Vynbmq3ux3RwpW6JAI/UUDsvONXaWjIwTc4/0zt0Gfp298rkrl4UmhDXToPJXnkOGx2T7x3QzY= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:24:25 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id AC8CD195608D; Mon, 21 Jul 2025 16:24:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115070; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JCIcRY3FjrsxztCxjDU551LRjYmvTa0oL9B8vX2Hcqw=; b=FKexU2+RnfdC9Kw0HEatzwv+EHvIOU2rlGNvsQ4ZVo9EGkHNteHknTGDPuyS1KwuHCU12L I+tq05XKqA8uYMfayW5moPiLinDWasqzFT3jLctbnfTnP0//EO0ilhfU7FU7R/XlmbDSy+ o0amsypzaWvC/JULC1b3FAw1FQwImg0= X-MC-Unique: dtjntCmqNTK5_E-0B8laVA-1 X-Mimecast-MFC-AGG-ID: dtjntCmqNTK5_E-0B8laVA_1753115066 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 38/50] ppc/xive2: Avoid needless interrupt re-check on CPPR set Date: Mon, 21 Jul 2025 18:22:21 +0200 Message-ID: <20250721162233.686837-39-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116169489116600 From: Nicholas Piggin When CPPR priority is decreased, pending interrupts do not need to be re-checked if one is already presented because by definition that will be the highest priority. This prevents a presented group interrupt from being lost. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-39-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index be945bef1c53..531e6517baa2 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1250,7 +1250,9 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8= _t sig_ring, uint8_t cppr) } =20 /* CPPR priority decreased (higher value) */ - xive2_tctx_process_pending(tctx, sig_ring); + if (!xive_nsr_indicates_exception(sig_ring, nsr)) { + xive2_tctx_process_pending(tctx, sig_ring); + } } =20 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=TCOtOvaTo9mRtczsKrEZhGgH5genHn2pQrBIAPGQpOQ=; b=NG06ujp5IH/PalX0rlotBhVQpPZhex6PL6dXWw5wBa+2DYe9dgirzS7hpgZbBDhrWS52JF wAjk37W+mPR0E9+5KEoBgUY6U5GRya3fpYxeGHV3p/UGC0Ir4SubgT5wu1H8QYB87U1TOX 3VwlLl7MDylnbdu9iYpqnj5iLaBnCLI= X-MC-Unique: v6mMSM46PUit0EERO7hnLQ-1 X-Mimecast-MFC-AGG-ID: v6mMSM46PUit0EERO7hnLQ_1753115068 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 39/50] ppc/xive: Assert group interrupts were redistributed Date: Mon, 21 Jul 2025 18:22:22 +0200 Message-ID: <20250721162233.686837-40-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115303241116600 From: Nicholas Piggin Add some assertions to try to ensure presented group interrupts do not get lost without being redistributed, if they become precluded by CPPR or preempted by a higher priority interrupt. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-40-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 2 ++ hw/intc/xive2.c | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 6ad84f93c77a..d609d552e89e 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -132,6 +132,8 @@ void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, u= int8_t pipr, uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; =20 + g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR])); + sig_regs[TM_PIPR] =3D pipr; =20 if (pipr < sig_regs[TM_CPPR]) { diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 531e6517baa2..a0a6b1a88179 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1089,6 +1089,7 @@ static void xive2_tctx_process_pending(XiveTCTX *tctx= , uint8_t sig_ring) int rc; =20 g_assert(sig_ring =3D=3D TM_QW3_HV_PHYS || sig_ring =3D=3D TM_QW1_OS); + g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR= ])); =20 /* * Recompute the PIPR based on local pending interrupts. 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115074; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f9zwT7ZGhqGYHNUIdjiGru3IcNqxqD9iWpzeEHAQh+g=; b=NoP9NOooeDULkDhiiAyzSWreb8/WbrkAzEn/dWennvUc3D1tqBWJPLW0FT6oi5m6Z0fl+3 EEz42R8lOUVjAUPXEJtAIgYy/v8GOl8rPVRfkFoK2fT8B//DDTVWtzEhZ8x/NvP727+Sh1 EccblhsgMszrmjTDSoTg3zSJYiAVLH0= X-MC-Unique: pVO4pux2P6KyUOCu-rD2Lg-1 X-Mimecast-MFC-AGG-ID: pVO4pux2P6KyUOCu-rD2Lg_1753115071 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 40/50] ppc/xive2: implement NVP context save restore for POOL ring Date: Mon, 21 Jul 2025 18:22:23 +0200 Message-ID: <20250721162233.686837-41-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753116171722116600 From: Nicholas Piggin In preparation to implement POOL context push, add support for POOL NVP context save/restore. The NVP p bit is defined in the spec as follows: If TRUE, the CPPR of a Pool VP in the NVP is updated during store of the context with the CPPR of the Hard context it was running under. It's not clear whether non-pool VPs always or never get CPPR updated. Before this patch, OS contexts always save CPPR, so we will assume that is the behaviour. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-41-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2_regs.h | 1 + hw/intc/xive2.c | 51 +++++++++++++++++++++++++------------ 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index f82054661bda..2a3e60abadbf 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -158,6 +158,7 @@ typedef struct Xive2Nvp { #define NVP2_W0_L PPC_BIT32(8) #define NVP2_W0_G PPC_BIT32(9) #define NVP2_W0_T PPC_BIT32(10) +#define NVP2_W0_P PPC_BIT32(11) #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */ #define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31) uint32_t w1; diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index a0a6b1a88179..7631d4886206 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -512,12 +512,13 @@ static void xive2_presenter_backlog_decr(XivePresente= r *xptr, */ =20 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, - uint8_t nvp_blk, uint32_t nvp_idx, - uint8_t ring) + uint8_t ring, + uint8_t nvp_blk, uint32_t nvp_idx) { CPUPPCState *env =3D &POWERPC_CPU(tctx->cs)->env; uint32_t pir =3D env->spr_cb[SPR_PIR].default_value; Xive2Nvp nvp; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; =20 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { @@ -553,7 +554,14 @@ static void xive2_tctx_save_ctx(Xive2Router *xrtr, Xiv= eTCTX *tctx, } =20 nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); - nvp.w2 =3D xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); + + if ((nvp.w0 & NVP2_W0_P) || ring !=3D TM_QW2_HV_POOL) { + /* + * Non-pool contexts always save CPPR (ignore p bit). XXX: Clarify + * whether that is the correct behaviour. + */ + nvp.w2 =3D xive_set_field32(NVP2_W2_CPPR, nvp.w2, sig_regs[TM_CPPR= ]); + } if (nvp.w0 & NVP2_W0_L) { /* * Typically not used. If LSMFB is restored with 0, it will @@ -722,7 +730,7 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, = XiveTCTX *tctx, } =20 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { - xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring); + xive2_tctx_save_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx); } =20 /* @@ -863,12 +871,15 @@ void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, X= iveTCTX *tctx, xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); } =20 -static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, - uint8_t nvp_blk, uint32_t nvp_idx, - Xive2Nvp *nvp) +static uint8_t xive2_tctx_restore_ctx(Xive2Router *xrtr, XiveTCTX *tctx, + uint8_t ring, + uint8_t nvp_blk, uint32_t nvp_idx, + Xive2Nvp *nvp) { CPUPPCState *env =3D &POWERPC_CPU(tctx->cs)->env; uint32_t pir =3D env->spr_cb[SPR_PIR].default_value; + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); + uint8_t *regs =3D &tctx->regs[ring]; uint8_t cppr; =20 if (!xive2_nvp_is_hw(nvp)) { @@ -881,10 +892,10 @@ static uint8_t xive2_tctx_restore_os_ctx(Xive2Router = *xrtr, XiveTCTX *tctx, nvp->w2 =3D xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); =20 - tctx->regs[TM_QW1_OS + TM_CPPR] =3D cppr; - tctx->regs[TM_QW1_OS + TM_LSMFB] =3D xive_get_field32(NVP2_W2_LSMFB, n= vp->w2); - tctx->regs[TM_QW1_OS + TM_LGS] =3D xive_get_field32(NVP2_W2_LGS, nvp->= w2); - tctx->regs[TM_QW1_OS + TM_T] =3D xive_get_field32(NVP2_W2_T, nvp->w2); + sig_regs[TM_CPPR] =3D cppr; + regs[TM_LSMFB] =3D xive_get_field32(NVP2_W2_LSMFB, nvp->w2); + regs[TM_LGS] =3D xive_get_field32(NVP2_W2_LGS, nvp->w2); + regs[TM_T] =3D xive_get_field32(NVP2_W2_T, nvp->w2); =20 nvp->w1 =3D xive_set_field32(NVP2_W1_CO, nvp->w1, 1); nvp->w1 =3D xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); @@ -893,9 +904,18 @@ static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *= xrtr, XiveTCTX *tctx, /* * Checkout privilege: 0:OS, 1:Pool, 2:Hard * - * TODO: we only support OS push/pull + * TODO: we don't support hard push/pull */ - nvp->w1 =3D xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); + switch (ring) { + case TM_QW1_OS: + nvp->w1 =3D xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); + break; + case TM_QW2_HV_POOL: + nvp->w1 =3D xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 1); + break; + default: + g_assert_not_reached(); + } =20 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); =20 @@ -930,9 +950,8 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, X= iveTCTX *tctx, } =20 /* Automatically restore thread context registers */ - if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && - do_restore) { - xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); + if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_restor= e) { + xive2_tctx_restore_ctx(xrtr, tctx, TM_QW1_OS, nvp_blk, nvp_idx, &n= vp); } =20 ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2); --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=zmjY5Y9EZxT/2HeR0ihNtiWignYjkZ2TZhM04W0MAJQ=; b=X/7wS2znJmcYRxoIFCPhnG6/Jd+bvAzTm9ZKlTxWXNCxuIU0bR6i9Yydmv9lUQW9Eh8QGF 2jUiMAi0z9vsR/fkrTye7eS6zgY226hVxKopqCKkeyC8nCxTFg7d15GgYiRfzIMwvQEmwv k0dpNBtm3n1yPpELRpLx8zL7oYiqeq8= X-MC-Unique: B7IXq15fOFGaMtwFzCzDlQ-1 X-Mimecast-MFC-AGG-ID: B7IXq15fOFGaMtwFzCzDlQ_1753115074 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 41/50] ppc/xive2: Prevent pulling of pool context losing phys interrupt Date: Mon, 21 Jul 2025 18:22:24 +0200 Message-ID: <20250721162233.686837-42-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115681787116600 From: Nicholas Piggin When the pool context is pulled, the shared pool/phys signal is reset, which loses the qemu irq if a phys interrupt was presented. Only reset the signal if a poll irq was presented. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-42-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 7631d4886206..112397459afe 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -727,20 +727,22 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr= , XiveTCTX *tctx, xive2_redistribute(xrtr, tctx, cur_ring); } } + + /* + * Lower external interrupt line of requested ring and below excep= t for + * USER, which doesn't exist. + */ + if (xive_nsr_indicates_exception(cur_ring, nsr)) { + if (cur_ring =3D=3D xive_nsr_exception_ring(cur_ring, nsr)) { + xive_tctx_reset_signal(tctx, cur_ring); + } + } } =20 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { xive2_tctx_save_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx); } =20 - /* - * Lower external interrupt line of requested ring and below except for - * USER, which doesn't exist. - */ - for (cur_ring =3D TM_QW1_OS; cur_ring <=3D ring; - cur_ring +=3D XIVE_TM_RING_SIZE) { - xive_tctx_reset_signal(tctx, cur_ring); - } return target_ringw2; } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115577; cv=none; d=zohomail.com; s=zohoarc; b=OLpHHWAXdtzkyRyrOA9b3OqU6AIoOAlwFSDDVlnOCi5ZXSU94utqfpgiELM/+dmQg6oBujht7vQTRsNT5scOUJl1oE6w7N2JD1BEnfU0WF0Y1k2Jv6iPJt59wSvr09yFKix8PwPs/MIAdoBjH9a2p0MWGKahFPDSlsyDSR4UWDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753115577; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 21 Jul 2025 16:24:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4MofCW4WrhSQMxEwKn+6DDYjv8FRn8QpBov5/RmA4x8=; b=W+EquccD639dZdHt9bExA8G7RD1BQbC+SOGrbri1HixpIQrh8D94POhhOcxIHyHXiMcNOy GBoZ2DQLRy2WoHcu3+ZNzA4XvpTlizIHRWha35QAPYhYze9F/rkWKAw1m+tm3fp4I0bzSg ZQHz0p7dlnnnGwUFehQW8PdVI8EXbgg= X-MC-Unique: -p9Pk16LM0qIZmw-i9arGg-1 X-Mimecast-MFC-AGG-ID: -p9Pk16LM0qIZmw-i9arGg_1753115076 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 42/50] ppc/xive: Redistribute phys after pulling of pool context Date: Mon, 21 Jul 2025 18:22:25 +0200 Message-ID: <20250721162233.686837-43-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115579453116600 From: Nicholas Piggin After pulling the pool context, if a pool irq had been presented and was cleared in the process, there could be a pending irq in phys that should be presented. Process the phys irq ring after pulling pool ring to catch this case and avoid losing irqs. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-43-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 3 +++ hw/intc/xive2.c | 16 ++++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index d609d552e89e..50a38bbf2ef9 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -320,6 +320,9 @@ static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xp= tr, XiveTCTX *tctx, =20 xive_tctx_reset_signal(tctx, TM_QW1_OS); xive_tctx_reset_signal(tctx, TM_QW2_HV_POOL); + /* Re-check phys for interrupts if pool was disabled */ + xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW3_HV_PHYS); + return qw2w2; } =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 112397459afe..e3f9ff384a1a 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -683,6 +683,8 @@ static void xive2_redistribute(Xive2Router *xrtr, XiveT= CTX *tctx, uint8_t ring) xive_tctx_reset_signal(tctx, ring); } =20 +static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring); + static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size, uint8_t ri= ng) { @@ -739,6 +741,18 @@ static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr,= XiveTCTX *tctx, } } =20 + if (ring =3D=3D TM_QW2_HV_POOL) { + /* Re-check phys for interrupts if pool was disabled */ + nsr =3D tctx->regs[TM_QW3_HV_PHYS + TM_NSR]; + if (xive_nsr_indicates_exception(TM_QW3_HV_PHYS, nsr)) { + /* Ring must be PHYS because POOL would have been redistribute= d */ + g_assert(xive_nsr_exception_ring(TM_QW3_HV_PHYS, nsr) =3D=3D + TM_QW3_HV_PHYS); + } else { + xive2_tctx_process_pending(tctx, TM_QW3_HV_PHYS); + } + } + if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { xive2_tctx_save_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx); } @@ -925,8 +939,6 @@ static uint8_t xive2_tctx_restore_ctx(Xive2Router *xrtr= , XiveTCTX *tctx, return cppr; } =20 -static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring); 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Mon, 21 Jul 2025 16:24:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8QInPeFo3Ev22hIbUsAozyIHN3IzM2Yz7Z8Umcgpl2s=; b=ZTuqJlhV+JrcXn25pJpSDXtUjs9BFaf0vw1V5E2wS8TbjuTtFp0YWvg5+Mn4jL1EQsasuK 4EnyoGF1pKeMuKhFu9kDfYvyHt9d1onHwLoRsoxs+dLRdLUtj9CWE6dTe6SY90hm614AlQ LtSYJTzk5LLojMwwmNTru6mx0A5gp2g= X-MC-Unique: Kp-LSHdrNc-AzQ30At6UNQ-1 X-Mimecast-MFC-AGG-ID: Kp-LSHdrNc-AzQ30At6UNQ_1753115079 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 43/50] ppc/xive: Check TIMA operations validity Date: Mon, 21 Jul 2025 18:22:26 +0200 Message-ID: <20250721162233.686837-44-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115354018116600 From: Nicholas Piggin Certain TIMA operations should only be performed when a ring is valid, others when the ring is invalid, and they are considered undefined if used incorrectly. Add checks for this condition. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-44-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 1 + hw/intc/xive.c | 196 +++++++++++++++++++++++++----------------- 2 files changed, 116 insertions(+), 81 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 2372d1014bd2..b7ca8544e431 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -365,6 +365,7 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring) return *((uint32_t *) &ring[TM_WORD2]); } =20 +bool xive_ring_valid(XiveTCTX *tctx, uint8_t ring); bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr); bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr); uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 50a38bbf2ef9..6589c0a523c9 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -25,6 +25,19 @@ /* * XIVE Thread Interrupt Management context */ +bool xive_ring_valid(XiveTCTX *tctx, uint8_t ring) +{ + uint8_t cur_ring; + + for (cur_ring =3D ring; cur_ring <=3D TM_QW3_HV_PHYS; + cur_ring +=3D XIVE_TM_RING_SIZE) { + if (!(tctx->regs[cur_ring + TM_WORD2] & 0x80)) { + return false; + } + } + return true; +} + bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr) { switch (ring) { @@ -663,6 +676,8 @@ typedef struct XiveTmOp { uint8_t page_offset; uint32_t op_offset; unsigned size; + bool hw_ok; + bool sw_ok; void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); @@ -675,34 +690,34 @@ static const XiveTmOp xive_tm_operations[] =3D { * MMIOs below 2K : raw values and special operations without side * effects */ - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, - xive_tm_vt_poll }, + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, true, true, + xive_tm_set_os_cppr, NULL }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, true, true, + xive_tm_push_os_ctx, NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true, + xive_tm_set_hv_cppr, NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, false, true, + xive_tm_vt_push, NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true, + NULL, xive_tm_vt_poll }, =20 /* MMIOs above 2K : special operations with side effects */ - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, - xive_tm_ack_os_reg }, - { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pendin= g, - NULL }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, - xive_tm_pull_os_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, - xive_tm_pull_os_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, - xive_tm_ack_hv_reg }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, - xive_tm_pull_pool_ctx= }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, - xive_tm_pull_pool_ctx= }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, - xive_tm_pull_phys_ctx= }, + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false, + NULL, xive_tm_ack_os_reg }, + { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, true, false, + xive_tm_set_os_pending, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false, + NULL, xive_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, true, false, + NULL, xive_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, true, false, + NULL, xive_tm_ack_hv_reg }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, true, false, + NULL, xive_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, true, false, + NULL, xive_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, true, false, + NULL, xive_tm_pull_phys_ctx }, }; =20 static const XiveTmOp xive2_tm_operations[] =3D { @@ -710,52 +725,48 @@ static const XiveTmOp xive2_tm_operations[] =3D { * MMIOs below 2K : raw values and special operations without side * effects */ - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive2_tm_set_os_cppr, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, xive2_tm_push_os_ctx, - NULL }, - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive2_tm_set_hv_cppr, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, - NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, - xive_tm_vt_poll }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, xive2_tm_set_hv_targe= t, - NULL }, + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, true, true, + xive2_tm_set_os_cppr, NULL }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, true, true, + xive2_tm_push_os_ctx, NULL }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, true, true, + xive2_tm_push_os_ctx, NULL }, + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, true, true, + xive_tm_set_os_lgs, NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true, + xive2_tm_set_hv_cppr, NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true, + NULL, xive_tm_vt_poll }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, true, true, + xive2_tm_set_hv_target, NULL }, =20 /* MMIOs above 2K : special operations with side effects */ - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, - xive_tm_ack_os_reg }, - { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pendin= g, - NULL }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL, - xive2_tm_pull_os_ctx = }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, - xive2_tm_pull_os_ctx = }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, - xive2_tm_pull_os_ctx = }, - { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, - xive_tm_ack_hv_reg }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL, - xive2_tm_pull_pool_ct= x }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, - xive2_tm_pull_pool_ct= x }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, - xive2_tm_pull_pool_ct= x }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_= ol, - NULL }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL, - xive2_tm_pull_phys_ct= x }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, - xive2_tm_pull_phys_ct= x }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ct= x_ol, - NULL }, - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, xive2_tm_ack_os_el, - NULL }, + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false, + NULL, xive_tm_ack_os_reg }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, true, false, + NULL, xive2_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false, + NULL, xive2_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, true, false, + NULL, xive2_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, true, false, + NULL, xive_tm_ack_hv_reg }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, true, false, + NULL, xive2_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, true, false, + NULL, xive2_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, true, false, + NULL, xive2_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, true, false, + xive2_tm_pull_os_ctx_ol, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, true, false, + NULL, xive2_tm_pull_phys_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, true, false, + NULL, xive2_tm_pull_phys_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, true, false, + xive2_tm_pull_phys_ctx_ol, NULL }, + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, true, false, + xive2_tm_ack_os_el, NULL }, }; =20 static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, @@ -797,18 +808,28 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX= *tctx, hwaddr offset, uint64_t value, unsigned size) { const XiveTmOp *xto; + uint8_t ring =3D offset & TM_RING_OFFSET; + bool is_valid =3D xive_ring_valid(tctx, ring); + bool hw_owned =3D is_valid; =20 trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value); =20 - /* - * TODO: check V bit in Q[0-3]W2 - */ - /* * First, check for special operations in the 2K region */ + xto =3D xive_tm_find_op(tctx->xptr, offset, size, true); + if (xto) { + if (hw_owned && !xto->hw_ok) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to HW TI= MA " + "@%"HWADDR_PRIx" size %d\n", offset, size); + } + if (!hw_owned && !xto->sw_ok) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to SW TI= MA " + "@%"HWADDR_PRIx" size %d\n", offset, size); + } + } + if (offset & TM_SPECIAL_OP) { - xto =3D xive_tm_find_op(tctx->xptr, offset, size, true); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " "@%"HWADDR_PRIx" size %d\n", offset, size); @@ -821,7 +842,6 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *= tctx, hwaddr offset, /* * Then, for special operations in the region below 2K. */ - xto =3D xive_tm_find_op(tctx->xptr, offset, size, true); if (xto) { xto->write_handler(xptr, tctx, offset, value, size); return; @@ -830,6 +850,11 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX = *tctx, hwaddr offset, /* * Finish with raw access to the register values */ + if (hw_owned) { + /* Store context operations are dangerous when context is valid */ + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to HW TIMA " + "@%"HWADDR_PRIx" size %d\n", offset, size); + } xive_tm_raw_write(tctx, offset, value, size); } =20 @@ -837,17 +862,27 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveT= CTX *tctx, hwaddr offset, unsigned size) { const XiveTmOp *xto; + uint8_t ring =3D offset & TM_RING_OFFSET; + bool is_valid =3D xive_ring_valid(tctx, ring); + bool hw_owned =3D is_valid; uint64_t ret; =20 - /* - * TODO: check V bit in Q[0-3]W2 - */ + xto =3D xive_tm_find_op(tctx->xptr, offset, size, false); + if (xto) { + if (hw_owned && !xto->hw_ok) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined read to HW TIM= A " + "@%"HWADDR_PRIx" size %d\n", offset, size); + } + if (!hw_owned && !xto->sw_ok) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined read to SW TIM= A " + "@%"HWADDR_PRIx" size %d\n", offset, size); + } + } =20 /* * First, check for special operations in the 2K region */ if (offset & TM_SPECIAL_OP) { - xto =3D xive_tm_find_op(tctx->xptr, offset, size, false); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to T= IMA" "@%"HWADDR_PRIx" size %d\n", offset, size); @@ -860,7 +895,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCT= X *tctx, hwaddr offset, /* * Then, for special operations in the region below 2K. */ - xto =3D xive_tm_find_op(tctx->xptr, offset, size, false); if (xto) { ret =3D xto->read_handler(xptr, tctx, offset, size); goto out; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115551; cv=none; d=zohomail.com; s=zohoarc; b=CrHkPCn5hvwnCOAMlQZyBhiMURG22eBiNMV0wvHDAAgHmSwVY39g1ipXa6bgELFPlnplGGN+q2/SnLl3IzfK/cdGEdg/eOTDwuTNvNc+FRNY8ZVYy8/eoXBWPhneoBCXwpqYU6FQRB9/Qdk6F1IhIZuokD/CxfbNnUhIwk5elY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753115551; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 21 Jul 2025 16:24:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115086; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hW0qyVo7jA8jnnYQBeOKqk6U8QRqNlohALcXAO+SKzI=; b=Msr9ohR69yQtoSmCx0Krb+Z4Kvwy2zs/46KOHVO7wb1npaY8KdG2X/QezEfqiIzCIC+8nb 4YzQ/4LXFyjk6DuXoAVNMlklcbJ8307cWfNiRAp2uTQIyaC3eUNythBzTjhQXKk13v8lyX d4+t07RKYIG/4gS5F+ThRrHXOG9KBh8= X-MC-Unique: 5pJYRcK_PjyLT6FWtE5XvQ-1 X-Mimecast-MFC-AGG-ID: 5pJYRcK_PjyLT6FWtE5XvQ_1753115082 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 44/50] ppc/xive2: Implement pool context push TIMA op Date: Mon, 21 Jul 2025 18:22:27 +0200 Message-ID: <20250721162233.686837-45-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115552654116600 From: Nicholas Piggin Implement pool context push TIMA op. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-45-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2.h | 2 ++ hw/intc/xive.c | 4 ++++ hw/intc/xive2.c | 50 ++++++++++++++++++++++++++++-------------- 3 files changed, 39 insertions(+), 17 deletions(-) diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index a91b99057c2a..c1ab06a55adf 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -140,6 +140,8 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, u= int8_t priority); void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority); void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); +void xive2_tm_push_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 6589c0a523c9..e7f77be2f711 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -733,6 +733,10 @@ static const XiveTmOp xive2_tm_operations[] =3D { xive2_tm_push_os_ctx, NULL }, { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, true, true, xive_tm_set_os_lgs, NULL }, + { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_WORD2, 4, true, true, + xive2_tm_push_pool_ctx, NULL }, + { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_WORD2, 8, true, true, + xive2_tm_push_pool_ctx, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true, xive2_tm_set_hv_cppr, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index e3f9ff384a1a..4244e1d02b61 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -583,6 +583,7 @@ static void xive2_tctx_save_ctx(Xive2Router *xrtr, Xive= TCTX *tctx, xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); } =20 +/* POOL cam is the same as OS cam encoding */ static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, uint32_t *nvp_idx, bool *valid, bool *hw) { @@ -940,10 +941,11 @@ static uint8_t xive2_tctx_restore_ctx(Xive2Router *xr= tr, XiveTCTX *tctx, } =20 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, + uint8_t ring, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { - uint8_t *regs =3D &tctx->regs[TM_QW1_OS]; + uint8_t *regs =3D &tctx->regs[ring]; uint8_t ipb; Xive2Nvp nvp; =20 @@ -965,7 +967,7 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, X= iveTCTX *tctx, =20 /* Automatically restore thread context registers */ if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_restor= e) { - xive2_tctx_restore_ctx(xrtr, tctx, TM_QW1_OS, nvp_blk, nvp_idx, &n= vp); + xive2_tctx_restore_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx, &nvp); } =20 ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2); @@ -976,48 +978,62 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr,= XiveTCTX *tctx, /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |=3D ipb; =20 - xive2_tctx_process_pending(tctx, TM_QW1_OS); + xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? + TM_QW3_HV_PHYS : ring); } =20 /* - * Updating the OS CAM line can trigger a resend of interrupt + * Updating the ring CAM line can trigger a resend of interrupt */ -void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, - hwaddr offset, uint64_t value, unsigned size) +static void xive2_tm_push_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size, + uint8_t ring) { uint32_t cam; - uint32_t qw1w2; - uint64_t qw1dw1; + uint32_t w2; + uint64_t dw1; uint8_t nvp_blk; uint32_t nvp_idx; - bool vo; + bool v; bool do_restore; =20 /* First update the thead context */ switch (size) { case 4: cam =3D value; - qw1w2 =3D cpu_to_be32(cam); - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + w2 =3D cpu_to_be32(cam); + memcpy(&tctx->regs[ring + TM_WORD2], &w2, 4); break; case 8: cam =3D value >> 32; - qw1dw1 =3D cpu_to_be64(value); - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); + dw1 =3D cpu_to_be64(value); + memcpy(&tctx->regs[ring + TM_WORD2], &dw1, 8); break; default: g_assert_not_reached(); } =20 - xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); + xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &v, &do_restore); =20 /* Check the interrupt pending bits */ - if (vo) { - xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, - do_restore); + if (v) { + xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, ring, + nvp_blk, nvp_idx, do_restore); } } =20 +void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW1_OS); +} + +void xive2_tm_push_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW2_HV_POOL); +} + /* returns -1 if ring is invalid, but still populates block and index */ static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, uint8_t *nvp_blk, uint32_t *nvp_idx) --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7QN5VLHm8a0imbzsn30xkxBHwfO0cbV7O1xSvFfJiIA=; b=bOfwSDDwflLWDBCASxLkOfbUZ6YpesVmWNFN8f/XKQcQu2RBmGLabmgiMbRi1jId8RWwol 5u7MMMnmF7TNWJfghkdc1tdXmcr3DhI5zxBhkSWOB5qZBN8tT4/0AbaG6mbV/XoVc5feVE DB2Zbmu19zgaLMGBrvSiKCm5tt6uRvQ= X-MC-Unique: MH30Sm25OA2UkxaOBRGN_Q-1 X-Mimecast-MFC-AGG-ID: MH30Sm25OA2UkxaOBRGN_Q_1753115085 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 45/50] ppc/xive2: redistribute group interrupts on context push Date: Mon, 21 Jul 2025 18:22:28 +0200 Message-ID: <20250721162233.686837-46-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115303223116600 From: Nicholas Piggin When pushing a context, any presented group interrupt should be redistributed before processing pending interrupts to present highest priority. This can occur when pushing the POOL ring when the valid PHYS ring has a group interrupt presented, because they share signal registers. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-46-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 4244e1d02b61..23eb85bb8669 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -945,8 +945,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, X= iveTCTX *tctx, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; - uint8_t ipb; + uint8_t ipb, nsr =3D sig_regs[TM_NSR]; Xive2Nvp nvp; =20 /* @@ -978,6 +979,11 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, = XiveTCTX *tctx, /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |=3D ipb; =20 + if (xive_nsr_indicates_group_exception(ring, nsr)) { + /* redistribute precluded active grp interrupt */ + g_assert(ring =3D=3D TM_QW2_HV_POOL); /* PHYS ring has the grp int= errupt */ + xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); + } xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? TM_QW3_HV_PHYS : ring); } --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115312; cv=none; d=zohomail.com; s=zohoarc; b=O8lgD/+Z6eyD4LPvhXVXDwGvKK8RV9HvArfbOMfOYdCGQ/aOKZBHhbOiNPMxkxghbsiUxUY3cggrmkC1GBW0kS0DxOX2qKBccV1I1lZYuTYL1tJNj6rHIr0VdM+mF7ZRGrUTE5qWClI6NLYOvNxWjRzXI5XgD4gDT/8m3NbO2+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753115312; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UrJGQXX5MFfKsbXmSUtHx7gCvIlhY9yVcEfDM+YXcRQ=; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UrJGQXX5MFfKsbXmSUtHx7gCvIlhY9yVcEfDM+YXcRQ=; b=E48iuL1R5384jMVXk+z8zb9UbaRouxQmGVgZROaTBFK5K/8zqjskc7hi7N6k3FDLw6HrIQ vwZBCHBEx+2Gv5aFRQY9nihq0iBkYr3od0TVjiN1YKWYq19cMj/Vy4QmDHCl6FA+UquXnk KrqIPfn8hg/6eKmMTwiIeDu1BqI5Was= X-MC-Unique: Rxf2t915MFaR6vDyy0Z8ig-1 X-Mimecast-MFC-AGG-ID: Rxf2t915MFaR6vDyy0Z8ig_1753115087 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 46/50] ppc/xive2: Implement set_os_pending TIMA op Date: Mon, 21 Jul 2025 18:22:29 +0200 Message-ID: <20250721162233.686837-47-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115313424116600 From: Nicholas Piggin xive2 must take into account redistribution of group interrupts if the VP directed priority exceeds the group interrupt priority after this operation. The xive1 code is not group aware so implement this for xive2. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-47-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2.h | 2 ++ hw/intc/xive.c | 2 ++ hw/intc/xive2.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index c1ab06a55adf..45266c2a8b9e 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -130,6 +130,8 @@ void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX= *tctx, hwaddr offset, uint64_t value, unsigned size); void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); +void xive2_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offs= et, uint64_t value, unsigned size); uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, diff --git a/hw/intc/xive.c b/hw/intc/xive.c index e7f77be2f711..25cb3877cb15 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -747,6 +747,8 @@ static const XiveTmOp xive2_tm_operations[] =3D { /* MMIOs above 2K : special operations with side effects */ { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false, NULL, xive_tm_ack_os_reg }, + { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, true, false, + xive2_tm_set_os_pending, NULL }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, true, false, NULL, xive2_tm_pull_os_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 23eb85bb8669..f9eaea119289 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1323,6 +1323,34 @@ void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveT= CTX *tctx, xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); } =20 +/* + * Adjust the IPB to allow a CPU to process event queues of other + * priorities during one physical interrupt cycle. + */ +void xive2_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + Xive2Router *xrtr =3D XIVE2_ROUTER(xptr); + uint8_t ring =3D TM_QW1_OS; + uint8_t *regs =3D &tctx->regs[ring]; + uint8_t priority =3D value & 0xff; + + /* + * XXX: should this simply set a bit in IPB and wait for it to be pick= ed + * up next cycle, or is it supposed to present it now? We implement the + * latter here. + */ + regs[TM_IPB] |=3D xive_priority_to_ipb(priority); + if (xive_ipb_to_pipr(regs[TM_IPB]) >=3D regs[TM_PIPR]) { + return; + } + if (xive_nsr_indicates_group_exception(ring, regs[TM_NSR])) { + xive2_redistribute(xrtr, tctx, ring); + } + + xive_tctx_pipr_present(tctx, ring, priority, 0); +} + static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t ta= rget) { uint8_t *regs =3D &tctx->regs[ring]; --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115666; cv=none; d=zohomail.com; s=zohoarc; b=Gx4yHngz1mE0gjSHsoWSFBej7uUzqVVosN0kfqFq3LqRwEt4wAfr1nKgRrhTc8yYfUwirpa3cU9ZCGP/iebtKqFMuEiuR8d+aZDshM8f7ibLg5ETj8rEgsxQi6DjpxNHbiVM2batNQa0VfpH99jces0duHi4uXSJc8mRFHpeLks= ARC-Message-Signature: i=1; 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Mon, 21 Jul 2025 16:24:50 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.19]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0E2D819560AD; Mon, 21 Jul 2025 16:24:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115095; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C2ZgW8Ta/jYhhfoxR4Cj+5sB7PkbrWhpyHhu0+VJS0g=; b=R3YxL/Cd605cMTfMN38BEvhQ1KVKbRLeBP1MYZOf9cfPiuu4EmAfvftsB0VNmXfS5DxCuw V01uIU9+4BO0v0QqOtB5VIeBYOjyCG92b2NmS8Zr1PM/V1OaDaHTlPKyBZq6zpCaxHWLsh y6UGPJcovPvBUUCutiqiACpplH4F0a4= X-MC-Unique: yp_m8tYaOFeeQ_oQASwH6Q-1 X-Mimecast-MFC-AGG-ID: yp_m8tYaOFeeQ_oQASwH6Q_1753115090 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 47/50] ppc/xive2: Implement POOL LGS push TIMA op Date: Mon, 21 Jul 2025 18:22:30 +0200 Message-ID: <20250721162233.686837-48-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115667863116600 From: Nicholas Piggin Implement set LGS for the POOL ring. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-48-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 25cb3877cb15..725ba72b8f7a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -532,6 +532,12 @@ static void xive_tm_set_os_lgs(XivePresenter *xptr, Xi= veTCTX *tctx, xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); } =20 +static void xive_tm_set_pool_lgs(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive_tctx_set_lgs(tctx, TM_QW2_HV_POOL, value & 0xff); +} + /* * Adjust the PIPR to allow a CPU to process event queues of other * priorities during one physical interrupt cycle. @@ -737,6 +743,8 @@ static const XiveTmOp xive2_tm_operations[] =3D { xive2_tm_push_pool_ctx, NULL }, { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_WORD2, 8, true, true, xive2_tm_push_pool_ctx, NULL }, + { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_LGS, 1, true, true, + xive_tm_set_pool_lgs, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true, xive2_tm_set_hv_cppr, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true, --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115097; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tQkr5sirkIYVlkew3vz7iKEHM5VQk0+durPjB467nNs=; b=dG7AFvkshVLFItu4uvD4fA5b5qt0VwYs+i6hDcrJNHxTiMXwV/NSsPh1bpn9BdV0XhsEUt SZT+vWNe9Pk45NVLqNeDfV7+wB4+FcK4Qfsju9zzK68MSX/OjvY+0wEhhwJUrTvjGNTy3R oyW2VlqLHyqs1A+htNg06/w7oycmuBQ= X-MC-Unique: 3PUIgMrDOca6ZYSgcRrjGA-1 X-Mimecast-MFC-AGG-ID: 3PUIgMrDOca6ZYSgcRrjGA_1753115093 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 48/50] ppc/xive2: Implement PHYS ring VP push TIMA op Date: Mon, 21 Jul 2025 18:22:31 +0200 Message-ID: <20250721162233.686837-49-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115647728116600 From: Nicholas Piggin Implement the phys (aka hard) VP push. PowerVM uses this operation. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-49-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive2.h | 2 ++ hw/intc/xive.c | 2 ++ hw/intc/xive2.c | 11 +++++++++++ 3 files changed, 15 insertions(+) diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index 45266c2a8b9e..f4437e2c79a7 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -146,6 +146,8 @@ void xive2_tm_push_pool_ctx(XivePresenter *xptr, XiveTC= TX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive2_tm_push_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 725ba72b8f7a..8b7182fbb86c 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -747,6 +747,8 @@ static const XiveTmOp xive2_tm_operations[] =3D { xive_tm_set_pool_lgs, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true, xive2_tm_set_hv_cppr, NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, false, true, + xive2_tm_push_phys_ctx, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true, NULL, xive_tm_vt_poll }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, true, true, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index f9eaea119289..1b005687961a 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1005,6 +1005,11 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, X= iveTCTX *tctx, =20 /* First update the thead context */ switch (size) { + case 1: + tctx->regs[ring + TM_WORD2] =3D value & 0xff; + cam =3D xive2_tctx_hw_cam_line(xptr, tctx); + cam |=3D ((value & 0xc0) << 24); /* V and H bits */ + break; case 4: cam =3D value; w2 =3D cpu_to_be32(cam); @@ -1040,6 +1045,12 @@ void xive2_tm_push_pool_ctx(XivePresenter *xptr, Xiv= eTCTX *tctx, xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW2_HV_POOL); } =20 +void xive2_tm_push_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); +} + /* returns -1 if ring is invalid, but still populates block and index */ static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, uint8_t *nvp_blk, uint32_t *nvp_idx) --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=w2Ytn8gCoH4cLDg3wEy7JfoNBafewUw23FBIc8zPuso=; b=Hbqys87ujBoYUmFBVLAaK8Su8LKXfHo+bndcfrU6GTgQiC8MACUp/ox0s1jnLPHsEuEEtY YYkxSLrcFieP+tbpLG6Z8E62FhgPKZGnlBzJnIsCxZREG7HsfHl4W9oo5OO1UCJ1VewPM4 Rdp13jGygZ52jTZ7M5YB9fL9M4uFv9o= X-MC-Unique: JJ9-8hoiMAuQyMlU0a8-Uw-1 X-Mimecast-MFC-AGG-ID: JJ9-8hoiMAuQyMlU0a8-Uw_1753115095 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 49/50] ppc/xive: Split need_resend into restore_nvp Date: Mon, 21 Jul 2025 18:22:32 +0200 Message-ID: <20250721162233.686837-50-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115307397116600 From: Nicholas Piggin This is needed by the next patch which will re-send on all lower rings when pushing a context. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-50-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 24 ++++++++++++------------ hw/intc/xive2.c | 28 ++++++++++++++++------------ 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8b7182fbb86c..e0ffcf89ebff 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -606,7 +606,7 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr= , XiveTCTX *tctx, return qw1w2; } =20 -static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, +static void xive_tctx_restore_nvp(XiveRouter *xrtr, XiveTCTX *tctx, uint8_t nvt_blk, uint32_t nvt_idx) { XiveNVT nvt; @@ -632,16 +632,6 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, Xi= veTCTX *tctx, uint8_t *regs =3D &tctx->regs[TM_QW1_OS]; regs[TM_IPB] |=3D ipb; } - - /* - * Always call xive_tctx_recompute_from_ipb(). Even if there were no - * escalation triggered, there could be a pending interrupt which - * was saved when the context was pulled and that we need to take - * into account by recalculating the PIPR (which is not - * saved/restored). - * It will also raise the External interrupt signal if needed. - */ - xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */ } =20 /* @@ -663,7 +653,17 @@ static void xive_tm_push_os_ctx(XivePresenter *xptr, X= iveTCTX *tctx, =20 /* Check the interrupt pending bits */ if (vo) { - xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); + xive_tctx_restore_nvp(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); + + /* + * Always call xive_tctx_recompute_from_ipb(). Even if there were = no + * escalation triggered, there could be a pending interrupt which + * was saved when the context was pulled and that we need to take + * into account by recalculating the PIPR (which is not + * saved/restored). + * It will also raise the External interrupt signal if needed. + */ + xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */ } } =20 diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 1b005687961a..c3c6871e91b3 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -940,14 +940,14 @@ static uint8_t xive2_tctx_restore_ctx(Xive2Router *xr= tr, XiveTCTX *tctx, return cppr; } =20 -static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, +/* Restore TIMA VP context from NVP backlog */ +static void xive2_tctx_restore_nvp(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { - uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); uint8_t *regs =3D &tctx->regs[ring]; - uint8_t ipb, nsr =3D sig_regs[TM_NSR]; + uint8_t ipb; Xive2Nvp nvp; =20 /* @@ -978,14 +978,6 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, = XiveTCTX *tctx, } /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |=3D ipb; - - if (xive_nsr_indicates_group_exception(ring, nsr)) { - /* redistribute precluded active grp interrupt */ - g_assert(ring =3D=3D TM_QW2_HV_POOL); /* PHYS ring has the grp int= errupt */ - xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); - } - xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? - TM_QW3_HV_PHYS : ring); } =20 /* @@ -1028,8 +1020,20 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, X= iveTCTX *tctx, =20 /* Check the interrupt pending bits */ if (v) { - xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, ring, + Xive2Router *xrtr =3D XIVE2_ROUTER(xptr); + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); + uint8_t nsr =3D sig_regs[TM_NSR]; + + xive2_tctx_restore_nvp(xrtr, tctx, ring, nvp_blk, nvp_idx, do_restore); + + if (xive_nsr_indicates_group_exception(ring, nsr)) { + /* redistribute precluded active grp interrupt */ + g_assert(ring =3D=3D TM_QW2_HV_POOL); /* PHYS ring has the int= errupt */ + xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, n= sr)); + } + xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? + TM_QW3_HV_PHYS : ring); } } =20 --=20 2.50.1 From nobody Sat Nov 15 09:22:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1753115821; cv=none; d=zohomail.com; s=zohoarc; b=Zw9A8abR4TG5EgwXy0fBcS1CoVRdLkpihRzNAIdsGuhHQbuUQn0w7vH0MX6rfsJAbBxtCK26Rjzp0cuT+2QpBQoAbesXy341jPs5KfI+g+IGZZZt/Fj4Yjg2LHRTWka2WWwB/zUcBfXD+f0FbrIg7iLTKJsGffjEn/eyj1CfOLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1753115821; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 21 Jul 2025 16:24:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1753115103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MerIZeYs/yxx3RFuXDtsAm61y3WcL99CR/oPk6azoZ4=; b=AtNCRArk/T8dS0+nWpJnMsZPr6VkCjvXsCNACwctEejyt5QHx87sFEd3ll+d9ZXgUXFALE hyJPwr6qlutujlUa+T+SeIgy5fgJa2UJaOK2WV1L/ysEnBGW2hKbo+xIF21rDMJm7Q6eG1 VyDt+qGSFhD2l1DWZtkdxLsyXpFHzRM= X-MC-Unique: jvx65dfHMFqZpJgYhg-YYA-1 X-Mimecast-MFC-AGG-ID: jvx65dfHMFqZpJgYhg-YYA_1753115098 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Glenn Miles , Michael Kowal , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 50/50] ppc/xive2: Enable lower level contexts on VP push Date: Mon, 21 Jul 2025 18:22:33 +0200 Message-ID: <20250721162233.686837-51-clg@redhat.com> In-Reply-To: <20250721162233.686837-1-clg@redhat.com> References: <20250721162233.686837-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.926, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1753115827475116600 From: Nicholas Piggin When pushing a context, the lower-level context becomes valid if it had V=3D1, and so on. Iterate lower level contexts and send them pending interrupts if they become enabled. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-51-npiggin@g= mail.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive2.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index c3c6871e91b3..ee5fa2617849 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -995,6 +995,12 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, Xiv= eTCTX *tctx, bool v; bool do_restore; =20 + if (xive_ring_valid(tctx, ring)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Attempt to push VP to enable= d" + " ring 0x%02x\n", ring); + return; + } + /* First update the thead context */ switch (size) { case 1: @@ -1021,19 +1027,32 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, = XiveTCTX *tctx, /* Check the interrupt pending bits */ if (v) { Xive2Router *xrtr =3D XIVE2_ROUTER(xptr); - uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, ring); - uint8_t nsr =3D sig_regs[TM_NSR]; + uint8_t cur_ring; =20 xive2_tctx_restore_nvp(xrtr, tctx, ring, nvp_blk, nvp_idx, do_restore); =20 - if (xive_nsr_indicates_group_exception(ring, nsr)) { - /* redistribute precluded active grp interrupt */ - g_assert(ring =3D=3D TM_QW2_HV_POOL); /* PHYS ring has the int= errupt */ - xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, n= sr)); + for (cur_ring =3D TM_QW1_OS; cur_ring <=3D ring; + cur_ring +=3D XIVE_TM_RING_SIZE) { + uint8_t *sig_regs =3D xive_tctx_signal_regs(tctx, cur_ring); + uint8_t nsr =3D sig_regs[TM_NSR]; + + if (!xive_ring_valid(tctx, cur_ring)) { + continue; + } + + if (cur_ring =3D=3D TM_QW2_HV_POOL) { + if (xive_nsr_indicates_exception(cur_ring, nsr)) { + g_assert(xive_nsr_exception_ring(cur_ring, nsr) =3D=3D + TM_QW3_HV_P= HYS); + xive2_redistribute(xrtr, tctx, + xive_nsr_exception_ring(ring, nsr)); + } + xive2_tctx_process_pending(tctx, TM_QW3_HV_PHYS); + break; + } + xive2_tctx_process_pending(tctx, cur_ring); } - xive2_tctx_process_pending(tctx, ring =3D=3D TM_QW2_HV_POOL ? - TM_QW3_HV_PHYS : ring); } } =20 @@ -1159,6 +1178,7 @@ static void xive2_tctx_process_pending(XiveTCTX *tctx= , uint8_t sig_ring) int rc; =20 g_assert(sig_ring =3D=3D TM_QW3_HV_PHYS || sig_ring =3D=3D TM_QW1_OS); + g_assert(sig_regs[TM_WORD2] & 0x80); g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR= ])); =20 /* --=20 2.50.1