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However, we got the tx/rx register definitions wrong. These should be: AArch32: DBGDTRTX p14 0 c0 c5 0 (on writes) DBGDTRRX p14 0 c0 c5 0 (on reads) AArch64: DBGDTRTX_EL0 2 3 0 5 0 (on writes) DBGDTRRX_EL0 2 3 0 5 0 (on reads) DBGDTR_EL0 2 3 0 4 0 (reads and writes) where DBGDTRTX and DBGDTRRX are effectively different names for the same 32-bit register, which has tx behaviour on writes and rx behaviour on reads. The AArch64-only DBGDTR_EL0 is a 64-bit wide register whose top and bottom halves map to the DBGDTRRX and DBGDTRTX registers. Currently we have just one cpreg struct, which: * calls itself DBGDTR_EL0 * uses the DBGDTRTX_EL0/DBGDTRRX_EL0 encoding * is marked as ARM_CP_STATE_BOTH but has the wrong opc1 value for AArch32 * is implemented as RAZ/WI Correct the encoding so: * we name the DBGDTRTX/DBGDTRRX register correctly * we split it into AA64 and AA32 versions so we can get the AA32 encoding right * we implement DBGDTR_EL0 at its correct encoding Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2986 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250708141049.778361-1-peter.maydell@linaro.org --- target/arm/debug_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 69fb1d0d9ff..aee06d4d426 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -988,11 +988,20 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* DBGDTRTX_EL0/DBGDTRRX_EL0 depend on direction */ - { .name =3D "DBGDTR_EL0", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, + /* Architecturally DBGDTRTX is named DBGDTRRX when used for reads */ + { .name =3D "DBGDTRTX_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DBGDTRTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 14, + .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D access_tdcc, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* This is AArch64-only and is a combination of DBGDTRTX and DBGDTRRX = */ + { .name =3D "DBGDTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 4, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D access_tdcc, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * OSECCR_EL1 provides a mechanism for an operating system * to access the contents of EDECCR. EDECCR is not implemented though, --=20 2.43.0