From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824527737997.8364078985426; Fri, 18 Jul 2025 00:42:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfj8-0001mn-TR; Fri, 18 Jul 2025 03:41:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfWA-0002kP-Ck for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:34 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVz-0002iu-2o for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:30 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxjayK93lovcksAQ--.58686S3; Fri, 18 Jul 2025 15:28:10 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S3; Fri, 18 Jul 2025 15:28:10 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 1/9] target/loongarch: Move some function definition to kvm directory Date: Fri, 18 Jul 2025 15:27:59 +0800 Message-Id: <20250718072807.3585466-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824530688116600 Content-Type: text/plain; charset="utf-8" Move function definition specified with kvm to the corresponding directory. Also remove header file "cpu.h" including outside of macro QEMU_KVM_LOONGARCH_H. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 9 --------- target/loongarch/kvm/kvm_loongarch.h | 4 ++-- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index b15ada2078..31215b7785 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -46,6 +46,7 @@ #include "hw/block/flash.h" #include "hw/virtio/virtio-iommu.h" #include "qemu/error-report.h" +#include "kvm/kvm_loongarch.h" =20 static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 9538e8d61d..bbe6db33f1 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -496,13 +496,4 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) =20 void loongarch_cpu_post_init(Object *obj); =20 -#ifdef CONFIG_KVM -void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu); -#else -static inline void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu) -{ -} -#endif -void kvm_loongarch_init_irq_routing(void); - #endif /* LOONGARCH_CPU_H */ diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kv= m_loongarch.h index 1051a341ec..51475675d6 100644 --- a/target/loongarch/kvm/kvm_loongarch.h +++ b/target/loongarch/kvm/kvm_loongarch.h @@ -5,11 +5,11 @@ * Copyright (c) 2023 Loongson Technology Corporation Limited */ =20 -#include "cpu.h" - #ifndef QEMU_KVM_LOONGARCH_H #define QEMU_KVM_LOONGARCH_H =20 +void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu); +void kvm_loongarch_init_irq_routing(void); int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level); void kvm_arch_reset_vcpu(CPUState *cs); =20 --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824565126490.60361411582994; Fri, 18 Jul 2025 00:42:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfjZ-0002sF-IE; Fri, 18 Jul 2025 03:42:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW6-0002gk-5n for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:27 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVz-0002ig-2L for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxYa+K93lowMksAQ--.52692S3; Fri, 18 Jul 2025 15:28:10 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S4; Fri, 18 Jul 2025 15:28:10 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 2/9] target/loongarch: Define function loongarch_cpu_post_init as static Date: Fri, 18 Jul 2025 15:28:00 +0800 Message-Id: <20250718072807.3585466-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824566940116600 Content-Type: text/plain; charset="utf-8" Function loongarch_cpu_post_init() is implemented and used in the same file target/loongarch/cpu.c, it can be defined as static function. This patch moves implementation about function loongarch_cpu_post_init() before it is referenced. And it is only code movement, no function change. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 180 ++++++++++++++++++++--------------------- target/loongarch/cpu.h | 2 - 2 files changed, 90 insertions(+), 92 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..b96429ffb1 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -422,6 +422,96 @@ static void loongarch_la464_init_csr(Object *obj) #endif } =20 +static bool loongarch_get_lsx(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->lsx !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_lsx(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; + + cpu->lsx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + if (cpu->lsx =3D=3D ON_OFF_AUTO_OFF) { + cpu->lasx =3D ON_OFF_AUTO_OFF; + if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { + error_setg(errp, "Failed to disable LSX since LASX is enabled"= ); + return; + } + } + + if (kvm_enabled()) { + /* kvm feature detection in function kvm_arch_init_vcpu */ + return; + } + + /* LSX feature detection in TCG mode */ + val =3D cpu->env.cpucfg[2]; + if (cpu->lsx =3D=3D ON_OFF_AUTO_ON) { + if (FIELD_EX32(val, CPUCFG2, LSX) =3D=3D 0) { + error_setg(errp, "Failed to enable LSX in TCG mode"); + return; + } + } else { + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, 0); + val =3D cpu->env.cpucfg[2]; + } + + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LSX, value); +} + +static bool loongarch_get_lasx(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->lasx !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_lasx(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; + + cpu->lasx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + if ((cpu->lsx =3D=3D ON_OFF_AUTO_OFF) && (cpu->lasx =3D=3D ON_OFF_AUTO= _ON)) { + error_setg(errp, "Failed to enable LASX since lSX is disabled"); + return; + } + + if (kvm_enabled()) { + /* kvm feature detection in function kvm_arch_init_vcpu */ + return; + } + + /* LASX feature detection in TCG mode */ + val =3D cpu->env.cpucfg[2]; + if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { + if (FIELD_EX32(val, CPUCFG2, LASX) =3D=3D 0) { + error_setg(errp, "Failed to enable LASX in TCG mode"); + return; + } + } + + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); +} + +static void loongarch_cpu_post_init(Object *obj) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + + cpu->lbt =3D ON_OFF_AUTO_OFF; + cpu->pmu =3D ON_OFF_AUTO_OFF; + cpu->lsx =3D ON_OFF_AUTO_AUTO; + cpu->lasx =3D ON_OFF_AUTO_AUTO; + object_property_add_bool(obj, "lsx", loongarch_get_lsx, + loongarch_set_lsx); + object_property_add_bool(obj, "lasx", loongarch_get_lasx, + loongarch_set_lasx); + /* lbt is enabled only in kvm mode, not supported in tcg mode */ + if (kvm_enabled()) { + kvm_loongarch_cpu_post_init(cpu); + } +} + static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -683,96 +773,6 @@ static void loongarch_cpu_unrealizefn(DeviceState *dev) lacc->parent_unrealize(dev); } =20 -static bool loongarch_get_lsx(Object *obj, Error **errp) -{ - return LOONGARCH_CPU(obj)->lsx !=3D ON_OFF_AUTO_OFF; -} - -static void loongarch_set_lsx(Object *obj, bool value, Error **errp) -{ - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - uint32_t val; - - cpu->lsx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; - if (cpu->lsx =3D=3D ON_OFF_AUTO_OFF) { - cpu->lasx =3D ON_OFF_AUTO_OFF; - if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { - error_setg(errp, "Failed to disable LSX since LASX is enabled"= ); - return; - } - } - - if (kvm_enabled()) { - /* kvm feature detection in function kvm_arch_init_vcpu */ - return; - } - - /* LSX feature detection in TCG mode */ - val =3D cpu->env.cpucfg[2]; - if (cpu->lsx =3D=3D ON_OFF_AUTO_ON) { - if (FIELD_EX32(val, CPUCFG2, LSX) =3D=3D 0) { - error_setg(errp, "Failed to enable LSX in TCG mode"); - return; - } - } else { - cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, 0); - val =3D cpu->env.cpucfg[2]; - } - - cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LSX, value); -} - -static bool loongarch_get_lasx(Object *obj, Error **errp) -{ - return LOONGARCH_CPU(obj)->lasx !=3D ON_OFF_AUTO_OFF; -} - -static void loongarch_set_lasx(Object *obj, bool value, Error **errp) -{ - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - uint32_t val; - - cpu->lasx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; - if ((cpu->lsx =3D=3D ON_OFF_AUTO_OFF) && (cpu->lasx =3D=3D ON_OFF_AUTO= _ON)) { - error_setg(errp, "Failed to enable LASX since lSX is disabled"); - return; - } - - if (kvm_enabled()) { - /* kvm feature detection in function kvm_arch_init_vcpu */ - return; - } - - /* LASX feature detection in TCG mode */ - val =3D cpu->env.cpucfg[2]; - if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { - if (FIELD_EX32(val, CPUCFG2, LASX) =3D=3D 0) { - error_setg(errp, "Failed to enable LASX in TCG mode"); - return; - } - } - - cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); -} - -void loongarch_cpu_post_init(Object *obj) -{ - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - - cpu->lbt =3D ON_OFF_AUTO_OFF; - cpu->pmu =3D ON_OFF_AUTO_OFF; - cpu->lsx =3D ON_OFF_AUTO_AUTO; - cpu->lasx =3D ON_OFF_AUTO_AUTO; - object_property_add_bool(obj, "lsx", loongarch_get_lsx, - loongarch_set_lsx); - object_property_add_bool(obj, "lasx", loongarch_get_lasx, - loongarch_set_lasx); - /* lbt is enabled only in kvm mode, not supported in tcg mode */ - if (kvm_enabled()) { - kvm_loongarch_cpu_post_init(cpu); - } -} - static void loongarch_cpu_init(Object *obj) { #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index bbe6db33f1..7731f6acdc 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -494,6 +494,4 @@ static inline void set_pc(CPULoongArchState *env, uint6= 4_t value) =20 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU =20 -void loongarch_cpu_post_init(Object *obj); - #endif /* LOONGARCH_CPU_H */ --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824513726562.7374377115369; Fri, 18 Jul 2025 00:41:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfj0-0001SD-Ln; Fri, 18 Jul 2025 03:41:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW4-0002dj-EZ for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVy-0002ii-Mr for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:24 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxIK+K93lowsksAQ--.24114S3; Fri, 18 Jul 2025 15:28:10 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S5; Fri, 18 Jul 2025 15:28:10 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 3/9] target/loongarch: Set page size in TLB misc with STLB Date: Fri, 18 Jul 2025 15:28:01 +0800 Message-Id: <20250718072807.3585466-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824517360116600 Content-Type: text/plain; charset="utf-8" With VTLB different TLB entry may have different page size, and page size is set in PS field of TLB misc. However with STLB, all the TLB entries have the same page size, page size comes from register CSR_STLBPS, PS field of TLB misc is not used. Here PS field of TLB misc is used with all TLB entries, even with STLB, it is convenient with TLB maintainance operation. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 41 ++++++++----------------------- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 8872593ff0..3ea0e153b1 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -110,11 +110,8 @@ static void invalidate_tlb_entry(CPULoongArchState *en= v, int index) if (!tlb_e) { return; } - if (index >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); pagesize =3D MAKE_64BIT_MASK(tlb_ps, 1); mask =3D MAKE_64BIT_MASK(0, tlb_ps + 1); =20 @@ -173,11 +170,8 @@ static void fill_tlb_entry(CPULoongArchState *env, int= index) lo1 =3D env->CSR_TLBELO1; } =20 - /* Only MTLB has the ps fields */ - if (index >=3D LOONGARCH_STLB) { - tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); - } - + /* Store page size in field PS */ + tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); @@ -283,12 +277,7 @@ void helper_tlbrd(CPULoongArchState *env) =20 index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); tlb =3D &env->tlb[index]; - - if (index >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); =20 if (!tlb_e) { @@ -476,11 +465,8 @@ void helper_invtlb_page_asid(CPULoongArchState *env, t= arget_ulong info, if (!tlb_e) { continue; } - if (i >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); vpn =3D (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1); compare_shift =3D tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; @@ -509,11 +495,8 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *e= nv, if (!tlb_e) { continue; } - if (i >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); vpn =3D (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1); compare_shift =3D tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; @@ -673,11 +656,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *= env, hwaddr *physical, uint64_t tlb_entry, tlb_ppn; uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; =20 - if (index >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); n =3D (address >> tlb_ps) & 0x1;/* Odd or even */ =20 tlb_entry =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824613618554.7813803281698; Fri, 18 Jul 2025 00:43:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfje-0003Il-84; Fri, 18 Jul 2025 03:42:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW4-0002dY-66 for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVz-0002j8-1z for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:23 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxLHKL93loxcksAQ--.57691S3; Fri, 18 Jul 2025 15:28:11 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S6; Fri, 18 Jul 2025 15:28:10 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 4/9] target/loongarch: Add header file cpu-mmu.h Date: Fri, 18 Jul 2025 15:28:02 +0800 Message-Id: <20250718072807.3585466-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824615437116600 Content-Type: text/plain; charset="utf-8" New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 30 ++++++++++++++++++++++++++++++ target/loongarch/cpu.c | 1 + target/loongarch/cpu_helper.c | 1 + target/loongarch/internals.h | 20 -------------------- target/loongarch/tcg/csr_helper.c | 1 + target/loongarch/tcg/tlb_helper.c | 1 + 6 files changed, 34 insertions(+), 20 deletions(-) create mode 100644 target/loongarch/cpu-mmu.h diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h new file mode 100644 index 0000000000..4c5cbd7425 --- /dev/null +++ b/target/loongarch/cpu-mmu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch CPU parameters for QEMU. + * + * Copyright (c) 2025 Loongson Technology Corporation Limited + */ + +#ifndef LOONGARCH_CPU_MMU_H +#define LOONGARCH_CPU_MMU_H + +enum { + TLBRET_MATCH =3D 0, + TLBRET_BADADDR =3D 1, + TLBRET_NOMATCH =3D 2, + TLBRET_INVALID =3D 3, + TLBRET_DIRTY =3D 4, + TLBRET_RI =3D 5, + TLBRET_XI =3D 6, + TLBRET_PE =3D 7, +}; + +bool check_ps(CPULoongArchState *ent, uint8_t ps); +int get_physical_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx, int is_de= bug); +void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, + uint64_t *dir_width, target_ulong level); +hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + +#endif /* LOONGARCH_CPU_MMU_H */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b96429ffb1..990985708e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -17,6 +17,7 @@ #include "hw/qdev-properties.h" #include "exec/translation-block.h" #include "cpu.h" +#include "cpu-mmu.h" #include "internals.h" #include "fpu/softfloat-helpers.h" #include "csr.h" diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index e172b11ce1..2e8d3d7cfb 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -13,6 +13,7 @@ #include "exec/target_page.h" #include "internals.h" #include "cpu-csr.h" +#include "cpu-mmu.h" #include "tcg/tcg_loongarch.h" =20 void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index a7384b0d31..e50d109767 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -32,19 +32,6 @@ void restore_fp_status(CPULoongArchState *env); #endif =20 #ifndef CONFIG_USER_ONLY -enum { - TLBRET_MATCH =3D 0, - TLBRET_BADADDR =3D 1, - TLBRET_NOMATCH =3D 2, - TLBRET_INVALID =3D 3, - TLBRET_DIRTY =3D 4, - TLBRET_RI =3D 5, - TLBRET_XI =3D 6, - TLBRET_PE =3D 7, -}; - -bool check_ps(CPULoongArchState *ent, uint8_t ps); - extern const VMStateDescription vmstate_loongarch_cpu; =20 void loongarch_cpu_set_irq(void *opaque, int irq, int level); @@ -54,13 +41,6 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongA= rchCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); -int get_physical_address(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx, int is_de= bug); -void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, - uint64_t *dir_width, target_ulong level); -hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); - #endif /* !CONFIG_USER_ONLY */ =20 uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 28b1bb86bd..0d99e2c92b 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -16,6 +16,7 @@ #include "accel/tcg/cpu-ldst.h" #include "hw/irq.h" #include "cpu-csr.h" +#include "cpu-mmu.h" =20 target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val) { diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 3ea0e153b1..1f49619e7f 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -10,6 +10,7 @@ #include "qemu/guest-random.h" =20 #include "cpu.h" +#include "cpu-mmu.h" #include "internals.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824542475476.06827138319204; Fri, 18 Jul 2025 00:42:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfj1-0001ZS-SL; Fri, 18 Jul 2025 03:41:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW4-0002de-79 for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVz-0002jF-2n for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:22 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxQK2M93lox8ksAQ--.9335S3; Fri, 18 Jul 2025 15:28:12 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S7; Fri, 18 Jul 2025 15:28:11 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 5/9] target/loongarch: Add common function loongarch_check_pte() Date: Fri, 18 Jul 2025 15:28:03 +0800 Message-Id: <20250718072807.3585466-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824544987116600 Content-Type: text/plain; charset="utf-8" Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 8 ++++ target/loongarch/cpu_helper.c | 62 +++++++++++++++++++++++++++++++ target/loongarch/tcg/tlb_helper.c | 61 ++++-------------------------- 3 files changed, 78 insertions(+), 53 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 4c5cbd7425..7162e76238 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -19,7 +19,15 @@ enum { TLBRET_PE =3D 7, }; =20 +typedef struct mmu_context { + target_ulong vaddr; + uint64_t pte; + int ps; /* page size shift */ +} mmu_context; + bool check_ps(CPULoongArchState *ent, uint8_t ps); +int loongarch_check_pte(CPULoongArchState *env, hwaddr *physical, int *pro= t, + mmu_context *context, int access_type, int mmu_idx= ); int get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx, int is_de= bug); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 2e8d3d7cfb..c90e260566 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -44,6 +44,68 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t= *dir_base, } } =20 +int loongarch_check_pte(CPULoongArchState *env, hwaddr *physical, int *pro= t, + mmu_context *context, int access_type, int mmu_idx) +{ + uint64_t plv =3D mmu_idx; + uint64_t tlb_entry, tlb_ppn; + uint8_t tlb_ps, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + + tlb_entry =3D context->pte; + tlb_ps =3D context->ps; + + tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); + tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); + if (is_la64(env)) { + tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); + tlb_nx =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NX); + tlb_nr =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NR); + tlb_rplv =3D FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV); + } else { + tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_32, PPN); + tlb_nx =3D 0; + tlb_nr =3D 0; + tlb_rplv =3D 0; + } + + /* Check access rights */ + if (!tlb_v) { + return TLBRET_INVALID; + } + + if (access_type =3D=3D MMU_INST_FETCH && tlb_nx) { + return TLBRET_XI; + } + + if (access_type =3D=3D MMU_DATA_LOAD && tlb_nr) { + return TLBRET_RI; + } + + if (((tlb_rplv =3D=3D 0) && (plv > tlb_plv)) || + ((tlb_rplv =3D=3D 1) && (plv !=3D tlb_plv))) { + return TLBRET_PE; + } + + if ((access_type =3D=3D MMU_DATA_STORE) && !tlb_d) { + return TLBRET_DIRTY; + } + + /* Remove sw bit between bit12 -- bit PS*/ + tlb_ppn =3D tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1)); + *physical =3D (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | + (context->vaddr & MAKE_64BIT_MASK(0, tlb_ps)); + *prot =3D PAGE_READ; + if (tlb_d) { + *prot |=3D PAGE_WRITE; + } + if (!tlb_nx) { + *prot |=3D PAGE_EXEC; + } + + return TLBRET_MATCH; +} + static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *phy= sical, int *prot, target_ulong address) { diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 1f49619e7f..ca2fabfa6a 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -653,64 +653,19 @@ static int loongarch_map_tlb_entry(CPULoongArchState = *env, hwaddr *physical, int access_type, int index, int mmu_idx) { LoongArchTLB *tlb =3D &env->tlb[index]; - uint64_t plv =3D mmu_idx; - uint64_t tlb_entry, tlb_ppn; - uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + uint64_t tlb_entry; + uint8_t tlb_ps, n; + mmu_context context; =20 tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); n =3D (address >> tlb_ps) & 0x1;/* Odd or even */ =20 tlb_entry =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; - tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); - tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); - tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); - if (is_la64(env)) { - tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); - tlb_nx =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NX); - tlb_nr =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NR); - tlb_rplv =3D FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV); - } else { - tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_32, PPN); - tlb_nx =3D 0; - tlb_nr =3D 0; - tlb_rplv =3D 0; - } - - /* Remove sw bit between bit12 -- bit PS*/ - tlb_ppn =3D tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1)); - - /* Check access rights */ - if (!tlb_v) { - return TLBRET_INVALID; - } - - if (access_type =3D=3D MMU_INST_FETCH && tlb_nx) { - return TLBRET_XI; - } - - if (access_type =3D=3D MMU_DATA_LOAD && tlb_nr) { - return TLBRET_RI; - } - - if (((tlb_rplv =3D=3D 0) && (plv > tlb_plv)) || - ((tlb_rplv =3D=3D 1) && (plv !=3D tlb_plv))) { - return TLBRET_PE; - } - - if ((access_type =3D=3D MMU_DATA_STORE) && !tlb_d) { - return TLBRET_DIRTY; - } - - *physical =3D (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | - (address & MAKE_64BIT_MASK(0, tlb_ps)); - *prot =3D PAGE_READ; - if (tlb_d) { - *prot |=3D PAGE_WRITE; - } - if (!tlb_nx) { - *prot |=3D PAGE_EXEC; - } - return TLBRET_MATCH; + context.vaddr =3D address; + context.ps =3D tlb_ps; + context.pte =3D tlb_entry; + return loongarch_check_pte(env, physical, prot, &context, access_type, + mmu_idx); } =20 int loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical, --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824594458498.5396026253394; Fri, 18 Jul 2025 00:43:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfjU-0002nB-1c; Fri, 18 Jul 2025 03:42:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW4-0002dk-Et for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVz-0002jv-2W for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:24 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxDeOM93loysksAQ--.56481S3; Fri, 18 Jul 2025 15:28:12 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S8; Fri, 18 Jul 2025 15:28:12 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 6/9] target/loongarch: Use loongarch_check_pte() with page table walking Date: Fri, 18 Jul 2025 15:28:04 +0800 Message-Id: <20250718072807.3585466-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824595279116600 Content-Type: text/plain; charset="utf-8" Function loongarch_check_pte() can get physical address and access priviledge, it works on both TLB entry and pte entry. It can be used at page table walking. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index c90e260566..84191b5852 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -107,13 +107,15 @@ int loongarch_check_pte(CPULoongArchState *env, hwadd= r *physical, int *prot, } =20 static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *phy= sical, - int *prot, target_ulong address) + int *prot, target_ulong address, + int access_type, int mmu_idx) { CPUState *cs =3D env_cpu(env); target_ulong index, phys; uint64_t dir_base, dir_width; uint64_t base; int level; + mmu_context context; =20 if ((address >> 63) & 0x1) { base =3D env->CSR_PGDH; @@ -156,29 +158,11 @@ static int loongarch_page_table_walker(CPULoongArchSt= ate *env, hwaddr *physical, base =3D ldq_phys(cs->as, phys); } =20 - /* TODO: check plv and other bits? */ - - /* base is pte, in normal pte format */ - if (!FIELD_EX64(base, TLBENTRY, V)) { - return TLBRET_NOMATCH; - } - - if (!FIELD_EX64(base, TLBENTRY, D)) { - *prot =3D PAGE_READ; - } else { - *prot =3D PAGE_READ | PAGE_WRITE; - } - - /* get TARGET_PAGE_SIZE aligned physical address */ - base +=3D (address & TARGET_PHYS_MASK) & ((1 << dir_base) - 1); - /* mask RPLV, NX, NR bits */ - base =3D FIELD_DP64(base, TLBENTRY_64, RPLV, 0); - base =3D FIELD_DP64(base, TLBENTRY_64, NX, 0); - base =3D FIELD_DP64(base, TLBENTRY_64, NR, 0); - /* mask other attribute bits */ - *physical =3D base & TARGET_PAGE_MASK; - - return 0; + context.vaddr =3D address; + context.ps =3D dir_base; + context.pte =3D base; + return loongarch_check_pte(env, physical, prot, &context, access_type, + mmu_idx); } =20 static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, @@ -202,7 +186,8 @@ static int loongarch_map_address(CPULoongArchState *env= , hwaddr *physical, * legal mapping, even if the mapping is not yet in TLB. return 0 = if * there is a valid map, else none zero. */ - return loongarch_page_table_walker(env, physical, prot, address); + return loongarch_page_table_walker(env, physical, prot, address, + access_type, mmu_idx); } =20 return TLBRET_NOMATCH; --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824600998119.4093051500355; Fri, 18 Jul 2025 00:43:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfj3-0001cF-Ie; Fri, 18 Jul 2025 03:41:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW4-0002df-B5 for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVz-0002jh-22 for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:24 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxnOKN93lozcksAQ--.56658S3; Fri, 18 Jul 2025 15:28:13 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S9; Fri, 18 Jul 2025 15:28:12 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 7/9] target/loongarch: Use mmu idx bitmap method when flush tlb Date: Fri, 18 Jul 2025 15:28:05 +0800 Message-Id: <20250718072807.3585466-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824603185116600 Content-Type: text/plain; charset="utf-8" With API tlb_flush_range_by_mmuidx(), bitmap method of mmu idx should be used rather than itself. Also mmu idx comes from page table entry information rather current running mode. With page table entry, global bit for MMU_KERNEL_IDX, otherwise it is MMU_USER_IDX. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index ca2fabfa6a..76ec469341 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -101,8 +101,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) target_ulong addr, mask, pagesize; uint8_t tlb_ps; LoongArchTLB *tlb =3D &env->tlb[index]; - - int mmu_idx =3D cpu_mmu_index(env_cpu(env), false); + int mmu_idx; uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); @@ -118,12 +117,14 @@ static void invalidate_tlb_entry(CPULoongArchState *e= nv, int index) =20 if (tlb_v0) { addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; /* even */ + mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry0, TLBENTRY, PLV)); tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, mmu_idx, TARGET_LONG_BITS); } =20 if (tlb_v1) { addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & pagesize; /* odd= */ + mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry1, TLBENTRY, PLV)); tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, mmu_idx, TARGET_LONG_BITS); } --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824596448199.07075442041537; Fri, 18 Jul 2025 00:43:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfjb-00034E-30; Fri, 18 Jul 2025 03:42:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW5-0002eD-FQ for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfW0-0002jm-Rb for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxG6yN93loz8ksAQ--.51423S3; Fri, 18 Jul 2025 15:28:13 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S10; Fri, 18 Jul 2025 15:28:13 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 8/9] target/loongarch: Use correct page size when flush tlb Date: Fri, 18 Jul 2025 15:28:06 +0800 Message-Id: <20250718072807.3585466-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824597104116600 Content-Type: text/plain; charset="utf-8" On LoongArch system, there are two pages with one TLB entry. If the whole TLB entry is flushed, two pages will be flushed. Otherwise if tlb is flushed one by one, page size is one page at a time. Also virtual address of odd page is fixed here. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 76ec469341..47eb3ee318 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -112,20 +112,19 @@ static void invalidate_tlb_entry(CPULoongArchState *e= nv, int index) } =20 tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - pagesize =3D MAKE_64BIT_MASK(tlb_ps, 1); - mask =3D MAKE_64BIT_MASK(0, tlb_ps + 1); + pagesize =3D BIT_ULL(tlb_ps); + mask =3D ~((pagesize << 1) - 1) & TARGET_VIRT_MASK; + addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & mask; =20 if (tlb_v0) { - addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; /* even */ mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry0, TLBENTRY, PLV)); tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, mmu_idx, TARGET_LONG_BITS); } =20 if (tlb_v1) { - addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & pagesize; /* odd= */ mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry1, TLBENTRY, PLV)); - tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize, + tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize, mmu_idx, TARGET_LONG_BITS); } } --=20 2.39.3 From nobody Sat Nov 15 10:42:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752824561013946.2734560320756; Fri, 18 Jul 2025 00:42:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfjj-0003SJ-7d; Fri, 18 Jul 2025 03:42:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucfW4-0002db-6c for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucfVz-0002jp-2o for qemu-devel@nongnu.org; Fri, 18 Jul 2025 03:28:23 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxrnKO93lo0cksAQ--.27523S3; Fri, 18 Jul 2025 15:28:14 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxocKI93lo0QwcAA--.17387S11; Fri, 18 Jul 2025 15:28:13 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 9/9] target/loongarch: Use fine-grained tlb flush method Date: Fri, 18 Jul 2025 15:28:07 +0800 Message-Id: <20250718072807.3585466-10-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250718072807.3585466-1-maobibo@loongson.cn> References: <20250718072807.3585466-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxocKI93lo0QwcAA--.17387S11 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752824562667116600 Content-Type: text/plain; charset="utf-8" Qemu TCG provides some tlb flushing API, tlb can be flushed with specified mmu idx and virtual address. Here fine-grained tlb flush method is used. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 47eb3ee318..0842b067b1 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -385,7 +385,8 @@ void helper_tlbclr(CPULoongArchState *env) } } =20 - tlb_flush(env_cpu(env)); + /* Flush all user tlb entries */ + tlb_flush_by_mmuidx(env_cpu(env), BIT(MMU_USER_IDX)); } =20 void helper_tlbflush(CPULoongArchState *env) @@ -447,7 +448,9 @@ void helper_invtlb_all_asid(CPULoongArchState *env, tar= get_ulong info) tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0); } } - tlb_flush(env_cpu(env)); + + /* Flush all user tlb entries */ + tlb_flush_by_mmuidx(env_cpu(env), BIT(MMU_USER_IDX)); } =20 void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info, @@ -475,15 +478,19 @@ void helper_invtlb_page_asid(CPULoongArchState *env, = target_ulong info, if (!tlb_g && (tlb_asid =3D=3D asid) && (vpn =3D=3D (tlb_vppn >> compare_shift))) { tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0); + tlb_flush_range_by_mmuidx(env_cpu(env), vpn << (tlb_ps + 1), + BIT_ULL(tlb_ps + 1), + BIT(MMU_USER_IDX), TARGET_LONG_BITS); + break; } } - tlb_flush(env_cpu(env)); } =20 void helper_invtlb_page_asid_or_g(CPULoongArchState *env, target_ulong info, target_ulong addr) { uint16_t asid =3D info & 0x3ff; + int mmu_idx; =20 for (int i =3D 0; i < LOONGARCH_TLB_MAX; i++) { LoongArchTLB *tlb =3D &env->tlb[i]; @@ -505,9 +512,13 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *e= nv, if ((tlb_g || (tlb_asid =3D=3D asid)) && (vpn =3D=3D (tlb_vppn >> compare_shift))) { tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0); + mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry0, TLBENTRY, PLV)); + tlb_flush_range_by_mmuidx(env_cpu(env), vpn << (tlb_ps + 1), + BIT_ULL(tlb_ps + 1), + mmu_idx, TARGET_LONG_BITS); + break; } } - tlb_flush(env_cpu(env)); } =20 bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, --=20 2.39.3