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b=Xv9XfIOKvZpqNdHyoW2rMDCY+ENX2cldkeaN6XdKqNlgK6BsHkTHus01izM3hx7AC3P/D2MgiU/EFLmlTAe7yOeEquEohwi9OnlOezjXtl7yLGVw/CylQhGB/Mm8HPIfwnvDsXqCTHSuINOXpTlKFBtfYlOr0Qh977OjaPb43qyRboeiF5B23KcS82ehwRBxdmfc2zejowSB9ogc8zdwZfH89L5ss0SZvgHR3jsy2Z/IFTXIPb0C9RmhFRwu6uyh46aCpGGH6cENQnNh553ea+N6PXb9UJvTRzG8/7+EHB4141VJiPjshJRLGlprz3SAk/8L6hCDPBkRB7a4q3gfYw== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , Djordje Todorovic Subject: [PATCH v6 07/14] target/riscv: Add Xmipslsp instructions Thread-Topic: [PATCH v6 07/14] target/riscv: Add Xmipslsp instructions Thread-Index: AQHb9v6W1kBgImncQkWlgy4s7uggmQ== Date: Thu, 17 Jul 2025 09:38:44 +0000 Message-ID: <20250717093833.402237-8-djordje.todorovic@htecgroup.com> References: <20250717093833.402237-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20250717093833.402237-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c201::5; envelope-from=Djordje.Todorovic@htecgroup.com; helo=AS8PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1752746146505116600 Content-Type: text/plain; charset="utf-8" Add MIPS P8700 ldp, lwp, sdp, swp instructions. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- target/riscv/cpu.c | 3 + target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/insn_trans/trans_xmips.c.inc | 84 +++++++++++++++++++++++ target/riscv/xmips.decode | 23 +++++++ 5 files changed, 112 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d280648b55..fcaee6628e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -245,6 +245,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), + ISA_EXT_DATA_ENTRY(xmipslsp, PRIV_VERSION_1_12_0, ext_xmipslsp), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1377,6 +1378,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = =3D { MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false), MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false), + MULTI_EXT_CFG_BOOL("xmipslsp", ext_xmipslsp, false), =20 { }, }; @@ -3195,6 +3197,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.pmp =3D true, .cfg.ext_zba =3D true, .cfg.ext_zbb =3D true, + .cfg.ext_xmipslsp =3D true, .cfg.ext_xmipscbop =3D true, .cfg.ext_xmipscmov =3D true, .cfg.marchid =3D 0x8000000000000201, diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 9734963035..f35d477f27 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -39,7 +39,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cf= g __attribute__((__unus =20 static inline bool has_xmips_p(const RISCVCPUConfig *cfg) { - return cfg->ext_xmipscbop || cfg->ext_xmipscmov; + return cfg->ext_xmipscbop || cfg->ext_xmipscmov || cfg->ext_xmipslsp; } =20 static inline bool has_xthead_p(const RISCVCPUConfig *cfg) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 9ee0a099bb..b5195959b2 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -147,6 +147,7 @@ BOOL_FIELD(ext_xtheadsync) BOOL_FIELD(ext_XVentanaCondOps) BOOL_FIELD(ext_xmipscbop) BOOL_FIELD(ext_xmipscmov) +BOOL_FIELD(ext_xmipslsp) =20 BOOL_FIELD(mmu) BOOL_FIELD(pmp) diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_= trans/trans_xmips.c.inc index 620c59cc28..d0c1c9fd19 100644 --- a/target/riscv/insn_trans/trans_xmips.c.inc +++ b/target/riscv/insn_trans/trans_xmips.c.inc @@ -33,6 +33,12 @@ } \ } while (0) =20 +#define REQUIRE_XMIPSLSP(ctx) do { \ + if (!ctx->cfg_ptr->ext_xmipslsp) { \ + return false; \ + } \ +} while (0) + static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) { REQUIRE_XMIPSCMOV(ctx); @@ -49,6 +55,84 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) return true; } =20 +static bool trans_ldp(DisasContext *ctx, arg_ldp *a) +{ + REQUIRE_XMIPSLSP(ctx); + REQUIRE_64_OR_128BIT(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv dest0 =3D dest_gpr(ctx, a->rd); + TCGv dest1 =3D dest_gpr(ctx, a->rs3); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_y); + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ); + gen_set_gpr(ctx, a->rd, dest0); + + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ); + gen_set_gpr(ctx, a->rs3, dest1); + + return true; +} + +static bool trans_lwp(DisasContext *ctx, arg_lwp *a) +{ + REQUIRE_XMIPSLSP(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv dest0 =3D dest_gpr(ctx, a->rd); + TCGv dest1 =3D dest_gpr(ctx, a->rs3); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_x); + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL); + gen_set_gpr(ctx, a->rd, dest0); + + tcg_gen_addi_tl(addr, addr, 4); + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL); + gen_set_gpr(ctx, a->rs3, dest1); + + return true; +} + +static bool trans_sdp(DisasContext *ctx, arg_sdp *a) +{ + REQUIRE_XMIPSLSP(ctx); + REQUIRE_64_OR_128BIT(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data0 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv data1 =3D get_gpr(ctx, a->rs3, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_w); + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ); + + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ); + + return true; +} + +static bool trans_swp(DisasContext *ctx, arg_swp *a) +{ + REQUIRE_XMIPSLSP(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data0 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv data1 =3D get_gpr(ctx, a->rs3, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_v); + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL); + + tcg_gen_addi_tl(addr, addr, 4); + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL); + + return true; +} + static bool trans_pref(DisasContext *ctx, arg_pref *a) { REQUIRE_XMIPSCBOP(ctx); diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode index 697bf26c26..99c98d4084 100644 --- a/target/riscv/xmips.decode +++ b/target/riscv/xmips.decode @@ -8,5 +8,28 @@ # Reference: MIPS P8700 instructions # (https://mips.com/products/hardware/p8700/) =20 +# Fields +%rs3 27:5 +%rs2 20:5 +%rs1 15:5 +%rd 7:5 +%imm_9 20:9 +%imm_hint 7:5 +%imm_v 25:2 9:3 !function=3Dex_shift_2 +%imm_w 25:2 10:2 !function=3Dex_shift_3 +%imm_x 22:5 !function=3Dex_shift_2 +%imm_y 23:4 !function=3Dex_shift_3 + +# Formats +@r4_immv ..... .. ..... ..... ... ... .. ....... %rs2 %rs3 %imm_v %rs1 +@r4_immw ..... .. ..... ..... ... .. ... ....... %rs2 %rs3 %imm_w %rs1 +@r4_immx ..... ..... .. ..... ... ..... ....... %rs3 %imm_x %rs1 %rd +@r4_immy ..... .... ... ..... ... ..... ....... %rs3 %imm_y %rs1 %rd + +# *** RV64 MIPS Extension *** ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011 pref 000 imm_9:9 rs1:5 000 imm_hint:5 0001011 +ldp ..... .... 000 ..... 100 ..... 0001011 @r4_immy +lwp ..... ..... 01 ..... 100 ..... 0001011 @r4_immx +sdp ..... .. ..... ..... 101 .. 0000001011 @r4_immw +swp ..... .. ..... ..... 101 ... 010001011 @r4_immv --=20 2.34.1