From nobody Tue Sep 23 22:17:33 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752745910222750.1789908228445; Thu, 17 Jul 2025 02:51:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucLGp-0006hQ-HF; Thu, 17 Jul 2025 05:51:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucL0O-0001n6-FX; Thu, 17 Jul 2025 05:34:21 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucL0L-0001md-Ss; Thu, 17 Jul 2025 05:34:20 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 39714137CE8; Thu, 17 Jul 2025 12:34:04 +0300 (MSK) Received: from think4mjt.origo (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 1CA0D2491E2; Thu, 17 Jul 2025 12:34:12 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Mark Cave-Ayland , Peter Maydell , Paolo Bonzini , Michael Tokarev Subject: [Stable-10.0.3 40/65] target/i386: fix TB exit logic in gen_movl_seg() when writing to SS Date: Thu, 17 Jul 2025 12:33:36 +0300 Message-ID: <20250717093412.728292-1-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752745911789116600 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Before commit e54ef98c8a ("target/i386: do not trigger IRQ shadow for LSS")= , any write to SS in gen_movl_seg() would cause a TB exit. The changes introduced= by this commit were intended to restrict the DISAS_EOB_INHIBIT_IRQ exit to the= case where inhibit_irq is true, but missed that a DISAS_EOB_NEXT exit can still = be required when writing to SS and inhibit_irq is false. Comparing the PE(s) && !VM86(s) section with the logic in x86_update_hflags= (), we can see that the DISAS_EOB_NEXT exit is still required for the !CODE32 case= when writing to SS in gen_movl_seg() because any change to the SS flags can affe= ct hflags. Similarly we can see that the existing CODE32 case is still correct= since a change to any of DS, ES and SS can affect hflags. Finally for the gen_op_movl_seg_real() case an explicit TB exit is not needed because the s= egment register selector does not affect hflags. Update the logic in gen_movl_seg() so that a write to SS with inhibit_irq s= et to false where PE(s) && !VM86(s) will generate a DISAS_EOB_NEXT exit along wit= h the inline comment. This has the effect of allowing Win98SE to boot in QEMU once again. Signed-off-by: Mark Cave-Ayland Fixes: e54ef98c8a ("target/i386: do not trigger IRQ shadow for LSS") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2987 Link: https://lore.kernel.org/r/20250611130315.383151-1-mark.cave-ayland@il= ande.co.uk Reviewed-by: Peter Maydell Signed-off-by: Paolo Bonzini (cherry picked from commit 0f1d6606c28d0ae81a1b311972c5c54e5e867bf0) Fixes: 0f1d6606c2 ("target/i386: do not trigger IRQ shadow for LSS" in 10.0= .x) Signed-off-by: Michael Tokarev diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 50cf56175f..7e590ef79c 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2000,8 +2000,11 @@ static void gen_movl_seg(DisasContext *s, X86Seg seg= _reg, TCGv src, bool inhibit tcg_gen_trunc_tl_i32(sel, src); gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), sel); =20 - /* For move to DS/ES/SS, the addseg or ss32 flags may change. */ - if (CODE32(s) && seg_reg < R_FS) { + /* + * For moves to SS, the SS32 flag may change. For CODE32 only, cha= nges + * to SS, DS and ES may change the ADDSEG flags. + */ + if (seg_reg =3D=3D R_SS || (CODE32(s) && seg_reg < R_FS)) { s->base.is_jmp =3D DISAS_EOB_NEXT; } } else { --=20 2.47.2